KR20060016423A - Mask for sls and method of making thin film transistor using the same - Google Patents

Abstract

The present invention relates to a mask for sequential lateral solidification (SLS). The mask for sequential side solidification according to the present invention includes at least three slit rows including three slit rows in which slits are arranged in parallel with each other or two dummy slits and one dummy row in which no slits are formed. Wherein the slit row groups are arranged in parallel to each other, and the first slit row group includes the two slit rows and the dummy row, wherein the dummy rows are positioned between the two slit rows. It is characterized by. As a result, it is possible to reduce the problem that the variation in the characteristics of the thin film transistor is recognized according to the energy variation between the laser shots.

Description

Mask for sequential side solidification and manufacturing method of thin film transistor using same {{MASK FOR SLS AND METHOD OF MAKING THIN FILM TRANSISTOR USING THE SAME}

1 is a plan view showing a mask according to a first embodiment of the present invention,

2 is a view showing a polycrystalline silicon layer crystallized using a mask according to the first embodiment of the present invention,

3 is a plan view showing a mask according to a second embodiment of the present invention,

4 is a cross-sectional view showing the structure of a polycrystalline silicon thin film transistor according to the present invention,

5A to 5D are cross-sectional views illustrating a method of manufacturing a polycrystalline silicon thin film transistor according to an embodiment of the present invention.

Explanation of Signs of Major Parts of Drawings

20: first slit group 30: second slit group

40: third slit family

21, 23, 32, 33, 41, 42: slit row

22, 31, 43: dummy rows

The present invention relates to a sequential side solidification mask (hereinafter referred to as a mask) and a method of manufacturing a thin film transistor using the same. More particularly, the present invention relates to a mask in which dummy rows that do not pass laser beams are formed between slit rows through which laser beams are passed, and a method of manufacturing a thin film transistor using the same.

Due to the advantages of low voltage driving, light weight, wide viewing angle, and high-speed response, organic electroluminescence (EL) display devices, which are expected to be the next generation display devices, require the characteristics of thin film transistors in the pixel region to be uniform. .

This is because when the device characteristics of the thin film transistor are different from location to location, different brightnesses are displayed for each location with respect to the same image signal, resulting in uneven brightness of the entire screen.

In the organic EL, two transistors, a switching thin film transistor and a driving thin film transistor, are basically provided in the pixel portion. However, a compensation circuit using two or more thin film transistors is built in to compensate for variations in driving thin film transistor characteristics. Since this compensating circuit causes a reduction in the aperture ratio, it is desirable to reduce the number of thin film transistors in order to realize high resolution.

On the other hand, polycrystalline silicon having high mobility is used as the semiconductor layer of the thin film transistor of organic EL.                         

As a technique for forming a thin film of polycrystalline silicon, a two-shot crystallization method using a mask and completely melting an amorphous silicon region irradiated with a laser is widely used. This method is called sequential lateral solidification (SLS). This is because the grain of polycrystalline silicon grows in the direction perpendicular to the interface at the boundary between the liquid region to which the laser is irradiated and the solid region to which the laser is not irradiated.

However, in the SLS method, the characteristics of the grains are changed due to the energy difference between the laser shots, which causes variation in the characteristics of the thin film transistor. Such thin film transistor characteristic variation is perceived by the user's eye as a luminance difference while leading to a current characteristic. In other words, a mask mark occurs due to an energy difference between shots.

It is therefore an object of the present invention to provide a mask for forming a polysilicon layer so that no boundary is recognized in the energy deviation between laser shots.

Another object of the present invention is to provide a method of manufacturing a thin film transistor using the mask.

The above object is a mask for sequential lateral solidification (SLS), comprising three slit rows in which slits are arranged in parallel with each other or two slit rows and a dummy row in which no slits are formed. And at least three slit rows, wherein the slit rows are arranged parallel to each other, and the first slit row group includes the two slit rows and the dummy row, and the dummy rows include the two slits. It can be achieved by positioning between rows.

The slit row group adjacent to the first slit row group preferably includes the two slit rows and the dummy row.

In the slit row group adjacent to the first slit row group, it is preferable that the dummy row is located outside.

In the first slit row group, it is preferable that slits formed in the two slit rows are formed to correspond to each other.

It is preferable that the slit arrangement of at least one of the slit rows in the slit row group other than the first slit row group is arranged to deviate from the slits of the first slit row group.

The width of the slit row and the width of the dummy row are preferably the same.

Still another object of the present invention is a method of manufacturing a thin film transistor, the method comprising the steps of forming an amorphous silicon layer on a substrate material, and the slits are arranged in parallel with each other in the slit rows or two and And at least three slit row groups including one dummy row in which no slit is formed, wherein the slit row groups are arranged in parallel with each other, and the first slit row group among the slit row groups includes the two slit rows and the dummy row 1 And the dummy rows are formed by crystallizing the amorphous silicon layer by a sequential lateral solidification (SLS) method using a mask positioned between the two slit rows to form a polycrystalline silicon layer, and the polycrystalline silicon Patterning the layer to form a semiconductor layer, forming a gate insulating film on the semiconductor layer, and forming an image of the gate insulating film on the semiconductor layer Forming a gate electrode in the portion, implanting impurities into the semiconductor layer to form a source region and a drain region, forming an interlayer insulating film on the gate electrode, and forming the gate insulating film or the interlayer insulating film Etching to form contact holes exposing the source and drain regions, respectively, and forming source and drain electrodes respectively connected to the source and drain regions through the contact holes, respectively. Can be achieved.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

1 is a plan view showing the structure of a mask according to a first embodiment of the present invention.

The mask 10 is composed of three groups of slit rows 20, 30, 40. Each slit row group 20, 30, 40 is provided in strip shape, and is arrange | positioned in parallel with each other. Each slit row group 20, 30, 40 includes two slit rows 21, 23, 32, 33, 41, 42 and one dummy row 22, 31, 43, respectively. Slits 25, 26, 35, 36, 45, and 46 are arranged in parallel in each slit row 21, 23, 32, 33, 41, 42. The mask 10 is provided by depositing and patterning chromium on a quartz substrate material. The slit 25, 26, 35, 36, 45, 46 passes through a laser irradiated because chromium is not formed, and the light shielding area 51 is provided. The chromium is formed in the block to irradiate the laser. The light shielding area 51 includes spaces between the slits 25, 26, 35, 36, 45, and 46 and dummy rows 22, 31, and 43.

The first slit row group 20 includes a first slit row 21 and a second slit row 23 and a first dummy row 22 positioned therebetween. The slits 25 of the first slit row 21 and the slits 26 of the second slit row 23 are arranged to correspond to each other, that is, parallel.

The second slit row group 30 includes a third slit row 32 and a fourth slit row 33, and a second dummy row 31 positioned between the third slit row 32 and the first slit row group 20. ). That is, the second dummy row 31 is located at the outside when viewed in the second slit row group 30. The slits 35 of the third slit row 32 are arranged in parallel with each other so as to correspond to the slits 25 of the first slit row 21. On the other hand, the slits 36 of the fourth slit rows 33 are alternately formed with the slits 35 of the third slits 32.

The third slit row group 40 includes a fifth slit row 41, a sixth slit row 42, and a third dummy row 43 sequentially arranged. That is, the third pile row 43 is located outside the third slit row group 40. The slits 45 of the fifth slit row 41 and the slits 46 of the sixth slit row 42 are arranged in parallel with each other so as to correspond to the slits 36 of the fourth slit row 33.

Here, the length d1 of the slit 25 of the first slit row 21, the width d4 of the second dummy row 31, and the length d7 of the slit 45 of the fifth slit row 41 are Same as each other. In addition, the width d2 of the first pile 22 and the length d5 of the slit 35 of the third slit row 32 and the length d8 of the slit 46 of the sixth slit row 42 are Same as each other. In addition, the length d3 of the slit 26 of the second slit row 23, the length d6 of the slit 36 of the fourth slit row 33, and the width d9 of the third dummy row 43 are Same as each other.                     

When the lateral sequential solidification is performed using the mask 10 of the present invention, the relative movement distance between the mask 10 and the amorphous silicon layer is one of the slit row groups 10 and 20 as shown in FIG. 1. , 30) is equal to the width. For example, in the next laser shot, the amorphous silicon layer melted through the fourth slit row 41 is blocked from laser irradiation by the second pile row 31, and the first slit row 21 is removed from the subsequent laser shot. Because it melts through. The widths of the slits 25, 26, 35, 36, 45, and 46 and the lengths of the dummy rows 20, 30, and 40 may be changed under such conditions.

It is preferable that the width of each slit 25, 26, 35, 36, 45, 46 is the same.

The mask according to the first embodiment can be variously modified. For example, in the third slit row group 40, a separate slit row may be provided instead of the third dummy row 43. In addition, the slits 25, 26, 35, and the upper slit of some of the slit rows 21, 23, 32 are higher than the slits 36, 45, 46, the lower slit of the remaining slit rows 33, 41, 42. Formed. This is to ensure that there is no region that does not crystallize during the crystallization process of the amorphous silicon layer, which can be interchanged.

Hereinafter, the polycrystalline silicon layer crystallized using the mask according to the first embodiment of the present invention will be described with reference to FIG. 2.

A shot boundary 221 is formed in the polysilicon layer 200 according to the energy difference of the laser shot for crystallization. Crystallization zones 201 to 214 having different characteristics are formed between shot boundaries 221. The difference in properties between the crystallization zones 201 to 214 is due to the different energy between the laser shots.                     

The widths d11, d12, and d13 of each of the first three crystallization zones 201, 202, and 203 are the widths of the first slit rows 21 in the first slit row group 20 of the mask 10, respectively. It corresponds to the width of the small row 22 and the width of the second slit row 23. That is, the first three crystallization zones 201, 202, and 203 are the zones irradiated through the first slit row group 20. The following crystallization zones 204 to 209 also correspond to the second slit row group 30 and the third slit row group 40. 1st After the shot, the mask 10 is relatively moved by the moving distance (corresponding to d1 + d2 + d3) of FIG. 1 to irradiate the 2nd shot, so that the first three crystallization zones 201, 202, and 203 cannot be completely crystallized. After the 2nd shot, relative movement and laser irradiation are repeated.

Intact crystallization of the amorphous silicon layer is a crystallization region 206 in which both laser irradiation through the fourth slit row 33 having the lower slit 36 and laser irradiation through the upper slit 26 through the second slit row 23 are performed. Starts from).

As shown in FIG. 2, polycrystalline silicon having different characteristics is mixed in each crystallization region 206 to 214, which will be described with reference to Tables 1 and 2 below.

Table 1 shows through which slit rows 21, 23, 32, 33, 41, and 42 the crystallization regions 201 to 214 were crystallized according to the sequential laser shots. Dark markings indicate irradiation with a single laser shot. The portion where the slit rows 21, 23, 32, 33, 41, and 42 are not displayed indicates the portion where the laser beams are not irradiated by the dummy rows 22, 31, and 43. As shown in Table 1, each laser shot is repeated with three crystallization regions 201 to 214.                     

Hereinafter, the crystallization area 207 to which three shots are irradiated will be described as an example. The crystallization region 207 is irradiated to the laser through the fifth slit row 41 of the third slit row group 40 by the first shot. In the 2nd shot after moving the mask 10, the laser beam is not irradiated by covering the second dummy row 31 of the second slit row group 30. In the 3rd shot after moving the mask 10 again, a laser is irradiated through the 1st slit row 21 of the 1st slit row group 20. FIG. Since the fifth slit row 41 has the lower slit 45 and the first slit row 21 has the upper slit 25, the crystallization regions 207 are all crystallized.

As described above, three lasers are irradiated to the crystallization regions 206 to 214, but the first is blocked by the dummy rows 22, 31, and 43, so that the laser is not irradiated, and thus crystallized by two laser irradiations. The grains grow stably because the later laser irradiation is performed only through the upper slits 25, 26 and 35.

TABLE 1

Table 2 shows the two laser shots used for the crystallization of each crystallization region 206 to 214 and the laser shot for determining the characteristics of the polycrystalline silicon. The laser shot that determines the properties of the polycrystalline silicon is one of two laser shots to be irradiated later.

As shown in Table 2, the laser shots used for the crystallization of each crystallization region 206 to 214 are variously distributed. In particular, when looking at the laser shots for determining the characteristics, it can be seen that the same laser shots are not continuous in the order of irradiation of the laser shots.

TABLE 2

As described above, when the mask 10 according to the first exemplary embodiment of the present invention is used, crystallization regions 206 to 214 having different characteristics are mixed with each laser shot. Accordingly, the thin film transistor formed by using the polysilicon layer 200 as a semiconductor layer is mixed in characteristics, making it difficult to recognize the boundary.

3 is a plan view showing a mask 50a according to a second embodiment of the present invention. The point of difference with the mask 50 according to the first embodiment will be described below.

In the second slit row group 30a, the second pile row 33a is positioned between the fourth slit row group 32a and the third slit row group 40a. That is, the second pile row 33a is the same in the outer side as seen in the second slit row group 30a as in the first embodiment, but the position thereof is reversed. In the third slit row group 40a, the third pile row 41a is adjacent to the second pile row 33a.

The third slit row 31a of the second slit row group 30a has a lower slit 35a and the fourth slit row 32a has an upper slit 36a.

Hereinafter, a thin film transistor manufactured using the mask 10 according to the embodiment of the present invention will be described.

4 is a cross-sectional view illustrating a structure of a polycrystalline silicon thin film transistor according to an embodiment of the present invention.

As shown in FIG. 4, the buffer layer 111 is formed on the substrate material 110, and the semiconductor layer 130 is positioned on the buffer layer 111. The buffer layer 111 is mainly made of silicon oxide, and prevents alkali metal or the like in the substrate material 110 from entering the semiconductor layer 130. In the semiconductor layer 130, LDD layers (lightly doped domains 132a and 132b), a source region 133a, and a drain region 134b are formed around the channel portion 131. LDD layers 132a and 132b are n-doped and are formed to disperse hot carriers. On the other hand, the channel portion 131 is not doped with impurities, and the source region 133a and the drain region 134b are n + doped. A gate insulating layer 141 made of silicon oxide or silicon nitride is formed on the semiconductor layer 130, and a gate electrode 151 is formed on the gate insulating layer 141 on the channel portion 131. An interlayer insulating layer 152 is formed on the gate insulating layer 141 to cover the gate electrode 151. The gate insulating layer 141 and the interlayer insulating layer 152 are formed on the source region 133a and the drain of the semiconductor layer 130. It has contact holes 181 and 182 exposing region 134b. The contact hole 182 is disposed on the interlayer insulating layer 152 to face the source electrode 161 with the source electrode 161 and the gate electrode 151 connected to the source region 133a through the contact hole 181. The drain electrode 162 connected to the drain region 133b is formed through the.

Hereinafter, a method of manufacturing a polycrystalline silicon thin film transistor according to an embodiment of the present invention will be described.

5A to 5D are cross-sectional views illustrating a method of manufacturing a polycrystalline silicon thin film transistor according to an embodiment of the present invention.

First, as shown in FIG. 6A, the buffer layer 111 and the amorphous silicon layer 121 are deposited on the substrate material 110, and the amorphous silicon layer 121 is crystallized by the sequential side solid phase crystal method. At this time, a mask 10 according to an embodiment of the present invention is used.

In the polycrystalline silicon layer formed, the boundaries between the laser shots are not formed sequentially but in accordance with the irradiation order of the laser shots.

5B illustrates that the semiconductor layer 130 is formed by patterning the polycrystalline silicon layer on which crystallization is completed.

Subsequently, as illustrated in FIG. 5C, silicon oxide or silicon nitride is deposited to form a gate insulating layer 121. Subsequently, the gate electrode 151 is formed by depositing and patterning a conductive material for gate wiring. Next, n-type impurities are ion-implanted using the gate electrode 151 as a mask to form the channel portion 131, the LDD layers 132a and 132b, the source region 133a, and the drain region 134b in the semiconductor layer 130. do. There are various methods of manufacturing the LDD layers 132a and 132b. For example, the gate electrode 151 may be made of a double layer, and then a method of making an overhang through wet etching may be used.

Subsequently, as shown in FIG. 5D, an interlayer insulating layer 152 covering the gate electrode 151 is formed on the gate insulating layer 121, and then patterned together with the gate insulating layer 121 to form a source of the semiconductor layer 130. Contact holes 181 and 182 exposing the region 133a and the drain region 134b are formed.

Finally, the data wiring metal is deposited and patterned on the substrate material 110, and the source electrode 161 and the drain connected to the source region 133a and the drain region 134b through the contact holes 181 and 182, respectively. When the electrode 162 is formed, a thin film transistor as shown in FIG. 5 is completed.

As described above, according to the present invention, when using a polycrystalline silicon layer through sequential lateral solidification, a mask is provided so that the boundary between laser shots is not recognized. In addition, a method of manufacturing a thin film transistor using the mask is provided.

Claims (7)

In the mask for sequential lateral solidification (SLS), At least three slit rows comprising three slits arranged in parallel with one another in a slit or two slit rows and one dummy row in which no slits are formed; The slit group is arranged in parallel to each other, The first slit row group of the slit row group includes the two slit rows and the dummy row, and the dummy row is positioned between the two slit rows. The method of claim 1, And a slit row group adjacent to the first slit row group includes the two slit rows and the dummy row. The method of claim 2, In the slit row group adjacent to the first slit row group, And the dummy rows are located at the outer side. The method of claim 1, In the first slit group, And slit formed in the two slit rows to correspond to each other. The method of claim 4, wherein Slit arrangement of at least one of the slit rows in the slit row group other than the first slit row group, A mask for sequential side elevation according to claim 1, wherein the mask is arranged so as to deviate from slits in the first slit row group. The method of claim 1, And the width of the slit row and the width of the dummy row are the same. In the method of manufacturing a thin film transistor, Forming an amorphous silicon layer on the substrate material; At least three slit rows comprising three slits arranged in parallel with one another in a slit, or two slit rows and one dummy row in which no slits are formed, wherein the slit rows are parallel to each other And a first slit row group of the slit row groups includes the two slit rows and the dummy row, and the dummy rows are sequentially side-solidified (SLS) by using a mask positioned between the two slit rows. Crystallizing the amorphous silicon layer by a method to form a polycrystalline silicon layer; Patterning the polycrystalline silicon layer to form a semiconductor layer; Forming a gate insulating film on the semiconductor layer; Forming a gate electrode on the gate insulating film of the semiconductor layer; Implanting impurities into the semiconductor layer to form a source region and a drain region; Forming an interlayer insulating film on the gate electrode; Etching the gate insulating film or the interlayer insulating film to form contact holes exposing the source region and the drain region, respectively; Forming source and drain electrodes respectively connected to said source region and said drain region through said contact hole, respectively.

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