KR20060013278A - Method of fabricating a mim capacitor - Google Patents

Abstract

Provided is a method for manufacturing an M capacitor. The MMC capacitor manufacturing method includes forming a contact plug penetrating the interlayer insulating film. A titanium silicide layer is formed on an upper surface of the contact plug. The titanium remaining after the titanium silicide layer is formed is plasma treated using a nitride gas. The titanium nitride film formed by the natural oxide film and the nitriding treatment remaining on the titanium silicide film is removed by a cleaning process. An etch stop film and a molding film are sequentially formed on the interlayer insulating film which has undergone the cleaning process. The molding layer is patterned to form lower electrode contact holes exposing the titanium silicide layer on the contact plug. A lower electrode covering an inner wall of the lower electrode contact hole is formed. The molding layer is removed, and a dielectric layer and an upper electrode covering the lower electrode are sequentially formed.

Silicide, ohmic contact layer, wet etchant, penetration

Description

Method of fabricating a MIM capacitor

1A to 1F are cross-sectional views sequentially illustrating a method of manufacturing an M capacitor according to the present invention.

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing an M capacitor.

In general, a semiconductor memory device, particularly a dynamic random access memory (DRAM), is a memory device that stores data in a capacitor of a unit cell. That is, the unit cell of the DRAM is composed of one access transistor and one cell capacitor connected in series.

As the cell capacitor, a metal-insulator-silicon (MIS) structure has been conventionally applied. In the capacitor of the MIS structure, polysilicon is disposed as a storage electrode which is a lower electrode. Then, metal is disposed as a plate electrode which is an upper electrode. A dielectric layer is disposed between the storage electrode and the plate electrode. However, in the case of the MIS structure, an oxidation reaction occurs at an interface between the polysilicon electrode and the dielectric layer, thereby changing electrical characteristics. In addition, depending on the magnitude of the voltage applied to the polysilicon electrodes, the capacitor exhibits non-uniform capacitance. For example, when the capacitor electrodes are doped with n-type impurities and a negative voltage is applied to the upper electrode, holes are induced on the surface of the lower electrode. That is, a depletion layer may be formed on the surface of the lower electrode, and the width of the depletion layer changes according to the magnitude of the negative voltage. As a result, the capacitor capacitance is not constant and changes depending on the magnitude of the voltage applied to the electrodes. As a result, there is a disadvantage that it is not suitable for a semiconductor device having an analog circuit due to the nonlinear nature of the capacitance.

In order to prevent the depletion layer generated by using the lower electrode of the polysilicon, a MIM structure in which both the upper electrode and the lower electrode are formed of a metal layer has recently been applied. In particular, a structure in which the lower electrode is formed of a titanium nitride film (TiN) is applied. The capacitor having the titanium lower electrode has excellent electrical reliability because the resistivity is small and there is no parasitic capacitance caused by internal depletion.

However, as the titanium nitride layer (TiN) is used instead of the polysilicon layer used as the lower electrode material, the contact resistance increases at the lower surface of the titanium nitride layer and the polysilicon plug interface disposed thereunder, thereby deteriorating the operating characteristics of the device. . In order to improve such contact resistance, a method of forming a titanium silicide layer, which is an ohmic contact layer, on the plug upper surface is applied.                         

After forming a titanium silicide layer on the upper surface of the plug, a method of forming a lower electrode made of a metal layer is described in US Pat. No. 6,660,620 entitled "Method of forming noble metal pattern" by Lan et al. .).

According to US Pat. No. 6,660,620, a method of defining various semiconductor devices such as capacitors as a selective etching process of a metal layer, as well as a method of improving the accuracy of the metal layer etching process is provided. More specifically, an opening is formed in the first insulating layer 24. A polysilicon plug 50 is formed to fill the opening. Titanium silicide (TiSi ₂ ) is formed on the upper surface of the polysilicon plug. The second insulating layer 25 is formed on the first insulating layer 24. An opening is formed in the second insulating layer 25 to expose the titanium silicide. The capacitor lower electrode 60 covering the opening and the second insulating layer 25 is conformally formed. The dielectric layer 62 and the upper electrode 65 are sequentially formed on the lower electrode.

According to US Pat. No. 6,660,620, an increase in contact resistance can be prevented by forming a titanium silicide layer as an ohmic contact layer at the polysilicon plug and the lower electrode interface. After forming the ohmic contact layer formed on the upper surface of the polysilicon plug, that is, the titanium silicide layer TiSi ₂ , unreacted titanium remains. If the contact hole line width is larger than the plug in the state where the unreacted titanium remains, or misalignment occurs during contact hole patterning, the unreacted titanium becomes a penetration path of the wet etchant during the subsequent molding film wet etching process. As a result, an etchant penetrates into the lower first insulating layer, that is, the molding layer, thereby deteriorating electrical characteristics. Eventually, this can cause the storage node to collapse and cause bridges between the storage nodes.

The technical problem to be achieved by the present invention is to provide an M capacitor manufacturing method that can improve the reliability of the device by preventing the etching defect caused by the unreacted titanium.

The present invention for solving the above technical problem provides a method for manufacturing an M capacitor. The MMC capacitor manufacturing method includes forming a contact plug penetrating the interlayer insulating film. A titanium silicide layer is formed on an upper surface of the contact plug. The titanium remaining after the titanium silicide layer is formed is plasma treated using a nitride gas. The titanium nitride film formed by the natural oxide film and the nitriding treatment remaining on the titanium silicide film is removed by a cleaning process. An etch stop film and a molding film are sequentially formed on the interlayer insulating film which has undergone the cleaning process. The molding layer is patterned to form lower electrode contact holes exposing the titanium silicide layer on the contact plug. A lower electrode covering an inner wall of the lower electrode contact hole is formed. The molding layer is removed, and a dielectric layer and an upper electrode covering the lower electrode are sequentially formed.                     

In the ME capacitor manufacturing method, the upper electrode may be formed of any one or more selected from the group consisting of titanium, tungsten, tantalum, titanium nitride film and tungsten nitride film.

In the ME capacitor manufacturing method, the plasma treatment using the nitride gas can be performed using NH ₃ or N ₂ gas.

In the ME capacitor manufacturing method, forming the lower electrode includes forming a lower conductive layer covering the inner wall of the contact hole and the upper surface of the molding layer, and etching back the lower conductive layer to expose the upper surface of the molding oxide layer. can do.

In the MMC capacitor manufacturing method, the molding film removal process may be performed by a wet etching process using a LAL solution or HF solution.

In the MIM capacitor manufacturing method, the cleaning step may be performed using an HF cleaning solution.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the scope of the invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.                     

1A to 1F are co-sectional cross-sectional views sequentially illustrating a method of manufacturing an M capacitor according to the present invention.

Referring to FIG. 1A, an isolation layer 102 is formed to define an active region of a semiconductor substrate 100. The device isolation layer (not shown) may proceed in a conventional shallow trench isolation (STI) process. Next, the gate insulating film 102, the conductive film 104, and the metal silicide film 106 are sequentially formed. The conductive film 104 may be formed of a polysilicon film. The metal silicide film 106 may be formed of a tungsten film. The metal silicide layer 106, the conductive layer 104, and the gate insulating layer 102 are patterned by photolithography and etching to form a gate pattern 108. Low concentration impurity regions 110 are formed in the active region of the semiconductor substrate 100 by performing low concentration ion implantation using the gate pattern 108 and the isolation layer (not shown) as an ion implantation mask. An insulating film for a spacer may be conformally formed on the entire surface of the semiconductor substrate 100 on which the gate pattern 108 is formed. The insulating layer is patterned by an anisotropic etching process to form insulating layer spacers 112 on both sidewalls of the gate pattern 108.

High concentration impurity regions 114 are formed on the semiconductor substrate 100 by using high concentration ion implantation using the gate pattern 108 and the device isolation layer (not shown) having the insulating layer spacer 112 as an ion implantation mask. The low concentration impurity region 110 and the high concentration impurity region 114 are source / drain 116 regions of the transistor. The source or drain region 116 becomes a connection region of a capacitor or a connection region of a metal wiring.                     

Referring to FIG. 1B, an interlayer insulating layer 118 is formed on a resultant product in which a transistor including the gate pattern 108 and a source / drain region 116 is formed. A selective photolithography process is performed on the interlayer insulating layer 118 to form a contact hole 120 exposing any one of the source or drain regions 116.

A conductive film filling the contact hole 120 is formed on the interlayer insulating film 118. The conductive film is planarized using a chemical mechanical polishing process or the like to expose an upper surface of the interlayer insulating film 118. As a result, a contact plug 122 connected to the source or drain 118 is formed. The contact plug 122 is formed of a polysilicon film.

Referring to FIG. 1C, a titanium film is formed on the entire surface of the interlayer insulating film 118 including the contact plug 122. In addition, a silicide process is performed to form a titanium silicide layer 124 on an upper surface of the contact plug 122. The titanium silicide layer 124 is an ohmic contact layer between the contact plug 122 and a lower electrode to be formed subsequently, and serves to improve contact resistance.

Subsequently, titanium that has not reacted in the silicidation process may be removed by a conventional wet etching process. The titanium remaining after the wet etching process is subjected to plasma treatment using a nitride gas. NH ₃ or N ₂ gas may be used as the nitriding gas. By performing the nitride plasma process, since the titanium nitride film and the natural oxide film are formed on the upper surface of the titanium silicide layer 124 and the upper surface of the interlayer insulating layer 118, a cleaning process is performed to remove them. The cleaning step is carried out using a HF cleaning solution.

An etch stop layer 126 is formed on the contact plug 122, the titanium silicide layer 124, and the formed interlayer insulating layer 118. The etch stop layer 126 may use a silicon oxynitride layer (SiON) or a silicon nitride layer (SiN).

Referring to FIG. 1D, a molding layer 128 is formed on the etch stop layer 126. The molding layer 128 may be formed of PE-TEOS, BPSG, or PSG. The molding layer 128 may be formed of a material having a high wet etching selectivity with respect to the etch stop layer 126. The lower electrode contact hole 130 exposing the upper surface of the titanium silicide layer 124 is formed by performing patterning using the selective photolithography and etching processes of the molding layer 128 and the etch stop layer 126. A titanium nitride layer covering the lower electrode contact hole 130 and the surface of the molding layer 128 may be conformally formed. The titanium nitride film may be formed by any one selected from CVD, ALD, PECVD, and PEALD methods.

A sacrificial layer 132 is formed on the entire surface of the semiconductor substrate on which the titanium nitride layer is formed. The sacrificial layer 132 may be formed of a PE-TEOS, a BPSG, or a PSG layer. The sacrificial layer 132 may have a small etching selectivity with respect to the molding layer 128 so that the sacrificial layer 132 may be simultaneously removed when the molding layer and the sacrificial layer are removed. The sacrificial layer 132 and the titanium nitride layer are planarized by a chemical mechanical polishing process to expose the upper surface of the molding layer 128 to form a lower electrode 134. Alternatively, the lower electrode 134 may be formed to etch back the titanium nitride layer without exposing the sacrificial layer 132 to expose the upper surface of the molding layer 128.

Referring to FIG. 1E, the molding layer 128 and the sacrificial layer 132 are removed by a wet etching process. The wet etching process may be performed using a LAL wet etching solution or an HF wet etching solution. In this case, a titanium silicide layer 124, which is an ohmic contact layer, is formed on the polysilicon contact plug 122 in the process of removing the molding layer 128. In addition, since all of the unreacted titanium remaining on the interlayer insulating layer 118 is removed, even if a misalignment occurs during the contact hole etching process, wet during the process of removing the molding layer 128 and the sacrificial layer 132 is performed. Wet etchant does not penetrate into the interlayer insulating film 118. As a result, the penetration of the wet etchant into the interlayer insulating layer 118 is prevented, so that the storage node does not fall. As a result, the etching defects of the titanium silicide layer 124, which is the ohmic contact layer, and the collapse of the storage node are prevented, thereby preventing deterioration of electrical characteristics of the device.

Referring to FIG. 1F, a dielectric film 136 covering the lower electrode surface may be conformally formed. In this case, the dielectric layer 136 may be formed of one or more materials selected from the group of HfO ₂ , Al ₂ O ₃ , Ta ₃ O ₅ , La ₂ O ₃ , and ZrO ₂ . In order to improve characteristics of the dielectric layer 136, the dielectric layer 136 may be heat-treated or plasma treated. An upper electrode 138 is formed on the entire surface of the semiconductor substrate on which the dielectric layer 136 is formed. The upper electrode 138 may be formed of at least one selected from the group consisting of titanium, tungsten, tantalum, titanium nitride, and tungsten nitride.

According to the present invention, the unreacted titanium remaining after the formation of the titanium silicide layer is completely removed by plasma treatment using a nitride gas, thereby preventing the wet etching defect by blocking the wet etching solution penetration path, thereby preventing the storage node from falling down. As a result, the deterioration of the electrical characteristics of the device can be prevented.

Claims (7)

Forming a contact plug penetrating the interlayer insulating film, Forming a titanium silicide film on the upper surface of the contact plug, Plasma treatment of titanium remaining after the titanium silicide film is formed using a nitride gas, The titanium oxide film formed by the natural oxide film and the nitriding treatment remaining on the titanium silicide film is removed by performing a washing process, An etch stop film and a molding film are sequentially formed on the interlayer insulating film subjected to the cleaning process, Patterning the molding layer to form a lower electrode contact hole exposing the titanium silicide layer on the contact plug; Forming a lower electrode covering an inner wall of the lower electrode contact hole; Removing the molding film, And forming a dielectric film covering the lower electrode and the upper electrode in sequence. The method of claim 1, The upper electrode may be formed of at least one selected from the group consisting of titanium, tungsten, tantalum, titanium nitride film and tungsten nitride film. The method of claim 1, The upper electrode may be formed of at least one selected from the group consisting of titanium, tungsten, tantalum, titanium nitride film and tungsten nitride film. The method of claim 1, Plasma treatment using the nitriding gas is carried out using NH ₃ or N ₂ gas. The method of claim 1, Forming the lower electrode Forming a lower conductive layer covering the inner wall of the contact hole and the upper surface of the molding layer; And etching the lower conductive film to expose the upper surface of the molding oxide film. The method of claim 1, The molding film removal process is an M capacitor manufacturing method characterized in that the wet etching process using a LAL solution or HF solution. The method of claim 1, The washing step is a method of manufacturing the M capacitor, characterized in that carried out using a HF cleaning solution.

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