KR20060011453A - Method for enhancement in low illumination characteristics and reliabilty of cmos image sensor - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a CMOS image sensor, and in particular, an invention in which low light image characteristics and NBTI characteristics of a device are simultaneously improved. According to an aspect of the present invention, there is provided a method of manufacturing a CMOS image sensor, comprising: forming a gate oxide film and a gate polysilicon on a semiconductor substrate; Forming a first mask that opens only the region where the PMOS device is to be formed; Selectively implanting florin into a region where a PMOS device is to be formed using the first mask; Patterning a gate electrode on the semiconductor substrate and forming a photodiode; Forming an interlayer insulating film and a metal wiring on the semiconductor substrate; Forming a passivation film including a silicon nitride film on the metal wiring; Performing hydrogen heat treatment on the entire surface of the semiconductor substrate; And forming a color filter and a microlens.

CMOS image sensor, NBTI, low light characteristics, florin, hydrogen heat treatment, passivation film

Description

MOSH image sensor low light characteristics and reliability improvement {METHOD FOR ENHANCEMENT IN LOW ILLUMINATION CHARACTERISTICS AND RELIABILTY OF CMOS IMAGE SENSOR}             

1A to 1D are process cross-sectional views illustrating a CMOS image sensor manufacturing process according to the prior art;

Figures 2a to 2d is a cross-sectional view showing a CMOS image sensor manufacturing process according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

41 substrate 42 device isolation film

43 well region for normal device 44 well region of pixel region

45 gate insulating film 46 gate polysilicon

47: first mask 48: Deep-N ion implantation region

49: LDD region 50: silicon oxide film

51 silicon nitride film 52 source / drain regions

53: P0 ion implantation region 54: silicide

55: first insulating film 56: metal wiring                 

57 second insulating film 58 passivation film

59: hydrogen heat treatment

The present invention relates to a method for manufacturing a CMOS image sensor, and more particularly, to a method for manufacturing a reliable CMOS image sensor while improving image characteristics in a low light environment.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal. Among them, a charge coupled device (CCD) includes individual metal-oxide-silicon (MOS) capacitors. A device in which charge carriers are stored and transported in a capacitor while being in close proximity to each other. Complementary MOS image sensors use CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits. A device employing a switching scheme that creates MOS transistors as many as pixels and sequentially detects outputs using the MOS transistors.

Typically, such CMOS image sensor converts light into an electrical signal in a pixel array, which is composed of tens or millions of unit pixels composed of one photodiode (PD) and four MOS transistors. It is used to reproduce the image.

In addition, the CMOS image sensor includes a general logic circuit area for amplifying or controlling the image signal converted from the pixel array to an electrical signal.

1A to 1D are cross-sectional views illustrating a manufacturing process of a CMOS image sensor according to the prior art.

First, as shown in FIG. 1A, a trench trench isolation (STI) 12 is formed on the semiconductor substrate 11 to define an active region and a field region.

Subsequently, normal device well ion implantation is performed to form a normal device well region 13. Next, p-type and n-type impurities are selectively implanted into the substrate to control the threshold voltage of the transistor.

Next, after forming the well region 14 of the pixel region by performing device well ion implantation in the photodiode region, ion implantation is selectively performed to adjust the threshold voltage.

Next, as shown in FIG. 1B, a gate insulating film 15 is formed on the semiconductor substrate using a nitride oxide film (SiON), and a gate polysilicon 16 is formed thereon.

Next, a patterning process using an appropriate mask is performed to selectively etch the gate polysilicon and the gate insulating layer to form a gate electrode pattern on the semiconductor substrate.

Subsequently, Deep N ion implantation is performed in the region where the photodiode is to be formed to form the Deep N ion implantation region 17 on the side of the gate electrode.

Next, LDDs (Lightly Doped Drain) regions 18 are formed on both sides of some of the gate electrodes. For reference, the LDD region is not formed in the gate electrode adjacent to the photodiode (sometimes referred to as a transfer gate). Referring to FIG.

Next, a process of forming spacers on both sidewalls of the gate electrode is performed. That is, after the silicon oxide film 19 is formed on the semiconductor substrate including the patterned gate electrode, the silicon nitride film 20 is successively formed. Spacers having a structure in which the oxide film 19 and the nitride film 20 are stacked on the sidewalls are formed.

Next, when ion implantation of n-type impurities and p-type impurities is selectively performed using the spacer and gate electrode patterns described above, source / drain regions 21 are formed on both sides of the gate electrode.

Subsequently, a P-type ion implantation process is performed on the deep-N region 17 of the region where the photodiode is to be formed to form a thin P0 ion implantation region 22 between the surface of the semiconductor substrate and the Deep-N region 17. To form.

Next, to lower the electrical resistance, a self-aligned silicide 23 is formed on the surface of the exposed source / drain regions and the top of the gate electrode. Through the above process, a series of transistors and photodiodes are completed.

Next, as shown in FIG. 1D, after the interlayer insulating film 24 for electrical insulation is formed on the entire semiconductor substrate, the metal wiring 25 is formed on the interlayer insulating film 24.

In the CMOS image sensor, three or more layers of metal wirings are generally used, but FIG. 1D illustrates a case in which two layers of metal wirings are used. Although not indicated by reference numerals in FIG. 1D, it can be seen that an interlayer insulating film is formed on the upper portion of the metal wiring, and a via etching process is also performed.

After the metal wiring process is completed, the insulating film 26 is deposited on the upper portion thereof, and then, as shown in FIG. 1D, the hydrogen heat treatment process 27 is performed.

At this time, in order to improve the image characteristics under low light environment, the hydrogen heat treatment process is performed by increasing the hydrogen heat treatment temperature or increasing the heat treatment time.

Subsequently, a passivation film (not shown) forming process made of a silicon nitride film or the like is performed to protect the device from moisture and scratches, and then a series of processes such as a color filter and a microlens forming process are performed to provide a chip level process. It is finished.

Referring to the problems of the prior art as follows.

First, in the prior art, a silicon nitride oxide film (SiON) is used as the gate insulating film, in order to prevent boron from penetrating into the PMOS device. However, the nitrogen ion of the silicon nitride oxide film acts as a fixed trap charge to deteriorate the NBTI reliability of the PMOS device, and due to such a trap charge, image characteristics are degraded under low light conditions. .

Here, the NBTI (Negative Bias Temperature Instability) characteristics will be described.

When a semiconductor device is released into a product or manufactured as a test product, a stress test is performed to accelerate the stress state by applying a negative bias to the gate so that the substrate is inverted and raising the temperature. Refers to a reliability item that is evaluated under

The NBTI phenomenon is a phenomenon that occurs mainly in PMOS transistors, and when the device is in operation, positive charges are trapped at the interface between the gate insulating film and the silicon substrate, thereby degrading the characteristics of the device. It is also called the Mohs hot carrier effect.

In addition, in order for the charge accumulated in the photodiode to be converted into an image signal, as much charge as possible must be transferred from the photodiode to the sensing region. However, the transfer rate is reduced due to the influence of the above-described charge trap.

In addition, the hydrogen heat treatment after the metallization process helps to improve the image characteristics under low light environment by curing the silicon dangling bond formed on the semiconductor substrate. In addition to the above-mentioned nitrogen ions, since it plays an excessive positive fixed charge role, it causes a problem of further deteriorating the NBTI reliability characteristics of the PMOS device.                         

In addition, in order to solve the problem of using a silicon nitride oxide film (SiON) as the gate insulating film, when the oxide film is applied as the gate insulating film has the following problems.

That is, when the oxide film is applied as the gate insulating film, fixed trap charge due to nitrogen ion can be reduced, but a long time hydrogen is performed at high temperature to heal silicon dangling bonds generated during oxide film growth. A heat treatment process is necessary.

As such, when the hydrogen heat treatment process is performed at a high temperature for a long time, a problem of rapid increase in resistance of the metallization and silicide layers may occur, which may cause deterioration of NBTI characteristics of the PMOS device.

An object of the present invention is to provide a method for manufacturing a CMOS image sensor that simultaneously improves low light characteristics and NBTI characteristics by applying hydrogen heat treatment after a selective fluorine ion implantation process and a passivation film deposition. .

According to an aspect of the present invention, there is provided a method of manufacturing a CMOS image sensor, comprising: stacking a gate oxide film and a gate polysilicon on a semiconductor substrate; Forming a first mask that opens only the region where the PMOS device is to be formed; Selectively implanting florin into a region where a PMOS device is to be formed using the first mask; Patterning a gate electrode on the semiconductor substrate and forming a photodiode; Forming an interlayer insulating film and a metal wiring on the semiconductor substrate; Forming a passivation film including a silicon nitride film on the metal wiring; Performing hydrogen heat treatment on the entire surface of the semiconductor substrate; And forming a color filter and a microlens.

The present invention is to solve the above-mentioned problems of the prior art, and a selective fluorine ion implantation process and a hydrogen heat treatment process were applied after passivation film deposition.

That is, in the present invention, the fluorine ions, which can improve the NBTI reliability, are selectively implanted only in the PMOS region, and the hydrogen ions contained in the passivation film are penetrated together by the hydrogen heat treatment process, thereby allowing a large amount of hydrogen even in a low thermal process. The ions were able to heal the silicon dangling bonds, simultaneously improving low light image quality and NBTI reliability.

In addition, to improve the positive fixed trap charge generated when the oxide film used as the gate insulating film is grown, the NBTI reliability is improved by performing a high temperature heat treatment process after the gate insulating film is grown.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

2A through 2D are cross-sectional views illustrating a manufacturing process of a CMOS image sensor according to an exemplary embodiment of the present invention.

First, as shown in FIG. 2A, a trench trench isolation (STI) 42 is formed on the semiconductor substrate 41 to define an active region and a field region.

Subsequently, normal device well ion implantation is performed to form a normal device well region 43. Next, p-type and n-type impurities are selectively implanted into the substrate to control the threshold voltage of the transistor.

In addition, well ion implantation is performed in the photodiode region to form the well region 44 of the pixel region, and then ion implantation is selectively performed to adjust the threshold voltage.

Next, a gate insulating film 45 is formed on the semiconductor substrate 41 using an oxide film, and a gate polysilicon 46 is formed on the gate insulating film 45.

In an embodiment of the present invention, an oxide film is used instead of a silicon nitride oxide film as a gate insulating film, which is to reduce positive trap charge.

In addition, in order to solve the dangling bond increase problem that occurred when the oxide film was used as the gate insulating film, after the gate insulating film was formed, subsequent heat treatment was performed for 20 to 30 minutes at 900 to 1050 ° C, N2 or Ar atmosphere.

Next, as shown in FIG. 2A, after forming the first mask 47 that opens only the region where the PMOS device is to be formed, fluorine is selectively implanted using the first mask 47.

In the prior art, to improve the low light characteristics through hydrogen heat treatment, in this case, there was a problem that the NBTI characteristics of the device is very deteriorated. However, in the present invention, by selectively injecting fluorine ions only into the PMOS device region in which NBTI characteristics are a problem, superior NBTI characteristics can be obtained.

Florin ion implantation process according to an embodiment of the present invention uses the ion implantation energy of 10 keV and the doze of 5 × 10 ¹³ ~ 10 ¹⁶ atom / cm ² .

Next, after the first mask 47 is removed, the gate polysilicon 46 and the gate insulating layer 45 are selectively etched by performing a patterning process using an appropriate mask as shown in FIG. 2B to gate on the semiconductor substrate. An electrode pattern is formed.

Subsequently, Deep N ion implantation is performed in the region where the photodiode is to be formed to form the Deep N ion implantation region 48 on the side of the gate electrode.

Next, LDDs (Lightly Doped Drain) regions 49 are formed on both sides of some of the gate electrodes. For reference, the LDD region is not formed in the gate electrode adjacent to the photodiode (sometimes referred to as a transfer gate). Referring to FIG.                     

Next, as shown in FIG. 2C, a process of forming spacers on both sidewalls of the gate electrode is performed. That is, after the silicon oxide film 50 is formed on the semiconductor substrate including the patterned gate electrode, the silicon nitride film 51 is continuously formed. Subsequently, when the front etch back process is applied, the amount of gate electrode Spacers having a structure in which the oxide film 50 and the nitride film 51 are stacked on the sidewalls are formed.

Next, when ion implantation of n-type impurities and p-type impurities is selectively performed using the spacer and gate electrode patterns described above, source / drain regions 52 are formed on both sides of the gate electrode.

Subsequently, a P-type ion implantation process is performed on the Deep-N region 48 in the region where the photodiode is to be formed, thereby forming a thin P0 ion implantation region 53 between the surface of the semiconductor substrate and the Deep-N region 48. To form.

Next, to lower the electrical resistance, a self-aligned silicide 54 is formed on the surface of the exposed source / drain regions and on top of the gate electrode. Through the above process, a series of transistors and photodiodes are completed.

Next, as shown in FIG. 2D, the first insulating film 55 for electrical insulation is formed on the entire semiconductor substrate, and then the metal wiring 56 is formed on the first insulating film 55.

In the CMOS image sensor, three or more layers of metal wirings are generally used, but FIG. 2D illustrates a case in which two layers of metal wirings are used. Although not indicated by reference numerals in FIG. 2D, it can be seen that an interlayer insulating film is formed on the upper portion of the metal wiring, and a via etching process is also performed.

After the metallization process is completed, the deposition process of the second insulating film 57 is performed on the upper portion, and the passivation film 58 is formed on the second insulating film 57.

In one embodiment of the present invention, a plasma enhanced silicon nitride film is used as the passivation film. The passivation film forming process is performed at a temperature of 200 to 450 ° C., a pressure of 1 to 10 Torr, a power of 300 to 1000 W, and an SiH ₄ / NH ₃ atmosphere, and in particular, the concentration of hydrogen ions can be increased in the above-described process conditions. It is desirable to proceed under low temperature, high pressure, high power, and high gas flow.

In the prior art, the hydrogen heat treatment process was applied before the passivation film deposition, but in one embodiment of the present invention, the hydrogen heat treatment process was performed after the passivation film deposition. In addition, a silicon nitride film was used as the passivation film, and such a passivation film deposition process was also made to contain a large amount of hydrogen ions in the film.

This allows the hydrogen contained in the passivation film to penetrate together with the temperature during subsequent hydrogen annealing so that a large amount of hydrogen ions can heal the dangling bond even with a low thermal process, thereby simultaneously improving the low light characteristics and NBTI characteristics of the device. For sake.

After such a passivation film forming process, a hydrogen heat treatment process 59 is performed to heal dangling bonds generated on the silicon semiconductor substrate. The hydrogen heat treatment process according to an embodiment of the present invention may be performed at a temperature of 350 to 450 ° C., It proceeds in N2 / H2 atmosphere.                     

In the hydrogen heat treatment, as described above, hydrogen ions contained in the passivation film are also used for dangling bond healing.

Next, a series of processes such as color filter and microlens formation are performed to finish manufacturing chip-level CMOS image sensor.

In an embodiment of the present invention, the fluorine ion implantation process is performed before the gate electrode patterning, but in addition, the selective fluorine ion implantation process may be performed after the gate electrode is patterned, or may be performed together with the source / drain ion implantation or the first process. It may also proceed after the formation of the insulating film.

In the prior art, in order to improve low light characteristics such as dark current characteristics, it is necessary to increase the hydrogen heat treatment temperature or to apply hydrogen heat treatment for a long time. However, the resistance of the metal wiring and silicide increases rapidly, and the driving ability of the device is significantly reduced. there was.

However, in the present invention, since the hydrogen contained in the passivation film is used together in the hydrogen heat treatment process performed at a low temperature, the resistance of the metal wiring and the silicide can be prevented from increasing and at the same time, the low light characteristics of the device can be improved. .

In addition, when the hydrogen heat treatment is excessively performed by the conventional method, there is a problem in that the NBTI reliability of the PMOS device is degraded. However, in the present invention, by selectively implanting fluorine ions into the PMOS device region, the NBTI reliability is significantly improved compared to the prior art. Could.

In addition, in the present invention, since the oxide film is used as the gate insulating film, heat treatment is performed at high temperature after the gate insulating film is formed in order to cure the positive fixed trap charge generated during the oxide film growth.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

Applying the present invention to the CMOS image sensor, it is possible to improve the low light characteristics of the device without increasing the resistance of the metal wiring and silicide, and also has the advantage of improving the NBTI reliability of the device through selective fluorine ion implantation.

Claims (6)

In the method of manufacturing the CMOS image sensor, Stacking a gate oxide film and a gate polysilicon on a semiconductor substrate; Forming a first mask that opens only the region where the PMOS device is to be formed; Selectively implanting florin into a region where a PMOS device is to be formed using the first mask; Patterning a gate electrode on the semiconductor substrate and forming a photodiode; Forming an interlayer insulating film and a metal wiring on the semiconductor substrate; Forming a passivation film including a silicon nitride film on the metal wiring; Performing hydrogen heat treatment on the entire surface of the semiconductor substrate; And Forming a color filter and a microlens Method of manufacturing a CMOS image sensor comprising a. The method of claim 1, Selective ion implantation of the florin, 10 keV ion implantation energy and 5 × 10 ¹³ ~ 10 ¹⁶ atom / cm ² dose using a method of manufacturing a CMOS image sensor. The method of claim 1, Hydrogen heat treatment is performed on the entire surface of the semiconductor substrate, A method for manufacturing a CMOS image sensor, characterized in that it proceeds in a temperature of 350 ~ 450 ℃, N2 / H2 atmosphere. The method of claim 2 or 3, Stacking the gate oxide film and the gate polysilicon may include: After the gate oxide film is formed on a semiconductor substrate, further comprising the step of performing a subsequent heat treatment for 20 to 30 minutes in 900 ~ 1050 ℃, N2 or Ar atmosphere. The method of claim 2 or 3, Forming the passivation film, A passivation film forming step using a plasma-excited nitride film which proceeds at a low temperature of 200 to 450 ° C. The method of claim 5, Forming the passivation film, A passivation film forming process using a plasma excited nitride film which proceeds in a pressure of 1 to 10 Torr, a power of 300 to 1000 W, and a SiH ₄ / NH ₃ atmosphere.

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