KR20060006251A - Thin film transistor array panel - Google Patents

Abstract

The present invention relates to a thin film transistor array panel capable of improving image quality by greatly reducing vertical crosstalk. The liquid crystal display includes first and second pixel electrodes arranged in a row direction, first and second switching elements connected to the first and second pixel electrodes, and a storage electrode overlapping the first pixel electrode. First and second gate lines connected to the first and second switching elements, respectively, and extending in the row direction and disposed up and down or vice versa of the first and second pixel electrodes, and the first and second gate lines. A data line connected to a second switching element and extending in a column direction and disposed outside the first and second pixel electrodes, wherein the storage electrode is disposed between adjacent boundaries of the first pixel electrode and the second gate line; At least one boundary of is located. As a result, the influence of the electric field between the second gate line and the first pixel electrode is reduced, so that the capacitance of the parasitic capacitors generated therebetween is greatly reduced. As a result, the deterioration in image quality caused by the change of pixel voltage by the parasitic capacitor is greatly reduced. The picture quality of the display device is improved.

LCD, Invert, Dot Invert, Heat Invert, Cross Torque, Flicker, Data Driver, Data Line

Description

Thin Film Transistor Display Panels {THIN FILM TRANSISTOR ARRAY PANEL}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a structural diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

5 and 6 are cross-sectional views of the thin film transistor array panel of FIG. 4 taken along lines V-V ′ and VI-VI ′, respectively.

7 is a layout view of a thin film transistor array panel according to a comparative example of the present invention.

FIG. 8 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 4 taken along the line 'VIII'.

FIG. 9 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 7 taken along the line 'VIII'.

10 is a diagram illustrating a pixel array according to another exemplary embodiment of the present invention.

FIG. 11 is a layout view of a thin film transistor array panel for a liquid crystal display device having the pixel array shown in FIG. 10.

FIG. 12 is a cross-sectional view of the thin film transistor array panel of FIG. 11 taken along the line II-XII '.

The present invention relates to a thin film transistor array panel.

A typical liquid crystal display (LCD) includes two display panels provided with pixel electrodes and a common electrode, and a liquid crystal layer having dielectric anisotropy interposed therebetween. The pixel electrodes are arranged in a matrix and connected to switching elements such as thin film transistors (TFTs) to receive data voltages one by one in sequence. The common electrode is formed over the entire surface of the display panel and receives a common voltage. The pixel electrode, the common electrode, and the liquid crystal layer therebetween form a liquid crystal capacitor, and the liquid crystal capacitor becomes a basic unit that forms a pixel together with a switching element connected thereto.

In such a liquid crystal display, a voltage is applied to two electrodes to generate an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. In this case, in order to prevent degradation caused by an electric field applied to the liquid crystal layer for a long time, the polarity of the data voltage with respect to the common voltage is inverted frame by frame, row by pixel, or pixel by pixel.

 Among the data voltage inversion methods, when the polarity of the data voltage is inverted for each pixel (hereinafter referred to as "dot inversion"), a vertical flicker phenomenon or a vertical crosstalk phenomenon due to kickback voltage may occur. Reduced quality improves. However, since the polarities of the data voltages must be inverted for each predetermined row and predetermined column, the operation of applying the data voltage to the data line becomes complicated and the problem due to the signal delay of the data line becomes serious. As a result, manufacturing processes are complicated and manufacturing costs are increased, such as making data lines with low resistance materials to reduce signal delay.

On the other hand, when inverting the polarity of the data voltage for each predetermined column (hereinafter referred to as "column inversion"), the polarity of the data voltage flowing through one data line is inverted only for each frame, thereby greatly reducing the signal delay problem of the data line.

However, since thermal inversion does not maintain the advantages of dot inversion, the image quality of the liquid crystal display deteriorates due to vertical flicker and vertical crosstalk.

The liquid crystal display also includes a gate line for transmitting a gate signal for controlling a switching element, a data line for transmitting a data voltage for applying to a field generating electrode, a gate driver and a data driver for generating a gate signal and a data voltage. . The gate driver and the data driver are usually composed of a plurality of driving integrated circuit chips, and the number of such chips as small as possible is an important factor in reducing the production cost. In particular, data driving integrated circuit chips are more expensive than gate driving circuit chips, and therefore, the number of data driving integrated circuit chips needs to be further reduced.

Another object of the present invention is to provide a display device having both the advantages of thermal inversion and the advantages of dot inversion.

Another object of the present invention is to reduce the number of driving circuit chips to reduce the manufacturing cost of the display device.

Another object of the present invention is to improve the image quality of a display device.

According to an aspect of the present invention, a thin film transistor array panel includes first and second pixel electrodes arranged in a row direction, and first and second electrodes connected to the first and second pixel electrodes, respectively. A first electrode connected to the switching element, a sustain electrode overlapping the first pixel electrode, the first and second switching elements respectively, extending in the row direction, and disposed upside down or vice versa of the first and second pixel electrodes; A first and second gate lines, and a data line connected to the first and second switching elements and extending in a column direction and disposed outside the first and second pixel electrodes, wherein the first pixel electrode is provided. At least one boundary of the sustain electrode is positioned between and the adjacent boundary of the second gate line.

The boundary of the first pixel electrode is preferably positioned on the sustain electrode.

Preferably, the terminal line connecting the data line and the second switching element passes between the first pixel electrode and the second gate line.

According to another aspect of the present invention, a thin film transistor array panel includes first and second pixel electrodes arranged in a row direction, first and second switching elements connected to the first and second pixel electrodes, respectively, and the first First and second gate lines connected to the sustain electrode overlapping the pixel electrode, the first and second switching elements, respectively, extending in the row direction, and disposed up and down or vice versa of the first and second pixel electrodes; And a data line connected to the first and second switching elements, extending in a column direction, and disposed outside the first and second pixel electrodes to connect the data line and the second switching element. The terminal line passes between the first pixel electrode and the second gate line.

In the above features, the second gate line may transfer a gate-on voltage following the first gate line, and the sustain electrode may be formed on the same layer as the gate line.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.                     

A thin film transistor array panel according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention. 3 is a structural diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 includes a plurality of display signal lines G ₁ -G _2n , D ₁ -D _m, L1 _, L2, connected to the plurality of display signal lines _, and arranged in an approximately matrix form in an equivalent circuit. ).

Display signal line (G ₁ -G _2n , D ₁ -D _m , L1 _and L2 are a plurality of gate lines G ₁ -G _2n that transmit gate signals (also referred to as "scan signals"), data lines D ₁ -D _m that transmit data signals, and dummy lines L1, L2). The gate lines G ₁ -G _2n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m and the dummy lines L1 and L2 extend substantially in the column direction and are substantially parallel to each other. .

As shown in FIG. 3, a liquid crystal display device is disposed above the liquid crystal panel assembly 300 including the gate lines G ₁ -G _2n , the data lines D ₁ -D _m , and the dummy lines L1 and L2. The printed circuit board (PCB) 550 is provided with circuit elements such as a signal controller 600, a driving voltage generator 700, and a gray voltage generator 800 for driving the LEDs. The miseon (L1) is maximum in the vicinity of the left edge, and more miseon (L2) of the liquid crystal panel assembly 300 will extend substantially in the row direction in the vicinity of the right-most edge of the liquid crystal panel assembly 300 and the data lines (D ₁ - Almost parallel to D _m ).

The liquid crystal panel assembly 300 and the PCB 550 are electrically and physically connected to each other through a flexible printed circuit (FPC) substrate 510.

The flexible circuit board 510 is provided with a data driver integrated circuit chip 540 constituting the data driver 500, and a plurality of data transfer lines 521 are formed. The data transfer line 521 is connected to a plurality of data lines D ₁ -D _m formed on the liquid crystal panel assembly 300 through the contact portion C1 to transfer corresponding data voltages.

Signal transmission lines 522a, 522b, 523a, and 523b are formed on the left and rightmost FPC boards 510. The signal transmission lines 522a, 522b, 523a, and 523b are connected to the signal transmission lines 551a and 551b formed on the PCB 550 through the contact portion C3.

The signal transmission line 522a formed on the leftmost FPC substrate 510 is connected to the leftmost data line D ₁ through the contact portion C2, and is also connected to the signal transmission line 551a through the contact portion C3. 523a is connected to the dummy line L2 through the contact portion C1.

In addition, the signal transmission line 523b formed on the rightmost FPC board 510 is connected to the rightmost data line D _m through the contact portion C2, and also through the contact portion C3. It is connected to 551b and 523b, and is connected to the dummy line L1 through the contact part C1.

Each pixel includes a switching element Q connected to the display signal lines G ₁ -G _2n , D ₁ -D _m and the dummy lines L1 and L2, a liquid crystal capacitor C _LC , and a storage capacitor connected thereto. (storage capacitor) (C _ST ). The holding capacitor C _ST can be omitted as necessary.

The switching element Q, such as a thin film transistor, is provided in the lower panel 100. The three-terminal element, the control terminal and the input terminal thereof, includes a gate line G ₁ -G _{2 n} , a data line DD _m , and a dummy line. (L1, L2), and the output terminal is connected to the liquid crystal capacitor (C _LC ) and the holding capacitor (C _ST ).

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 190 and 270 may be formed in a linear or bar shape.

The storage capacitor C _ST , which serves as an auxiliary part of the liquid crystal capacitor C _LC , is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage V _com is applied to this separate signal line. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

As shown in FIG. 3, the pair of gate lines G ₁ and G ₂ , G ₃ and G _{4,... Are} arranged above and below the pixel electrodes 190 in a row. The data lines D ₁ -D _m are arranged one by one between the pixel electrodes 190 in two columns, that is, one data line is disposed between the pair of pixel columns. The connection between the gate lines G ₁ -G _2n and the data lines D ₁ -D _m and the pixel electrode 190 will be described in more detail.

A plurality of pairs of gate lines G ₁ -G _2n connected to the top and bottom of the pixel electrode 190 may be connected to the corresponding pixel electrode 190 through a switching element Q formed above or below each pixel electrode 190. Connected.

That is, in the odd-numbered pixel row, the switching element Q located on the left side of the data lines D ₁ -D _{m is} connected to the gate lines G ₁ , G ₅ , G ₉ ,... The switching element Q located on the right side of the data line D ₁ -D _{m is} connected to the gate lines G ₂ , G ₆ , G ₁₀ ,... On the other hand, the upper gate line (G ₃ , G ₇ , G ₁₁ , ...) and the lower gate line (G ₄ , G ₈ , G ₁₂ , ...) positioned in the even-numbered pixel row and the switching element (Q) The concatenation is the opposite of odd-numbered pixel rows. That is, the switching element Q located on the right side of the data line D ₁ -D _{m is} connected to the gate lines G ₃ , G ₇ , G ₁₁ ,... Located above, and the data line ( The switching element Q on the left side of the center D ₁ -D _{m is} connected to the gate lines G ₄ , G ₈ , G ₁₂ ,...

The pixel electrode 190 located on the left side of the pixel electrodes 190 in the odd-numbered row with respect to the data lines D ₁ -D _m is connected to the immediately adjacent data lines D ₁ -D _m through the switching element Q. The pixel electrode 190 connected to the right side of the data line D ₁ -D _m is connected to the data line adjacent to each other through the switching element Q. The pixel electrode 190 located on the left side of the even-numbered pixel electrodes 190 around the data lines D ₁ -D _m is connected to the immediately preceding data line through the switching element Q. The data line The pixel electrode 190 positioned on the right side of the center D ₁ -D _m is connected to the immediately adjacent data line through the switching element Q. In addition, the pixel electrodes 190 of the even row of the first column are connected to the dummy line L1 connected to the last data line D _m , and the pixel electrodes 190 of the odd row of the last column are connected to the first data line ( It is connected to the connecting line L2 connected to D ₁ ).

As described above, the switching element Q formed in each pixel can be more easily connected to the connected data lines D ₁ -D _m or the dummy lines L1 and L2, that is, the connection length can be as short as possible. Formed in position. Therefore, in the arrangement shown in FIG. 3, the position of the switching element Q changes every pixel row. That is, to the right of the odd-numbered pixels located in the left side of the pixel pair in the row data lines (D ₁ -D _m) had a switching element (Q) on the right upper end portion is formed on the data lines (D ₁ -D _m) The switching element Q is formed in the lower right portion of the pixel.

On the other hand, the formation positions of the switching elements Q of the pixels located in the even rows are opposite to the formation positions of the adjacent pixel rows. That is, the right side of the even-numbered pixels located in the left side of the pixel pair in the row data lines (D ₁ -D _m) is formed on the switching element (Q) at the bottom left, and the data lines (D ₁ -D _m) The switching element Q is formed in the upper left portion of the pixel.

When the connection between the pixel electrode 190 and the data lines D ₁ -D _m shown in FIG. 3 is arranged, in each pixel row, the switching elements Q of two pixels positioned between two adjacent data lines are the same data line. Is connected to. That is, the switching elements Q of two pixels formed between two data lines in an odd pixel row are connected to the data line positioned on the right side, and the switching elements Q of two pixels formed between two data lines in an even pixel row. ) Is connected to the data line on the left.

The arrangement shown in FIG. 3 is just one example, and the connection between the pixel electrodes 190 and the data lines D ₁ -D _m and the gate lines G ₁ -G _{2n in the} odd and even rows are mutually different. It can be changed and can also have other connections.

On the other hand, to implement color display, each pixel uniquely displays one of the three primary colors (spatial division) or each pixel alternately displays the three primary colors over time (time division) so that the desired color can be selected by the spatial and temporal sum of these three primary colors. To be recognized. 2 shows that each pixel includes a red, green, or blue color filter 230 in a region corresponding to the pixel electrode 190 as an example of spatial division. Unlike FIG. 2, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

3, the color filters 230 are arranged in the order of red, green, and blue in the row direction, and each pixel column forms a stripe arrangement including only the color filter 230 of one color.

A polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the two display panels 100 and 200 of the liquid crystal panel assembly 300.

Next, the structure of the thin film transistor array panel, which is the lower panel 100 of the liquid crystal panel assembly 300, will be described in detail with reference to FIGS. 4 to 6.

4 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIGS. 5 and 6 are cross-sectional views taken along lines V-V ′ and VI-VI ′ of the thin film transistor array panel of FIG. 4, respectively.

A plurality of gate lines 121a and 121b and a plurality of storage electrode lines 131 are formed on an insulating substrate 110 such as transparent glass.

The gate lines 121a and 121b mainly extend in the horizontal direction, and a part of the gate lines 121a protrude downward or upward to form the gate electrodes 124a and 124b. In addition, one end portion 129 of the gate lines 121a and 121b is widened for connection with another layer or an external device. The two gate lines 121a and 121b are paired adjacent to each other. The top gate line 121b and the bottom gate line 121a may not be paired.

Each storage electrode line 131 is separated from the gate lines 121a and 121b and connects a plurality of sets of storage electrodes 133a to 133d which are connected to each other to form a pair of rectangles, and a pair of storage electrode connection parts 135a and 135b. Include.

One set of storage electrodes 133a to 133d includes a pair of first storage electrodes 133a and a second storage electrode 133b which mainly extend in a horizontal direction, and a pair of third storage electrodes that mainly extend in a vertical direction ( 133c and a fourth sustain electrode 133d extending therebetween and extending in the vertical direction. The first to third storage electrodes 133a to 133c are disposed one by one on both the left and right sides of the fourth storage electrode 133d to form a rectangle sharing the fourth storage electrode 133d. It has a rotational symmetry of 180 degrees about the center of the electrode 133d.

The storage electrode connector 135 connects adjacent storage electrodes 133c of two sets of adjacent storage electrodes 133a-133d, and the storage electrode 133a is bent near the gate electrode 124.                     

A predetermined voltage such as a common voltage applied to the common electrode 270 of the other display panel 200 of the liquid crystal display device is applied to the sustain electrode line 131.

The gate lines 121a and 121b and the sustain electrode line 131 are made of aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, and copper-based metals such as copper (Cu) and copper alloys. Metal, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta) and titanium (Ti). However, the gate lines 121a and 121b and the storage electrode line 131 may include two layers having different physical properties, that is, a lower layer (not shown) and an upper layer (not shown) thereon. The upper layer may have a low resistivity metal such as aluminum (Al) or an aluminum alloy such as aluminum or silver to reduce signal delay or voltage drop between the gate lines 121a and 121b and the storage electrode line 131. (Ag) or a silver alloy, such as a silver-based metal, copper (Cu), or a copper-based metal such as a copper alloy. In contrast, the underlayer is a material having excellent contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as chromium, molybdenum (Mo), molybdenum alloys, tantalum (Ta), or titanium (Ti) Or the like. A good example of a combination of a bottom film and a top film is a chromium / aluminum-neodymium (Nd) alloy.

Side surfaces of the gate lines 121a and 121b and the storage electrode line 131 are inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30-80 °.

A gate insulating layer 140 made of silicon nitride (SiN _x ) is formed on the gate lines 121a and 121b and the storage electrode line 131.

On the gate insulating layer 140, a plurality of island-like semiconductors 152, 154a, and 154b made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si), polycrystalline silicon, or the like are formed. The semiconductors 154a and 154b are positioned on and cover the gate electrodes 124a and 124b, respectively, and the semiconductor 154a extends to cover the neighboring gate line 121a and the sustain electrode connection 135a. In addition, the semiconductor 152 covers the sustain electrode connection part 135b.

A plurality of isotropic ohmic contacts 162, 163a, and 163b formed on a top surface of the semiconductors 152, 154a, and 154b made of a material such as n + hydrogenated amorphous silicon that is heavily doped with silicide or n-type impurities. , 165a, 165b) are formed. The contact members 163a / 163b and the contact members 165a / 165b are paired and positioned on the island-like semiconductors 154a / 154b.

Side surfaces of the semiconductors 152, 154a, and 154b and the ohmic contacts 162, 163a, 163b, 165a, and 165b are also inclined with respect to the surface of the substrate 110, and the inclination angle is 30-80 °.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 162, 163a, 163b, 165a, and 165b and the gate insulating layer 140, respectively.

The data line 171 mainly extends in the vertical direction and crosses the gate lines 121a and 121b and the storage electrode connectors 135a and 135b and transmits a data voltage. The end portion 179 of each data line 171 is extended in width for connection with another layer or an external device. A plurality of branches extending from the data lines 171 toward the drain electrodes 175a and 175b respectively form the source electrodes 173a and 173b, and one end of the drain electrodes 175a and 175b is linear but the other The other end is extended in width to connect with the other layer and is positioned on the sustain electrode 133a. The source electrode 173b is bent to partially wrap the linear end of the drain electrode 175a, and the source electrode 173a approaches the adjacent adjacent drain electrode 175a across the two adjacent gate lines 121a and 121b. It is bent to partially wrap the linear end of the drain electrode 175a.

The gate electrodes 124a / 124b, the source electrodes 173a / 173b, and the drain electrodes 175a / 175b together with the island-like semiconductors 154a / 154b form a thin film transistor (TFT), and the channel of the thin film transistor ( Channels are formed in the island-like semiconductors 154a / 154b between the source electrodes 173a / 173b and the drain electrodes 175a / 175b.

The data line 171 and the drain electrodes 175a and 175b may be made of a molybdenum-based metal, a refractory metal such as chromium, tantalum, or titanium, and include a lower layer having a low resistance and a lower layer having good contact characteristics. It can have a multilayer film structure.

Like the gate line 121, the data line 171 and the drain electrodes 175a and 175b are inclined at an angle of about 30 to 80 degrees, respectively.

The ohmic contacts 162, 163a, 163b, 165a, and 165b exist only between the semiconductors 152, 154a, and 154b thereunder and the data lines 171 and drain electrodes 175a and 175b thereon and have contact resistances. It serves to lower.

As described above, the island-type semiconductors 152, 154a, and 154b have a gate line at a portion where the data line 171 or the drain electrodes 175a and 175b meet the gate line 121 and the storage electrode lines 133a-133d and 135. Disconnection of the data line 171 is prevented by covering the boundary between the 121 and the storage electrode lines 133a to 133d and 135.

A passivation layer 180 is formed on the data line 171, the drain electrodes 175a and 175b, and the exposed portions of the semiconductors 152, 154a and 154b. The passivation layer 180 may be formed of a-Si: C: O, a-Si: O: organic material having excellent planarization characteristics and photosensitivity, or formed by plasma enhanced chemical vapor deposition (PECVD). It consists of low dielectric constant insulating material of dielectric constant below 4.0, such as F, or silicon nitride which is an inorganic material. Alternatively, the passivation layer 180 may be formed of a double layer of organic material and silicon nitride.

The passivation layer 180 is provided with a plurality of contact holes 185 and 182 exposing the drain electrodes 175a and 175b and the end portion 179 of the data line 171, respectively, and the gate insulating layer 140. In addition, a plurality of contact holes 181 exposing the end portion 129 of the gate line 121 are formed.

A plurality of pixel electrodes 190 made of ITO or IZO and a plurality of contact assistants 81 and 82 are formed on the passivation layer 180.

The pixel electrode 190 is physically and electrically connected to the drain electrodes 175a and 175b through the contact hole 185 to receive a data voltage from the drain electrodes 175a and 175b. The pixel electrode 190 to which the data voltage is applied generates an electric field together with the common electrode 270 of the other display panel 200 to which the common voltage V _com is applied, thereby creating a liquid crystal layer 3 between the two electrodes 190 and 270. Rearrange the liquid crystal molecules.

In addition, the pixel electrode 190 and the common electrode 270 form a liquid crystal capacitor C _LC to maintain the applied voltage even after the thin film transistor is turned off, and in parallel with the liquid crystal capacitor C _LC to enhance the voltage holding capability. The storage capacitor C _ST connected to each other is formed by overlapping the pixel electrode 190 and the neighboring storage electrode line 131.

The pixel electrode 190 covers the extended ends of the drain electrodes 175a and 175b and the storage electrode 133a, and partially overlaps the storage electrodes 133b, 133c and 133d so that the boundary line of the pixel electrode 190 is maintained. It is located on the electrodes 133b, 133c, and 133d. As such, the storage electrode 133b is exposed between the gate lines 121a and 121b and the boundary line between the pixel electrode 190 and the pixel electrode 190 due to the parasitic capacitance between the pixel electrode 190 and the gate line 121a. Reduces the voltage fluctuations.

The contact auxiliary members 81 and 82 are connected to the end portions 129 of the gate lines 121a and 121b and the end portions 179 of the data lines 171 through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 complement and protect the adhesiveness between the end portions 129 and 179 of the gate lines 121a and 121b and the data line 171 and the external device. When a gate driver (not shown) for applying a scan signal to the gate lines 121a and 121b is integrated on the display panel, the contact member 81 may include the end portion 129 and the gate driver of the gate lines 121a and 121b. It may serve as a connecting member for connecting and may be omitted from time to time.

According to another embodiment of the present invention, a transparent conductive polymer may be used as the material of the pixel electrode 190, and in the case of a reflective liquid crystal display, an opaque reflective metal may be used. In this case, the contact assistants 81 and 82 may be made of a material different from the pixel electrode 190, in particular, ITO or IZO.

An alignment film (not shown) may be coated on the pixel electrode 190 to align the liquid crystal layer.

Referring back to FIG. 1, the gray voltage generator 800 generates two sets of gray voltages related to transmittance of a pixel. One of the two sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The gate driver 400 is connected to the gate lines G ₁ -G _2n of the liquid crystal panel assembly 300 to receive a gate signal formed by a combination of a gate on voltage V _on and a gate off voltage V _off from the outside. It is applied to the gate lines G ₁ -G _2n and consists of a plurality of integrated circuits.

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 to select the gray voltage from the gray voltage generator 800 and apply the gray voltage to the pixel as a data signal.

A plurality of gate drive integrated circuits or data drive integrated circuits may be mounted on the FPC substrate in the form of a chip to attach the FPC substrate to the liquid crystal panel assembly 300, or directly attach these integrated circuits onto the glass substrate without using the FPC substrate. It may be attached (chip on glass, COG mounting method), and a circuit performing the same function as these integrated circuits may be formed directly on the liquid crystal panel assembly 300 together with the thin film transistor of the pixel.

The signal controller 600 controls operations of the gate driver 400 and the data driver 500.

The display operation of such a liquid crystal display device will now be described in detail.

The signal controller 600 is configured to control the input image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical synchronization signal Vsync and a horizontal synchronization signal ( Hsync, main clock MCLK, and data enable signal DE are provided. Based on the input image signals R, G and B of the signal controller 600 and the input control signals, the image signals R, G and B are properly processed according to the operating conditions of the liquid crystal panel assembly 300, and the gate control signal After generating the CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to The processing of the image signals R, G, and B here includes rearranging the image data R, G, and B according to the pixel arrangement of the liquid crystal panel assembly illustrated in FIG. 3.

The gate control signal (CONT1) is at least one clock signal for controlling the output time and the output voltage of the gate-on voltage (V _on) state four start signal (STV) and a gate-on voltage (V _on) indicating the start of output, such as It includes.

The data control signal CONT2 includes a horizontal synchronization start signal STH indicating the start of transmission of the image data DAT, a load signal TP for applying a corresponding data voltage to the data lines D ₁ -D _m , and a common voltage ( V inverted signal (RVS), data clock signal (HCLK), etc. to invert the polarity of the data voltage for the _com (hereinafter referred to as "polarity of the data voltage by reducing the polarity of the data voltage for the common voltage"), etc. do.

The data driver 500 sequentially receives a set of image data DATs for half of the pixels in a row according to the data control signal CONT2 from the signal controller 600, and the gray voltage from the gray voltage generator 800. The grayscale voltage corresponding to each image data DAT is selected to convert the image data DAT into a corresponding data voltage, and then apply the grayscale voltage to the corresponding data lines D ₁ -D _m .

The gate driver 400 sequentially applies the gate-on voltage V _on to the gate lines G ₁ -G _2n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G. _The switching element Q connected to _2n ) is turned on so that the data voltage applied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

The difference between the data voltage applied to the pixel and the common voltage V _com is shown as the charging voltage of the liquid crystal capacitor C _LC , that is, the pixel voltage. The arrangement of the liquid crystal molecules varies according to the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

The data driver 500 and the gate driver 400 repeat the same operation based on a 1/2 horizontal period (or "1 / 2H") (one period of the horizontal synchronization signal Hsync). In this way, the gate-on voltage V _on is sequentially applied to all the gate lines G ₁ -G _2n during one frame to apply the data voltage to all the pixels. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame ("frame inversion). ").

In addition to the frame inversion, the data driver 500 inverts the polarities of the data voltages descending on the neighboring data lines D ₁ -D _m in one frame, thereby changing the polarities of the pixel voltages to which the data voltages are applied. However, as shown in FIG. 3, since the connection between the pixels and the data lines D ₁ -D _m varies, the polarity inversion pattern of the data driver 500 and the pixel voltage appearing on the screen of the liquid crystal panel assembly 300 are reversed. The pattern looks different. In the following, the inversion in the data driver 500 is referred to as driver inversion, and the inversion that appears on the screen is called an inversion.

Referring to FIG. 3 again, an inversion form according to an embodiment of the present invention will be described in detail.

In FIG. 3, the driver inversion is a column inversion, and the data voltage flowing in one data line is always the same polarity, the data voltage flowing in two neighboring data lines is the opposite polarity, and the apparent inversion is 1 × 2 dot inversion.

As such, when the apparent inversion causes the dot inversion, the difference in the luminance due to the kickback voltage appears when the pixel voltage is positive and negative, and thus the vertical line defect is reduced.

Next, a structure of a thin film transistor array panel according to a comparative example of the present invention will be described in detail with reference to FIGS. 7 and 9. 8 and 9 will be described in detail with respect to the difference between one embodiment of the present invention and a comparative example.

7 is a layout view of a thin film transistor array panel according to a comparative example of the present invention. FIG. 8 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 4 taken along the line 'VIII'. 9 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 7 taken along the line 'VIII'.

Referring to FIG. 7, the structure of the thin film transistor array panel 100 according to the comparative example of the present invention is similar to that shown in FIG. 4.

 That is, the plurality of gate lines 121a and 121b including the plurality of gate electrodes 124, the storage electrodes 133a, 133b, 133c, and 133d and the storage electrode connecting parts 135a and 135b are disposed on the substrate 110. A plurality of sustain electrode lines 131 are formed, and the gate insulating layer 140, the plurality of island semiconductors 152, 154a, and 154b, and the plurality of ohmic contacts 162, 163a, 163b, 165a, and 165b are sequentially formed thereon. Formed. A plurality of data lines 171 and a plurality of drain electrodes 175a and 175b are formed on the ohmic contacts 162, 163a, 163b, 165a, and 165b and the gate insulating layer 140, and a passivation layer 180 is formed thereon. It is. A plurality of contact holes 181 and 182 are formed in the passivation layer 180 and the gate insulating layer 140, and a plurality of pixel electrodes 190 and a plurality of contact auxiliary members 82 and 81 are formed on the passivation layer 180. It is.

However, in the liquid crystal display of FIGS. 4 and 8, only a part of the pixel electrode 190 overlaps the sustain electrode 133b. While the boundary of the pixel electrode 190 is positioned on the storage electrode 133b, in the liquid crystal display of FIGS. 7 and 9, the pixel electrode 190 completely covers the storage electrode 133b to form the pixel electrode 190. The boundary is located between the sustain electrode 133b and the gate electrode 121a.

Therefore, in the liquid crystal display of FIGS. 4 and 8, the distance d1 between the pixel electrode 190 and the gate lines 121a and 121b is set to the pixel electrode 190 of the liquid crystal display of FIGS. 7 and 9. Farther than the distance d2 between the gate lines 121a and 121b, the capacitance of the parasitic capacitor formed between them is reduced, thereby reducing the kickback voltage. Therefore, the variation of the pixel voltage due to the kickback voltage is reduced, thereby reducing the phenomenon of vertical stripes.

Next, another embodiment of the present invention will be described in detail with reference to FIGS. 10 to 12.

FIG. 10 is a diagram illustrating a pixel array according to another exemplary embodiment. FIG. 11 is a layout view of a thin film transistor array panel for a liquid crystal display device having the pixel array illustrated in FIG. 10, and FIG. 12 is a thin film transistor array panel of FIG. 11. Here is a cross-sectional view taken along the line II-XII '.

Referring to FIG. 11, the structure of the thin film transistor array panel 100 according to the comparative example of the present invention is similar to that of FIG. 4.

A plurality of gate lines 121a and 121b including the plurality of gate electrodes 124, the storage electrodes 133a, 133b, 133c, and 133d on the substrate 110, and the plurality of gate electrodes 124a and 135b, respectively. The storage electrode line 131 is formed, and the gate insulating layer 140, the plurality of island-like semiconductors 152, 154a, and 154b, and the plurality of ohmic contacts 162, 163a, 163b, 165a, and 165b are sequentially formed thereon. have. A plurality of data lines 171 and a plurality of drain electrodes 175a and 175b are formed on the ohmic contacts 162, 163a, 163b, 165a, and 165b and the gate insulating layer 140, and a passivation layer 180 is formed thereon. It is. A plurality of contact holes 181 and 182 are formed in the passivation layer 180 and the gate insulating layer 140, and a plurality of pixel electrodes 190 and a plurality of contact auxiliary members 82 and 81 are formed on the passivation layer 180. It is.

The pixel arrangement shown in FIG. 10 is almost similar to the pixel arrangement shown in FIG. 3, and only the position of the source terminal line connected to the switching element Q has been changed. That is, in FIG. 10, a source terminal line extending from each data line D ₁ -D _m extends between the pixel electrode 190 and the gate lines G2, G4, G6,... In contrast, in FIG. 3, the source terminal line extends between neighboring gate lines G1 and G2, G3 and G4,...

Therefore, the electric field formed between the gate lines 121a is blocked by this source terminal line, and the capacitance of the parasitic capacitor therebetween is greatly reduced.

Next, referring to Table 1, when designing the thin film transistor array panel 100 of the first embodiment shown in FIG. 4, the second embodiment shown in FIG. 11, and the comparative example shown in FIG. 7, respectively, The capacitance of the parasitic capacitor Cpg generated between the electrode and the gate line and the amount of reduction of the pixel voltage due to the kickback voltage will be described.

Comparative example Example 1 Example 2 Cpg 0.0043pf 0.0002pf 0.0001pf Pixel voltage reduction amount 140 mV 8 mV 4.6 mV

As can be seen from Table 1, the capacity of the parasitic capacitor Cpg was significantly reduced in Examples 1 and 2 compared to the comparative example. In addition, it can be seen that the capacity of the parasitic capacitor Cpg of Example 2 is reduced by about half compared to the capacity of the parasitic capacitor Cpg of Example 1. The amount of reduction of the pixel voltage was also greatly reduced in the case of Example 1 and Example 2 compared to the comparative example, and the case of Example 2 was reduced by about half compared to the case of Example 1.

As a result, the deterioration of image quality due to the parasitic capacitor Cpg in Examples 1 and 2 is significantly less than that of the comparative example, and in the case of Example 2, the adverse effect of the parasitic capacitor Cpg is significantly greater than that of Example 1. It can be seen that the decrease.

 As described above, when the position of the data line to which the switching elements are connected between adjacent pixel rows is changed, the apparent inversion may be 1 × 2 dot inversion even though the driver inversion is a column inversion method. Therefore, since the polarity of the data voltage is determined and applied from the data driver by the column inversion method, the material selection width of the data line is increased, and the manufacturing process is easy to simplify, and since the apparent inversion is dot inversion, the image quality is improved. Furthermore, since the number of data lines is reduced, the number of expensive data driving circuit chips connected thereto is also reduced, which greatly reduces the manufacturing cost of the display device.

In addition, the influence of the electric field between the gate line and the pixel electrode is reduced, so that the capacitance of the parasitic capacitors generated therebetween is greatly reduced. As a result, the deterioration of the image quality caused by the change of the pixel voltage by the parasitic capacitor is greatly reduced, thereby improving the image quality of the display device. Improves.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (8)

First and second pixel electrodes arranged in a row direction, First and second switching elements connected to the first and second pixel electrodes, respectively, A storage electrode overlapping the first pixel electrode; First and second gate lines connected to the first and second switching elements, respectively, and extending in the row direction and disposed up and down or vice versa of the first and second pixel electrodes; and A data line connected to the first and second switching elements and extending in a column direction and disposed outside the first and second pixel electrodes Including, At least one boundary of the sustain electrode is positioned between an adjacent boundary between the first pixel electrode and the second gate line. Thin film transistor array panel. In claim 1, The boundary of the first pixel electrode is disposed on the sustain electrode. The method of claim 1 or 2, And the second gate line transfers a gate-on voltage following the first gate line. In claim 3, The sustain electrode is formed on the same layer as the gate line. In claim 1, And a terminal line connecting the data line and the second switching element to pass between the first pixel electrode and the second gate line. First and second pixel electrodes arranged in a row direction, First and second switching elements connected to the first and second pixel electrodes, respectively, A storage electrode overlapping the first pixel electrode; First and second gate lines connected to the first and second switching elements, respectively, and extending in the row direction and disposed up and down or vice versa of the first and second pixel electrodes; and A data line connected to the first and second switching elements and extending in a column direction and disposed outside the first and second pixel electrodes Including, And a terminal line connecting the data line and the second switching element to pass between the first pixel electrode and the second gate line. In claim 6, And the second gate line transfers a gate-on voltage following the first gate line. In claim 6 or 7, The sustain electrode is formed on the same layer as the gate line.

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