KR20060028539A - Thin film transistor array panel and liquid crystal display - Google Patents

Abstract

The present invention relates to a thin film transistor array panel, comprising: a plurality of pixel electrodes, a plurality of sustain electrodes at least partially overlapping the pixel electrodes, a plurality of switching elements connected to the pixel electrodes, and connected to the switching elements, And a plurality of gate lines arranged two per pixel electrode row, and a plurality of data lines connected to the switching element and arranged one per two pixel electrode columns. Each of the plurality of switching elements includes a gate electrode, a source electrode, and a drain electrode, and the drain electrode includes an extension part overlapping the sustain electrode. The sustain electrode includes a plurality of sustain electrode portions connected to each other to form one rectangular ring, and the extension part overlaps the sustain electrode portion while following the plurality of sustain electrode portions. As a result, the capacitance of the storage capacitor is increased, thereby reducing the pixel voltage variation generated between the pixels due to the parasitic capacitance variation, thereby reducing the deterioration in image quality of the display device.

LCD, Invert, Dot Invert, Heat Invert, Cross Torque, Parasitic Capacitance, Holding Capacitance

Description

Thin Film Transistor Panels & Liquid Crystal Display {THIN FILM TRANSISTOR ARRAY PANEL AND LIQUID CRYSTAL DISPLAY}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a structural diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

5 to 7 are cross-sectional views of the thin film transistor array panel of FIG. 4 taken along lines V-V ′, VI-VI ′, and VII-VII ′, respectively.

8 is a diagram illustrating a pixel array according to another exemplary embodiment of the present invention.

FIG. 9 is a layout view of a thin film transistor array panel for a liquid crystal display device having the pixel array shown in FIG. 8.

10 is a layout view of a thin film transistor array panel according to another exemplary embodiment of the present invention.

FIG. 11 is a cross-sectional view of the thin film transistor array panel of FIG. 10 taken along the line XI-XI ′.

12 is an equivalent circuit diagram for parasitic capacitance occurring between two pixel electrodes.

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to thin film transistor array panels and liquid crystal displays (LCDs).

A general liquid crystal display device includes two display panels including a pixel electrode and a common electrode and a liquid crystal layer having dielectric anisotropy interposed therebetween. The pixel electrodes are arranged in a matrix and connected to switching elements such as thin film transistors (TFTs) to receive data voltages one by one in sequence. The common electrode is formed over the entire surface of the display panel and receives a common voltage. The pixel electrode, the common electrode, and the liquid crystal layer therebetween form a liquid crystal capacitor, and the liquid crystal capacitor becomes a basic unit that forms a pixel together with a switching element connected thereto.

In such a liquid crystal display, a voltage is applied to two electrodes to generate an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. In this case, in order to prevent degradation caused by an electric field applied to the liquid crystal layer for a long time, the polarity of the data voltage with respect to the common voltage is inverted frame by frame, row by pixel, or pixel by pixel.

In such a liquid crystal display, a voltage is applied to two electrodes to generate an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image. In this case, in order to prevent deterioration caused by the application of an electric field in one direction to the liquid crystal layer for a long time, the polarity of the data voltage with respect to the common voltage is inverted frame by frame, row by pixel, or pixel by pixel.

In the method of manufacturing a display panel for a liquid crystal display device, a pattern such as a wiring or a contact hole is formed by patterning by a photolithography process using a mask, and a plurality of display panels for display devices are formed on one mother substrate, and photo etching is performed. After completing the pattern through the process, the parent substrate is separated into a display panel.

In the photolithography process, when the active area in which the pattern is formed on the mother substrate is larger than the mask size, a step and repeat process is performed by dividing the active area to form a pattern in the active area. Split exposure is required. In this case, the actual shot may cause distortion such as shift, rotation, and distortion of the mask, so that the shots are not aligned correctly, and thus the parasitic capacitance difference between each wiring and the pixel electrode between the shots is different. Or a pattern position difference occurs.

Since the difference in parasitic capacitance and the position of the pattern causes the difference in the electrical characteristics and the aperture ratio of each region, the difference in screen brightness at the boundary between shots results in poor stitching or flicker. Cause problems. Here, flicker is a flicker phenomenon caused by a difference in the effective voltage applied to the liquid crystal between frames based on a common voltage. Various causes of flicker have been suggested, but one of them is a kickback voltage. to be. This kickback voltage is caused by the parasitic capacitance present between the gate electrode and the drain electrode of the thin film transistor. If the distortion, such as mask transition, rotation, and torsion, occurs between the gate electrode and the drain electrode in different shots, The capacity varies from area to area, which causes the screen to flicker.

In order to reduce image quality deterioration due to the kickback voltage, the polarity of the data voltage may be reversed for each pixel among the inversion methods of the data voltage (hereinafter referred to as "dot inversion"). However, since the polarities of the data voltages must be inverted for each predetermined row and predetermined column, the operation of applying the data voltage to the data line becomes complicated and the problem due to the signal delay of the data line becomes serious. As a result, manufacturing processes are complicated and manufacturing costs are increased, such as making data lines with low resistance materials to reduce signal delay.

On the other hand, when inverting the polarity of the data voltage for each predetermined column (hereinafter referred to as "column inversion"), the polarity of the data voltage flowing through one data line is inverted only for each frame, thereby greatly reducing the signal delay problem of the data line.

However, since thermal inversion does not maintain the advantages of dot inversion, the image quality of the liquid crystal display is still deteriorated due to flicker.

The liquid crystal display also includes a gate line for transmitting a gate signal for controlling a switching element, a data line for transmitting a data voltage for applying to a field generating electrode, a gate driver and a data driver for generating a gate signal and a data voltage. . The gate driver and data driver are usually composed of a plurality of driving integrated circuit chips, and the number of such chips as small as possible is an important factor in reducing the production cost. In particular, data driving integrated circuit chips are more expensive than gate driving circuit chips, and therefore, the number of data driving integrated circuit chips needs to be further reduced.

An object of the present invention is to provide a display device having both the advantages of thermal inversion and the advantages of dot inversion.

Another object of the present invention is to reduce the number of driving circuit chips to reduce the manufacturing cost of the display device.

Another object of the present invention is to improve the image quality of a display device.

Another technical problem to be achieved by the present invention is to ensure a uniform parasitic capacitance between the gate electrode and the drain electrode.

Another technical problem to be achieved by the present invention is to increase the auxiliary dose.

According to an aspect of the present invention, a thin film transistor array panel includes a plurality of pixel electrodes arranged in a matrix form, a plurality of storage electrodes at least partially overlapping the pixel electrodes, and connected to the pixel electrodes. A plurality of switching elements, a plurality of gate lines connected to the switching elements and extending in a row direction and arranged two per row of pixel electrodes, and connected to the switching elements and extending in a column direction and having two A plurality of data lines disposed one per pixel electrode column, each of the plurality of switching elements being connected to a gate electrode connected to the gate line, a source electrode connected to the data line, and a pixel electrode; And a drain electrode, wherein the drain electrode is in contact with the sustain electrode. It includes an extension to.

In addition, a switching element connected to two pixel electrodes arranged in a row direction between two adjacent data lines may be connected to the same data line, and switching elements connected to vertically adjacent pixel electrodes in one pixel electrode column may be different from each other. It may be connected to the data line.

The switching elements connected to at least two pixel electrodes are preferably connected to gate lines disposed above and below.

The terminal line connecting the data line and the switching element may pass between two adjacent gate lines.

Each of the pixel electrodes has a first boundary line close to the data line and a second boundary line far from the data line, the switching element is positioned near the second boundary line of the pixel electrode, and one terminal line is disposed at two pixels. It is good to be connected.

 According to another aspect of the present invention, a liquid crystal display includes a plurality of pixel electrodes arranged in a matrix form, a plurality of storage electrodes at least partially overlapping the pixel electrodes, a plurality of switching elements connected to the pixel electrodes, and the switching. A plurality of gate lines connected to the element and extending in a row direction and arranged two per row of pixel electrodes, and one connected to the switching element and extending in a column direction and arranged in two pixel electrode columns A thin film transistor array panel including a plurality of data lines, and a common electrode panel facing the thin film transistor array panel, wherein each of the plurality of switching elements is connected to the gate electrode and the data line; The source electrode and the drain connected to the pixel electrode A phosphor electrode is included, and the drain electrode includes an extension part overlapping the sustain electrode.

In the above features, the sustain electrode includes a plurality of sustain electrode portions connected to each other to form one rectangular ring, and the extension portion overlaps the sustain electrode portion while following the plurality of sustain electrode portions.

In addition, each of the plurality of gate lines further includes a first protrusion extending in one direction, the drain electrode further includes a second protrusion extending in a direction opposite to the source electrode, and the first protrusion is formed in the second protrusion. It is preferable to overlap with 2 protrusions.

The longitudinal side of the first protrusion may be parallel to the longitudinal side of the second protrusion.

Further, it is preferable that the sustain electrode is formed on the same layer as the gate line, and the drain electrode is formed on the same layer as the data line.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.                     

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A thin film transistor array panel and a liquid crystal display according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention. 3 is a structural diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 includes a plurality of display signal lines G ₁ -G _2n , D ₁ -D _m, L1 _, L2, connected to the plurality of display signal lines _, and arranged in an approximately matrix form in an equivalent circuit. ).

Display signal line (G ₁ -G _2n , D ₁ -D _m , L1 _and L2 are a plurality of gate lines G ₁ -G _2n that transmit gate signals (also referred to as "scan signals"), data lines D ₁ -D _m that transmit data signals, and dummy lines L1, L2). The gate lines G ₁ -G _2n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m and the dummy lines L1 and L2 extend substantially in the column direction and are substantially parallel to each other. .

As shown in FIG. 3, a liquid crystal display device is disposed above the liquid crystal panel assembly 300 including the gate lines G ₁ -G _2n , the data lines D ₁ -D _m , and the dummy lines L1 and L2. The printed circuit board (PCB) 550 is provided with circuit elements such as a signal controller 600, a driving voltage generator 700, and a gray voltage generator 800 for driving the LEDs. The miseon (L1) is maximum in the vicinity of the left edge, and more miseon (L2) of the liquid crystal panel assembly 300 will extend substantially in the row direction in the vicinity of the right-most edge of the liquid crystal panel assembly 300 and the data lines (D ₁ - Almost parallel to D _m ).

The liquid crystal panel assembly 300 and the PCB 550 are electrically and physically connected to each other through a flexible printed circuit (FPC) substrate 510.

The flexible circuit board 510 is provided with a data driver integrated circuit chip 540 constituting the data driver 500, and a plurality of data transfer lines 521 are formed. The data transfer line 521 is connected to a plurality of data lines D ₁ -D _m formed on the liquid crystal panel assembly 300 through the contact portion C1 to transfer corresponding data voltages.

Signal transmission lines 522a, 522b, 523a, and 523b are formed on the left and rightmost FPC boards 510. The signal transmission lines 522a, 522b, 523a, and 523b are connected to the signal transmission lines 551a and 551b formed on the PCB 550 through the contact portion C3.

The signal transmission line 522a formed on the leftmost FPC substrate 510 is connected to the leftmost data line D ₁ through the contact portion C2, and is also connected to the signal transmission line 551a through the contact portion C3. 523a is connected to the dummy line L2 through the contact portion C1.

In addition, the signal transmission line 523b formed on the rightmost FPC board 510 is connected to the rightmost data line D _m through the contact portion C2, and also through the contact portion C3. It is connected to 551b and 523b, and is connected to the dummy line L1 through the contact part C1.

Each pixel includes a switching element Q connected to the display signal lines G ₁ -G _2n , D ₁ -D _m and the dummy lines L1 and L2, a liquid crystal capacitor C _LC , and a storage capacitor connected thereto. (storage capacitor) (C _ST ). The holding capacitor C _ST can be omitted as necessary.

The switching element Q, such as a thin film transistor, is provided in the lower display panel 100, which is a thin film transistor display panel, and is a three-terminal element whose control terminal and input terminal are respectively a gate line G ₁ -G _{2 n} and a data line DD _m. ) And dummy lines L1 and L2, and output terminals are connected to the liquid crystal capacitor C _LC and the storage capacitor C _ST .

The liquid crystal capacitor C _LC has two terminals, a pixel electrode 190 of the lower panel 100 and a common electrode 270 of the upper panel 200, which is a common electrode display panel, and the liquid crystal layer between the two electrodes 190 and 270. (3) functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST , which serves as an auxiliary part of the liquid crystal capacitor C _LC , is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage V _com is applied to this separate signal line. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

As shown in FIG. 3, the pair of gate lines G ₁ and G ₂ , G ₃ and G _{4,... Are} arranged above and below the pixel electrodes 190 in a row. In addition, the data lines D ₁ -D _m are disposed one by one between the pixel electrodes 190 of two columns. That is, one data line is arranged between the pair of pixel columns. The connection between the gate lines G ₁ -G _2n and the data lines D ₁ -D _m and the pixel electrode 190 will be described in more detail.

The plurality of pairs of gate lines G ₁ -G _2n connected to the top and bottom of the pixel electrode 190 are connected to the corresponding pixel electrode 190 through a switching element Q disposed above or below each pixel electrode 190. Is connected to.

That is, in the odd-numbered pixel row, the switching element Q located on the left side of the data lines D ₁ -D _{m is} connected to the gate lines G ₁ , G ₅ , G ₉ ,... The switching element Q located on the right side of the data line D ₁ -D _{m is} connected to the gate lines G ₂ , G ₆ , G ₁₀ ,... On the other hand, the upper gate line (G ₃ , G ₇ , G ₁₁ , ...) and the lower gate line (G ₄ , G ₈ , G ₁₂ , ...) positioned in the even-numbered pixel row and the switching element (Q) The concatenation is the opposite of odd-numbered pixel rows. That is, the switching element Q located on the right side of the data line D ₁ -D _{m is} connected to the gate lines G ₃ , G ₇ , G ₁₁ ,... Located above, and the data line ( The switching element Q on the left side of the center D ₁ -D _{m is} connected to the gate lines G ₄ , G ₈ , G ₁₂ ,...

The pixel electrode 190 located on the left side of the pixel electrodes 190 in the odd-numbered row with respect to the data lines D ₁ -D _m is connected to the immediately adjacent data lines D ₁ -D _m through the switching element Q. The pixel electrode 190 connected to the right side of the data line D ₁ -D _m is connected to the data line adjacent to each other through the switching element Q. The pixel electrode 190 located on the left side of the even-numbered pixel electrodes 190 around the data lines D ₁ -D _m is connected to the immediately preceding data line through the switching element Q. The data line The pixel electrode 190 positioned on the right side of the center D ₁ -D _m is connected to the immediately adjacent data line through the switching element Q. In addition, the pixel electrodes 190 of the even row of the first column are connected to the dummy line L1 connected to the last data line D _m , and the pixel electrodes 190 of the odd row of the last column are connected to the first data line ( It is connected to the connecting line L2 connected to D ₁ ).

As described above, the switching element Q formed in each pixel can be more easily connected to the connected data lines D ₁ -D _m or the dummy lines L1 and L2, that is, the connection length can be as short as possible. Formed in position. Therefore, in the arrangement shown in FIG. 3, the position of the switching element Q changes every pixel row. That is, to the right of the odd-numbered pixels located in the left side of the pixel pair in the row data lines (D ₁ -D _m) had a switching element (Q) on the right upper end portion is formed on the data lines (D ₁ -D _m) The switching element Q is formed in the lower right portion of the pixel.

On the other hand, the formation positions of the switching elements Q of the pixels located in the even rows are opposite to the formation positions of the adjacent pixel rows. That is, the right side of the even-numbered pixels located in the left side of the pixel pair in the row data lines (D ₁ -D _m) is formed on the switching element (Q) at the bottom left, and the data lines (D ₁ -D _m) The switching element Q is formed in the upper left portion of the pixel.

When the connection between the pixel electrode 190 and the data lines D ₁ -D _m shown in FIG. 3 is arranged, in each pixel row, the switching elements Q of two pixels positioned between two adjacent data lines are the same data line. Is connected to. That is, the switching elements Q of two pixels formed between two data lines in an odd pixel row are connected to the data line positioned on the right side, and the switching elements Q of two pixels formed between two data lines in an even pixel row. ) Is connected to the data line on the left.

The arrangement shown in FIG. 3 is just one example, and the connection between the pixel electrodes 190 and the data lines D ₁ -D _m and the gate lines G ₁ -G _{2n in the} odd and even rows are mutually different. It can be changed and can also have other connections.

On the other hand, to implement color display, each pixel uniquely displays one of the three primary colors (spatial division) or each pixel alternately displays the three primary colors over time (time division) so that the desired color can be selected by the spatial and temporal sum of these three primary colors. To be recognized. 2 shows that each pixel includes a red, green, or blue color filter 230 in a region corresponding to the pixel electrode 190 as an example of spatial division. Unlike FIG. 2, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

3, the color filters 230 are arranged in the order of red, green, and blue in the row direction, and each pixel column forms a stripe arrangement including only the color filter 230 of one color.

Polarizers (not shown) for polarizing light are attached to an outer surface of at least one of the two display panels 100 and 200 of the liquid crystal panel assembly 300.

Next, the structure of the thin film transistor array panel 100 of the liquid crystal panel assembly 300 will be described in detail with reference to FIGS. 4 to 7.

4 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIGS. 5 to 7 respectively illustrate the thin film transistor array panel of FIG. 4 along a line V-V ', VI-VI', and VII-VII ', respectively. It is a cut section.

As described above, the liquid crystal display according to the exemplary embodiment includes a thin film transistor array panel 100 and a common electrode panel 200 facing the thin film transistor array panel 100 and a thin film transistor array panel 100 and the common electrode panel 200. It contains the liquid crystal layer 3 contained.

First, the thin film transistor array panel 100 will be described in detail.

A plurality of gate lines 121a and 121b and a plurality of storage electrode lines 131 are formed on an insulating substrate 110 such as transparent glass.

The gate lines 121a and 121b mainly extend in the horizontal direction, and a part of the gate lines 121a protrude downward or upward to form the gate electrodes 124a and 124b. In addition, one end portion 129 of the gate lines 121a and 121b is widened for connection with another layer or an external device. The two gate lines 121a and 121b are paired adjacent to each other. The top gate line 121b and the bottom gate line 121a may not be paired.

Each storage electrode line 131 is separated from the gate lines 121a and 121b, and is connected to each other to form a pair of storage electrodes 133a to 133d and a pair of storage electrode connection portions 135a and 135b. It includes.

One set of storage electrodes 133a to 133d includes a pair of first storage electrodes 133a and a second storage electrode 133b which mainly extend in a horizontal direction, and a pair of third storage electrodes that mainly extend in a vertical direction ( 133c and a fourth sustain electrode 133d extending therebetween and extending in the vertical direction. The first to third storage electrodes 133a to 133c are disposed one by one on both the left and right sides of the fourth storage electrode 133d to form a rectangle sharing the fourth storage electrode 133d. It has a rotational symmetry of 180 degrees about the center of the electrode 133d.

The storage electrode connector 135 connects adjacent storage electrodes 133c of two sets of adjacent storage electrodes 133a-133d, and the storage electrode 133a is bent near the gate electrode 124.

A predetermined voltage such as a common voltage applied to the common electrode 270 of the common electrode display panel 200 of the liquid crystal display device is applied to the sustain electrode line 131.

The gate lines 121a and 121b and the sustain electrode line 131 are made of aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, and copper-based metals such as copper (Cu) and copper alloys. Metal, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta) and titanium (Ti). However, the gate lines 121a and 121b and the storage electrode line 131 may include two layers having different physical properties, that is, a lower layer (not shown) and an upper layer (not shown) thereon. The upper layer may have a low resistivity metal such as aluminum (Al) or an aluminum alloy such as aluminum (Al) or aluminum alloy to reduce signal delay or voltage drop between the gate lines 121a and 121b and the storage electrode line 131. It may be made of a silver-based metal such as silver (Ag) or a silver alloy, or a copper-based metal such as copper (Cu) or a copper alloy. In contrast, the underlayer is a material having excellent contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as chromium, molybdenum (Mo), molybdenum alloys, tantalum (Ta), or titanium (Ti) Or the like. A good example of a combination of a bottom film and a top film is a chromium / aluminum-neodymium (Nd) alloy.

Side surfaces of the gate lines 121a and 121b and the storage electrode line 131 are inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30-80 °.

A gate insulating layer 140 made of silicon nitride (SiN _x ) is formed on the gate lines 121a and 121b and the storage electrode line 131.

On the gate insulating layer 140, a plurality of island-like semiconductors 152, 154a, and 154b made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si), polycrystalline silicon, or the like are formed. The semiconductors 154a and 154b are positioned on and cover the gate electrodes 124a and 124b, respectively, and the semiconductor 154a extends to cover the neighboring gate line 121a and the sustain electrode connection 135a. In addition, the semiconductor 152 covers the sustain electrode connection part 135b.

A plurality of island-type ohmic contacts 162, 163a, and 163b formed of a material such as n + hydrogenated amorphous silicon doped with a high concentration of silicide or n-type impurities on the semiconductors 152, 154a, and 154b. , 165a, 165b) are formed. The contact members 163a / 163b and the contact members 165a / 165b are paired and positioned on the island semiconductors 154a / 154b.

Side surfaces of the semiconductors 152, 154a, and 154b and the ohmic contacts 162, 163a, 163b, 165a, and 165b are also inclined with respect to the surface of the substrate 110, and the inclination angle is 30-80 °.

A plurality of data lines 171 and a plurality of drain electrodes 175a and 175b are formed on the ohmic contacts 162, 163a, 163b, 165a, and 165b and the gate insulating layer 140, respectively. have.

The data line 171 mainly extends in the vertical direction and crosses the gate lines 121a and 121b and the storage electrode connectors 135a and 135b and transmits a data voltage. The end portion 179 of each data line 171 is extended in width for connection with another layer or an external device. A plurality of branches extending from the data lines 171 toward the drain electrodes 175a and 175b in the right direction or the left direction respectively form the source electrodes 173a and 173b and one side of the drain electrodes 175a and 175b. The end is linear but the other end is extended in width for connection with the other layer and is positioned over the sustain electrode 133a. The source electrode 173b is bent to partially wrap the linear end of the drain electrode 175a, and the source electrode 173a approaches the adjacent adjacent drain electrode 175a across the two adjacent gate lines 121a and 121b. It is bent to partially wrap the linear end of the drain electrode 175a.                     

The gate electrodes 124a / 124b, the source electrodes 173a / 173b, and the drain electrodes 175a / 175b together with the island-like semiconductors 154a / 154b form a thin film transistor (TFT), and the channel of the thin film transistor ( Channels are formed in the island-like semiconductors 154a / 154b between the source electrodes 173a / 173b and the drain electrodes 175a / 175b.

The data line 171 and the drain electrodes 175a and 175b may be made of a molybdenum-based metal, a refractory metal such as chromium, tantalum, or titanium, and include a lower layer having a low resistance and a lower layer having good contact characteristics. It can have a multilayer film structure.

Like the gate line 121, the data line 171 and the drain electrodes 175a and 175b are inclined at an angle of about 30 to 80 degrees, respectively.

The ohmic contacts 162, 163a, 163b, 165a, and 165b exist only between the semiconductors 152, 154a, and 154b thereunder and the data lines 171 and drain electrodes 175a and 175b thereover, and provide contact resistance. It acts to lower.

As described above, the island-type semiconductors 152, 154a, and 154b have a gate line at a portion where the data line 171 or the drain electrodes 175a and 175b meet the gate line 121 and the storage electrode lines 133a-133d and 135. The boundary between 121 and the sustain electrode lines 133a to 133d and 135 is covered to prevent disconnection of the data line 171.

A passivation layer 180 is formed on the data line 171, the drain electrodes 175a and 175b, and the exposed portions of the semiconductors 152, 154a and 154b. The passivation layer 180 may be formed of a-Si: C: O, a-Si: O: organic material having excellent planarization characteristics and photosensitivity, or formed by plasma enhanced chemical vapor deposition (PECVD). It consists of low dielectric constant insulating material of dielectric constant below 4.0, such as F, or silicon nitride which is an inorganic material. Alternatively, the passivation layer 180 may be formed of a double layer of organic material and silicon nitride.

The passivation layer 180 is provided with a plurality of contact holes 185 and 182 exposing the drain electrodes 175a and 175b and the end portion 179 of the data line 171, respectively, and the gate insulating layer 140. In addition, a plurality of contact holes 181 exposing the end portion 129 of the gate line 121 are formed.

A plurality of pixel electrodes 190 made of ITO or IZO and a plurality of contact assistants 81 and 82 are formed on the passivation layer 180.

The pixel electrode 190 is physically and electrically connected to the drain electrodes 175a and 175b through the contact hole 185 to receive a data voltage from the drain electrodes 175a and 175b. The pixel electrode 190 to which the data voltage is applied generates an electric field together with the common electrode 270 of the other display panel 200 to which the common voltage V _com is applied, thereby creating a liquid crystal layer 3 between the two electrodes 190 and 270. Rearrange the liquid crystal molecules.

In addition, the pixel electrode 190 and the common electrode 270 form a liquid crystal capacitor C _LC to maintain the applied voltage even after the thin film transistor is turned off, and in parallel with the liquid crystal capacitor C _LC to enhance the voltage holding capability. The storage capacitor C _ST connected to each other is formed by overlapping the pixel electrode 190 and the neighboring storage electrode line 131.

The pixel electrode 190 covers the extended ends of the drain electrodes 175a and 175b and the storage electrode 133a, and partially overlaps the storage electrodes 133b, 133c and 133d so that the boundary line of the pixel electrode 190 is maintained. It is located on the electrodes 133b, 133c, and 133d. As such, the storage electrode 133b is exposed between the gate lines 121a and 121b and the boundary line between the pixel electrode 190 and the pixel electrode 190 due to the parasitic capacitance between the pixel electrode 190 and the gate line 121a. Reduces the voltage fluctuations.

The contact auxiliary members 81 and 82 are connected to the end portions 129 of the gate lines 121a and 121b and the end portions 179 of the data lines 171 through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 complement and protect the adhesiveness between the end portions 129 and 179 of the gate lines 121a and 121b and the data line 171 and the external device. When a gate driver (not shown) for applying a scan signal to the gate lines 121a and 121b is integrated on the display panel, the contact member 81 connects the end portion 129 of the gate lines 121a and 121b to the gate driver. May serve as a connecting member and may be omitted from time to time.

According to another embodiment of the present invention, a transparent conductive polymer may be used as the material of the pixel electrode 190, and in the case of a reflective liquid crystal display, an opaque reflective metal may be used. In this case, the contact assistants 81 and 82 may be made of a material different from the pixel electrode 190, in particular, ITO or IZO.

An alignment film (not shown) may be coated on the pixel electrode 190 to align the liquid crystal layer 3.                     

The common electrode display panel 200 will now be described in detail.

A light blocking member 220 called a black matrix is formed on an insulating substrate 210 such as transparent glass. The light blocking member 220 serves to prevent light leakage between the pixel electrodes 190 and defines an opening area facing the pixel electrode 190.

A plurality of color filters 230 are formed on the substrate 210 and the light blocking member 220. The color filter 230 is disposed to almost enter the opening area defined by the light blocking member 220. The color filters 230 disposed between two neighboring data lines 171 and arranged in the vertical direction may be connected to each other to form a band. Each color filter 230 may represent one of three primary colors such as red, green, and blue.

An overcoat 250 made of an organic material is formed on the color filter 230 and the light blocking member 220 to protect the color filter 230 and to flatten the surface.

The common electrode 270 made of a transparent conductive material such as ITO or IZO is formed on the overcoat 250.

Referring back to FIG. 1, the gray voltage generator 800 generates two sets of gray voltages related to transmittance of a pixel. One of the two sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The gate driver 400 is connected to the gate lines G ₁ -G _2n of the liquid crystal panel assembly 300 to form a gate signal formed by a combination of a gate on voltage V _on and a gate off voltage V _off from the outside. Is applied to the gate lines G ₁ -G _2n to form a plurality of integrated circuits.

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 to select the gray voltage from the gray voltage generator 800 and apply the gray voltage to the pixel as a data signal.

A plurality of gate drive integrated circuits or data drive integrated circuits may be mounted on the FPC substrate in the form of a chip to attach the FPC substrate to the liquid crystal panel assembly 300, or directly attach these integrated circuits onto the glass substrate without using the FPC substrate. It may be attached (chip on glass, COG mounting method), and a circuit performing the same function as these integrated circuits may be formed directly on the liquid crystal panel assembly 300 together with the thin film transistor of the pixel.

The signal controller 600 controls operations of the gate driver 400 and the data driver 500.

The display operation of such a liquid crystal display device will now be described in detail.

The signal controller 600 is configured to control the input image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical synchronization signal Vsync and a horizontal synchronization signal ( Hsync, main clock MCLK, and data enable signal DE are provided. Based on the input image signals R, G and B of the signal controller 600 and the input control signals, the image signals R, G and B are properly processed according to the operating conditions of the liquid crystal panel assembly 300, and the gate control signal After generating the CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to The processing of the image signals R, G, and B includes rearranging the image data R, G, and B according to the pixel arrangement of the liquid crystal panel assembly 300 illustrated in FIG. 3.

For example, a gate control signal (CONT1) includes a gate-on voltage (V _on) the scan starts indicating the start of output of a signal (STV) and a gate-on voltage (V _on) at least one clock signal for controlling the output time and the output voltage of the Include.

The data control signal CONT2 includes a horizontal synchronization start signal STH indicating the start of transmission of the image data DAT, a load signal TP for applying a corresponding data voltage to the data lines D ₁ -D _m , and a common voltage ( V inverted signal (RVS), data clock signal (HCLK), etc. to invert the polarity of the data voltage for the _com (hereinafter referred to as "polarity of the data voltage by reducing the polarity of the data voltage for the common voltage"), etc. do.

The data driver 500 sequentially receives a set of image data DATs for half of the pixels in a row according to the data control signal CONT2 from the signal controller 600, and the gray voltage from the gray voltage generator 800. The grayscale voltage corresponding to each image data DAT is selected to convert the image data DAT into a corresponding data voltage, and then apply the grayscale voltage to the corresponding data lines D ₁ -D _m .

The gate driver 400 sequentially applies the gate-on voltage V _on to the gate lines G ₁ -G _2n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G. _The switching element Q connected to _2n ) is turned on so that the data voltage applied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

The difference between the data voltage applied to the pixel and the common voltage V _com is shown as the charging voltage of the liquid crystal capacitor C _LC , that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the display panels 100 and 200.

The data driver 500 and the gate driver 400 repeat the same operation based on a 1/2 horizontal period (or "1 / 2H") (one period of the horizontal synchronization signal Hsync). In this way, the gate-on voltage V _on is sequentially applied to all the gate lines G ₁ -G _2n during one frame to apply the data voltage to all the pixels. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame ("frame inversion). ").

In addition to the frame inversion, the data driver 500 inverts the polarities of the data voltages descending on the neighboring data lines D ₁ -D _m in one frame, thereby changing the polarities of the pixel voltages to which the data voltages are applied. However, as shown in FIG. 3, since the connection between the pixels and the data lines D ₁ -D _m varies, the polarity inversion pattern of the data driver 500 and the pixel voltage appearing on the screen of the liquid crystal panel assembly 300 are reversed. The pattern looks different. In the following, the inversion in the data driver 500 is referred to as driver inversion, and the inversion that appears on the screen is called an inversion.

Referring to FIG. 3 again, an inversion form according to an embodiment of the present invention will be described in detail.

In FIG. 3, the driver inversion is a column inversion, and the data voltage flowing in one data line is always the same polarity, the data voltage flowing in two neighboring data lines is the opposite polarity, and the apparent inversion is 1 × 2 dot inversion.

As such, when the apparent inversion causes the dot inversion, the difference in the luminance due to the kickback voltage appears when the pixel voltage is positive and negative, and thus the vertical line defect is reduced.

Next, a liquid crystal display according to another exemplary embodiment of the present invention will be described in detail with reference to FIG. 8.

8 is a diagram illustrating a pixel array of a liquid crystal display according to another exemplary embodiment of the present invention.

The pixel arrangement shown in FIG. 8 is also similar to the pixel arrangement shown in FIG. That is, a pair of gate lines are disposed above and below the pixel electrodes 190 in a row, and the data lines D ₁ to D _m are disposed one by one between the pixel electrodes 190 in two columns.

In addition, the switching elements Q connected to the pair of pixel electrodes 190 positioned between two adjacent data lines D _p and D _{p + 1} in one pixel _row may have different gate lines G _{2q + 1} and G _{2q +. 2} ) (q = 0, 1, 2, ...), for example, the switching element Q disposed under the pixel is connected to the lower gate line G _{2q + 2} , and The switching element Q disposed at is connected to the upper gate line G _{2q + 1} .

In addition, a plurality of terminal lines extending from the data lines D _p and D _{p + 1} and connected to the switching element Q are present between two adjacent gate lines.

However, the position of the switching element Q connected to each pixel electrode 190 in FIG. 8 is different from that in FIG. 3. That is, each switching element Q is arranged far from the data lines D _p and D _{p + 1} . In other words, one of the two longitudinal borders of the substantially rectangular pixel electrode 190 is a data line (D _p, D _{p + 1)} adjacent to the other is farther from the data line (D _p, D _{p + 1)} The switching elements Q are all located near the boundary line far from the data lines D _p and D _{p + 1} .

The arrangement shown in FIG. 8 will be described in detail. A pair of pixels located between two adjacent data lines D _p and D _{p + 1} and adjacent in a row direction (hereinafter referred to as “unit pixel pairs”) The switching elements Q of are connected to the same data lines D _p and D _{p + 1} . In addition, a pair of pixels adjacent in the column direction are connected to different data lines D _p and D _{p + 1} , and the switching elements Q are located on opposite sides. When one pixel row is viewed, a unit pixel pair having the same structure is repeated. As a result, the pixel array of the 2x1 matrix structure is repeatedly arranged in the row direction and the column direction.

Next, the structure of the thin film transistor array panel for the liquid crystal display device having the pixel arrangement of FIG. 8 will be described in detail with reference to FIG. 9. FIG. 9 is a layout view of a thin film transistor array panel for a liquid crystal display device having the pixel array shown in FIG. 8.

Referring to FIG. 9, the structure of the thin film transistor array panel 100 according to another exemplary embodiment of the present invention is similar to that shown in FIGS. 4 to 7.

A plurality of gate lines 121a and 121b including the plurality of gate electrodes 124, the storage electrodes 133a, 133b, 133c, and 133d on the substrate 110, and the plurality of gate electrodes 124a and 135b, respectively. The storage electrode line 131 is formed, and the gate insulating layer 140, the plurality of island-like semiconductors 152, 154a, and 154b, and the plurality of ohmic contacts 162, 163a, 163b, 165a, and 165b are sequentially formed thereon. have. A plurality of data lines 171 and a plurality of drain electrodes 175a and 175b are formed on the ohmic contacts 162, 163a, 163b, 165a, and 165b and the gate insulating layer 140, and a passivation layer 180 is formed thereon. It is. A plurality of contact holes 181 and 182 are formed in the passivation layer 180 and the gate insulating layer 140, and a plurality of pixel electrodes 190 and a plurality of contact auxiliary members 82 and 81 are formed on the passivation layer 180. It is.                     

However, in FIG. 9, in addition to the island semiconductors 152, 154a, and 154b, a plurality of island semiconductors 153 are further formed. The island-like semiconductor 153 covers the gate lines 121a and 121b, and an ohmic contact is present between the island-like semiconductor 153 and the data line 171.

The island type semiconductor 153 also covers the boundary of the gate line 121 at a portion where the data line 171 meets the gate line 121 to prevent disconnection of the data line 171, and the ohmic contact member 166 also has an island type semiconductor. The contact resistance between 153 and the data line 171 is lowered.

In the case of the embodiment illustrated in FIGS. 8 and 9, the vertical stripe phenomenon is reduced compared to the embodiment illustrated in FIGS. 4 to 7.

This will be described in detail as follows.

The distance between two adjacent pixel electrodes 190 differs between when the data line 171 is disposed and when it is not, and because of the width difference between the pixel electrodes 190, the distance between the pixel electrodes 190 is increased. The width of the light blocking member positioned also varies depending on whether the data line 171 is disposed. For example, in the case of a 15-inch WXGA class liquid crystal display device, the width of the light blocking member of the portion where the data line 171 is disposed is about 29 μm, whereas the width of the portion where the data line 171 is not disposed is measured. The width of the light blocking member is about 18 μm, and a width difference of about 11 μm occurs. As a result, vertical line defects may occur due to a difference in the display area of the pixel having the data line 171 and the two pixels having no data line 171.

However, in the liquid crystal display device shown in FIGS. 8 and 9, when the switching element is disposed between the pixel electrodes 190 where the data line 171 is not arranged, the area of the light blocking member is not arranged with the data line 171. Areas due to these switching elements are added in addition to the area between the non-pixel electrode 190.

By doing so, the area of the light blocking member is increased by the portion where the switching element is formed, and accordingly, the increase of the light blocking member increased due to the arrangement of the data lines 171 is compensated, so that the portion where the data line 171 is formed is not and is not. The area of the light shielding member of the portion is almost the same, so that the area difference of the light shielding member is reduced in the vertical streak.

Next, a liquid crystal display according to another exemplary embodiment of the present invention will be described in detail with reference to FIGS. 10 to 12.

FIG. 10 is a layout view of a thin film transistor array panel according to another exemplary embodiment. FIG. 11 is a cross-sectional view of the thin film transistor array panel of FIG. 10 taken along line XI-XI ′. 12 is an equivalent circuit diagram for parasitic capacitance generated between two pixel electrodes.

Referring to FIG. 10, the structure of the thin film transistor array panel 100 according to another exemplary embodiment of the present invention is similar to that shown in FIGS. 8 and 9.

A plurality of gate lines 121a and 121b including the plurality of gate electrodes 124, the storage electrodes 133a, 133b, 133c, and 133d on the substrate 110, and the plurality of gate electrodes 124a and 135b, respectively. The storage electrode line 131 is formed, and the gate insulating layer 140, the plurality of island semiconductors 152, 154a, 154b, 153a, and 153b and the plurality of ohmic contacts 162, 163a, 163b, 165a, and 165b are disposed thereon. Are formed in turn. A plurality of data lines 171 and a plurality of drain electrodes 175a and 175b are formed on the ohmic contacts 162, 163a, 163b, 165a, and 165b and the gate insulating layer 140, and a passivation layer 180 is formed thereon. It is. A plurality of contact holes 181 and 182 are formed in the passivation layer 180 and the gate insulating layer 140, and a plurality of pixel electrodes 190 and a plurality of contact auxiliary members 82 and 81 are formed on the passivation layer 180. It is. In FIG. 9, island-like semiconductors 153 integrally formed at the portions where the data lines 171 branch, are denoted by reference numerals 153a and 153b at portions intersecting with the gate lines 121a and 121b in FIG. 10, respectively. Divided.

However, in FIG. 10, the gate lines 121a and 121b further include protrusions 125a and 125b.

The protrusions 125a and 125b protrude upward or downward from the respective gate lines 121a and 121b.

In addition to the island-like semiconductors 152, 154a, 154b, 153a, and 153b, a plurality of island-like semiconductors 156a and 156b are further formed.

In addition, in the portions of the drain electrodes 175a and 175b whose widths are expanded for connection with other layers, the linear protrusions 176a and 176b in a direction opposite to the linear portions, that is, in a direction opposite to the source electrodes 173a and 173b. ) Is stretched. Part of the protrusions 176a and 176b overlaps the protrusions 125a and 125b of the gate lines 121a and 121b. The vertical widths of the linear portions of the drain electrodes 175a and 175b and the vertical widths of the protrusions 176a and 176b are the same, and the vertical sides of these linear portions and the vertical sides of the protrusions 176a and 176b are parallel to each other.

In addition, the drain electrodes 175a and 175b further include an extension part 172. The extension part 172 includes first to fifth portions 178a, 178b, and 177b-177d and overlaps the sustain electrodes 133a-133d. That is, the first portion 178a, the second portion 178b, and the third portion 177b mainly extend in the horizontal direction, and each of the first storage electrode 133a and the remaining portion of the first storage electrode 133a. The portion overlaps with the second storage electrode 133b. The fourth part 177c and the fifth part 177d mainly extend in the vertical direction, and overlap with the third storage electrode 133c and the fourth storage electrode 133d, respectively. As a result, these extension portions 172 extend out of the drain electrodes 175a and 175b and overlap with the sustain electrodes 133a to 133d to form a rectangle connected to each other similarly to the sustain electrode 13a.

The island semiconductors 156a and 156b cover a part of the protrusions 125a and 125b of the gate lines 121a and 121b, and the protrusions 176a and 176b of the island semiconductors 156a and 156b and the drain electrodes 175a and 175b. There is an ohmic contact member (not shown) in between.

The island semiconductors 156a and 156b also have protrusions 176a and 176b of the drain electrodes 175a and 175b at portions where the protrusions 176a and 176b meet the protrusions 125a and 125b of the gate lines 121a and 121b. Covers the boundaries of the 125a and 125b to prevent disconnection of the protrusions 176a and 176b of the drain electrodes 175a and 175b, and the ohmic contact member also includes the protrusions of the island-like semiconductors 156a and 156b and the drain electrodes 175a and 175b. Lower the contact resistance between (176a, 176b).

As the drain electrodes 175a and 175b further include an extension 172 overlapping the storage electrode line 131, the capacitance of the storage capacitor C _ST increases.

That is, in the thin film transistor array panel illustrated in FIGS. 10 and 11, the extension portion 172 of the drain electrodes 175a and 175b connected to the pixel electrode 190 has the storage electrode line 131 with the gate insulating layer 140 interposed therebetween. In the thin film transistor array panel illustrated in FIG. 9, the pixel electrode 190 overlaps the storage electrode line 131 with the passivation layer 180 interposed therebetween.

Accordingly, in the thin film transistor array panel illustrated in FIGS. 10 and 11, the distance between the extension part 172 connected to the pixel electrode 190 and the storage electrode line 131 is equal to the pixel electrode 190 of the thin film transistor array panel illustrated in FIG. 9. Closer than the distance between the storage electrode line 131, the capacitance of the storage capacitor C _ST formed between the extension portion 172 and the storage electrode line 131 is formed between the pixel electrode 190 and the storage electrode line 131. It is much larger than the capacity of the holding capacitor C _ST .

As shown in FIG. 12, when two pixel electrodes 190 are disposed between adjacent data lines D _l and D _{l + 1} , the data lines D _l and D _{l + 1} and the pixel electrode 190 are disposed. Parasitic capacitances Cdp1, Cdp2, and Cpp are generated between the pixels and the adjacent pixel electrodes 190, respectively. However, these parasitic capacitances Cdp1 and Cdp2 change according to a change in distance between the adjacent data lines D ₁ and D _{1 + 1} and the pixel electrode 190.

During the process of manufacturing the thin film transistor array panel, when the pixel electrode 190 is formed, the entirety of the pixel electrode 190 may move to the left or the right, in this case, between the data line D ₁ and the pixel electrode 190. The distance d1 and the distance d2 between the data line D1 _{+ 1} and the pixel electrode 190 are changed. That is, when the distance d1 is shortened or lengthened, the distance d2 becomes longer or shorter on the contrary, so that the two distances d1 and d2 are different from each other, and the parasitic capacitances Cdp1 and Cdp2 formed therebetween are different. A deviation occurs between the capacities Cdp1 and Cdp2.

The change width ΔV of the pixel voltage according to the parasitic capacitance Cdp between the pixel electrode 190 and the data line is defined as in Equation 1 below.

(Where ΔVg is the voltage variation of the gate line, C _LC is the capacitance of the liquid crystal capacitor, and C _ST is the capacitance of the storage capacitor.)

Accordingly, since the change width ΔV of the pixel voltage varies according to the sizes of the parasitic capacitances Cdp1 and Cdp2, a deviation occurs between the pixel voltages of two adjacent pixels.

However, as the storage capacitor C _ST is increased by using the structures shown in FIGS. 10 and 11, the variation width ΔV of the pixel voltage decreases, thereby reducing the pixel voltage deviation of adjacent pixels. In the case of the thin film transistor array panel to which the structure is applied, the holding capacitance C _ST may be increased by about 30% and the pixel voltage deviation of about 10 to 20% may be reduced as compared with the thin film transistor array panel.

In addition, as described above, the protrusions 176a and 176b having vertical sides parallel to the vertical sides of the linear portions of the drain electrodes 175a and 175b overlap the protrusions 125a and 125b of the gate lines 121a and 121b. . In this case, as the mask for exposing the data line photoresist film is not aligned at the correct position and the data line pattern moves to the left or right, even if the data electrodes 175a and 175b move to the left or right, the drain electrode 175a, 175b and the protrusions 176a and 176 overlap with the gate electrodes 124a and 124b and the protrusions 125a and 125b of the gate lines 121a and 121b, respectively. Therefore, the capacitance of the parasitic capacitor Cgd proportional to the overlapping area of the gate line and the drain electrode is kept constant.

In more detail, the gate electrodes 124a and 124b and the drain electrode (even if the mask for the data line photoresist moves in the left or right direction at the correct position and the data line pattern moves in the left or right direction as a whole). The increase or decrease of the overlapped area of 175a and 175b is equal to the decrease or increase of the overlapping portions of the protrusions 125a and 125b of the gate lines 121a and 121b and the protrusions 176a and 176b of the drain electrodes 175a and 175b. Do. As a result, the overlapping area of the drain electrodes 175a and 175b, the gate electrodes 124a and 124b, and the protrusions 125a and 125b becomes constant regardless of the movement of the entire data line pattern, and thus the parasitic capacitor Cgd generated therebetween. ) Does not change. That is, even if the mask for the data line photoresist film is not aligned at the correct position, the parasitic capacitance does not occur even if the position of the data line pattern changes.

Of course, even when the mask exposing the photosensitive film for the data line moves upward or downward in the correct alignment position, each of the linear portion of the drain electrode 175a and the protrusion 176a is substantially perpendicular to the data line 171. Since the vertical direction moves along the edges of 124a and the protrusion 125a, the capacitance of the parasitic capacitor Cgd does not change.

As described above, when the position of the data line to which the switching elements are connected between adjacent pixel rows is changed, the apparent inversion may be 1 × 2 dot inversion even though the driver inversion is a column inversion method. Therefore, since the polarity of the data voltage is determined and applied from the data driver by the column inversion method, the material selection width of the data line is increased, and the manufacturing process is easy to simplify, and since the apparent inversion is dot inversion, the image quality is improved. Furthermore, since the number of data lines is reduced, the number of expensive data driving circuit chips connected thereto is also reduced, which greatly reduces the manufacturing cost of the display device.

In addition, a switching element is formed in a portion where the data line is not formed, so that the difference in the light blocking member area between the pixel electrodes in which the data line is formed and the pixel electrode in which the data line is not formed is reduced. Accordingly, the phenomenon of the vertical stripes due to the difference in display area is reduced, and the image quality of the display device is improved.

Furthermore, by forming a protrusion of the drain electrode overlapping the gate line in the opposite direction to the source electrode, the overlapping area between the gate line and the drain electrode does not change even if the data line moves to the left or right without being patterned at the correct position during the manufacturing process. Parasitic doses occurring between them remain the same. Therefore, the difference in screen brightness between shots or flickering of screens is prevented, so the deterioration of image quality due to poor stitching or flicker is reduced.

In addition, since the capacitance of the storage capacitor is increased to reduce the pixel voltage variation generated between the pixels due to the parasitic capacitance variation, the deterioration in image quality of the display device is reduced.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (17)

A plurality of pixel electrodes arranged in a matrix form, A plurality of sustain electrodes at least partially overlapping the pixel electrodes; A plurality of switching elements connected to the pixel electrode, A plurality of gate lines connected to the switching element and extending in a row direction and arranged in two per pixel electrode row; A plurality of data lines connected to the switching element and extending in a column direction and arranged one per two pixel electrode columns Including, Each of the plurality of switching elements includes a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode. The drain electrode includes an extension that overlaps the sustain electrode. Thin film transistor array panel. In claim 1, The sustain electrode includes a plurality of sustain electrode portions connected to each other to form one rectangular ring, The extension part overlaps the sustain electrode part while following the plurality of sustain electrode parts. Thin film transistor array panel. In claim 2, Each of the plurality of gate lines further includes a first protrusion extending in one direction, The drain electrode further includes a second protrusion extending in a direction opposite to the source electrode, The first protrusion overlaps the second protrusion. Thin film transistor array panel. In claim 3, The vertical side of the first protrusion is parallel to the vertical side of the second protrusion. The method of claim 1 or 4, A thin film transistor array panel in which switching elements connected to two pixel electrodes arranged in a row direction between two adjacent data lines are connected to the same data line. In claim 5, A thin film transistor array panel in which switching elements connected to vertically adjacent pixel electrodes in one pixel electrode column are connected to different data lines. In claim 6, A switching device connected to at least two pixel electrodes is connected to a gate line disposed above and below. In claim 7, And a terminal line connecting the data line and the switching element to pass between two adjacent gate lines. In claim 8, Each of the pixel electrodes has a first boundary line close to the data line and a second boundary line far from the data line, The switching element is positioned near a second boundary of the pixel electrode, One terminal line is connected to two pixels Thin film transistor array panel. In claim 1, And the sustain electrode is formed on the same layer as the gate line. In claim 1, And the drain electrode is formed on the same layer as the data line. A plurality of pixel electrodes arranged in a matrix form, a plurality of sustain electrodes overlapping at least a portion of the pixel electrodes, a plurality of switching elements connected to the pixel electrodes, connected to the switching elements, extending in a row direction, A thin film transistor array panel including a plurality of gate lines arranged at two per pixel electrode row, and a plurality of data lines connected to the switching element and extending in a column direction and arranged at one line per two pixel electrode columns. , And A common electrode panel facing the thin film transistor array panel Including, Each of the plurality of switching elements includes a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode. The drain electrode includes an extension that overlaps the sustain electrode. Liquid crystal display. In claim 12, The sustain electrode includes a plurality of sustain electrode portions connected to each other to form one rectangular ring, The extension part overlaps the sustain electrode part while following the plurality of sustain electrode parts. Liquid crystal display. In claim 13, Each of the plurality of gate lines further includes a first protrusion extending in one direction, The drain electrode further includes a second protrusion extending in a direction opposite to the source electrode, The first protrusion overlaps the second protrusion. Liquid crystal display. The method of claim 14, The vertical side of the first protrusion is parallel to the vertical side of the second protrusion. In claim 12, And the sustain electrode is formed on the same layer as the gate line. In claim 12, And the drain electrode is formed on the same layer as the data line.

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