KR20060005258A - Semiconductor memory device and signal line arrangement method thereof - Google Patents

Abstract

The present invention discloses a semiconductor memory device and a signal line arrangement method thereof. The apparatus includes at least one driver for transmitting a signal, a second signal line disposed in the same direction as the first signal line, and a signal of the first signal line to the second signal line. And the first signal line and the second signal line on different layers. Therefore, even if the semiconductor memory device is highly integrated and chip size is increased, the semiconductor memory device can be operated at high speed.

Description

Semiconductor memory device and signal line arrangement method

1 is a diagram showing a configuration of a semiconductor memory device according to the prior art.

FIG. 2 is a diagram illustrating a signal line arrangement method of the semiconductor memory device of FIG. 1. FIG.

FIG. 3 is a diagram for describing a delay component of the predecoded row address signal line of FIG. 2. FIG.

4 illustrates a configuration of a semiconductor memory device according to the technology of the present invention.

FIG. 5 is a diagram illustrating a signal line arrangement method of the semiconductor memory device of FIG. 4. FIG.

FIG. 6 illustrates a delay component of the pre-decoded row address signal line of FIG. 5. FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device for supporting a high operating speed and a signal line arrangement method thereof.

As the semiconductor memory device becomes larger, the capacity and size of the memory cell array increase, and accordingly, the chip size of the semiconductor memory device also increases.

1 illustrates a configuration of a semiconductor memory device according to the related art. The semiconductor memory device of FIG. 1 includes a memory cell array 10, a row address predecoder 20, a row address decoder 30, and a column address predecoder. 40, a column address buffer 41 and a column address decoder 50 are provided.

Each block of the semiconductor memory device operates as follows.

The memory cell array 10 writes / reads data to / from the selected memory cell MC in response to the word line selection signal and the column selection signal.

The row address buffer 21 receives the row address RA and converts the row address RA into a row address RA / RAB having a form that can be recognized by the semiconductor memory device.

The row address predecoder 20 receives and predecodes the row addresses RA / RAB to generate the predecoded row addresses DRA.

The row address decoder 30 decodes the predecoded row address DRA to generate a word line enable signal for selecting a specific word line enable signal line NWE, and outputs it to the memory cell array 10. do.

The column address buffer 41 receives the column address CA and converts the column address CA into a column address CA / CAB having a form that can be recognized by the semiconductor memory device.

The column address predecoder 40 receives and predecodes the column address CA / CAB to generate a predecoded row address DCA.

The column address decoders 50 decode the predecoded column address DCA to generate a column select signal for selecting a specific column select signal line CSL, and output the column select signal to the memory cell array 10.

FIG. 2 illustrates a method of arranging signal lines in the semiconductor memory device of FIG. 1, in which signal lines disposed on one layer are indicated by dotted lines, and signal lines disposed on two layers are indicated by solid lines.

First, prior to describing the signal line arrangement method of FIG. 1, the arrangement of each block of FIG. 1 will be described.

When the memory cell array 10 is disposed, the row address decoder 30 is disposed in the array area under the memory cell array 10 to be parallel to the horizontal direction of the memory cell array 10.

The row address predecoder 20 and the row address buffer 21 are arranged in a line in a peripheral area below the row address decoder 30 so as to be parallel to the horizontal direction of the row address decoder 30.

The column address decoders 50 are arranged on the right side of the column address decoder 50 such that the column address decoders 50 are parallel to the vertical direction of the memory cell array 10 in the array area on the right side of the memory cell array 10. The peripheral areas are arranged to be parallel to the vertical direction of the column address decoder 50.

The column address buffer 41 is disposed below the row address buffer 21.

Signal lines for connecting the blocks arranged in this way are arranged as follows.

The word line enable signal line NWE and the local input / output line LIO are connected to memory cells of the same vertical column of the memory cell array 10 and are disposed in the vertical direction on the memory cell array 10.

The column select signal line CSL and the global input / output line GIO are connected to memory cells of the same horizontal column of the memory cell array 10, and are orthogonal to the word line enable signal line NWE on the memory cell array 10. It is arranged in the direction.

The row address signal line RA is connected to the row address buffer 21 and the row address predecoder 20 and is disposed on the row address predecoder 20 in a direction orthogonal to the word line enable signal line NWE. do.

The pre-decoded row address signal line DRA is connected to the row address predecoder 20 and the row address decoder 30 and is orthogonal to the word line enable signal line NWE on the row address decoder 30. Is placed.

The column address signal line CA connects the column address buffer 41 and the column address predecoder 40 so that some regions have a word line enable signal line NWE on the column address predecoder 40. And the remaining area is disposed in the direction orthogonal to the word line enable signal line NWE on the peripheral area.

The predecoded column address signal line DCA is connected to the column address driver 43 and the column address decoder 50 and has the same direction as the word line enable signal line NWE on the column address decoder 50. It is arranged to be.

Accordingly, some areas of the local input / output line (LIO), the predecoded column address signal line (DCA), and the column address signal line (CA) are arranged in the same direction as the word line enable signal line (NWE). Is placed on.

In addition, some regions of the memory cell column select signal line CSL, the global input / output line LIO, the predecoded row address signal line DRA, the row address signal line RA, and the column address signal line CA are words. It is arranged in a direction orthogonal to the line enable signal line NWE, which is arranged on the second floor.

As the capacity of the semiconductor memory device having the above configuration and arrangement increases, the number of memory cells MC included in the memory cell array 10 increases, and thus the horizontal or vertical length of the memory cell array 10 also increases. Is increased.

Therefore, the length of signal lines (RA, DRA, CA, DCA, etc.) inside the semiconductor memory device may be lengthened according to the increased width or length of the memory cell array.

In order to drive the memory cell array 10 including more memory cells MC, peripheral circuits such as the row address decoder 20 and the column address decoder 50 must also have a larger number of circuit elements. .

The signal line at this time is a transmission medium having a delay component and has a delay component proportional to the length. As the length of the signal line increases, the delay component also increases in proportion to the increased length. In addition, the delay time of the signal transmitted through the signal line also increases according to the increased delay component.

The signal lines include a signal line passing through a peripheral area having a very small number of circuits, such as a row address signal line RA and a column address signal line CA, and a predecoded row address signal line DRA and a predecoded signal line. The number of circuits connected to the signal line, such as the column address signal line DCA, is divided into signal lines passing through the array area.

Since the signal line passing through the peripheral region has only the delay component of the signal line itself, a repeater can be inserted into the signal line even if the signal line is increased in length, thereby sufficiently preventing the delay of the signal.

However, in the case of signal lines passing through the array region, not only the delay components of the signal lines themselves but also additional delay components by circuits connected to the signal lines are provided. As the length of the signal line increases, not only the delay component according to the increased length but also the additional delay component by the circuits connected to the signal line also increase, so that the delay component increases rapidly.

This is especially true in predecoded row address signal lines that are not logically or electrically short of signal lines in predecoded column address signal lines (DCAs), which are logically or electrically short circuited by a plurality of column address drivers. More prominently in (DRA).

There is a problem in such a signal line that even if a repeater is inserted, the delay of the signal cannot be sufficiently prevented.

FIG. 3 is a diagram for describing a delay component of the predecoded row address signal line of FIG. 2.

In FIG. 3, row addresses RA / RAB2 to RA / RAB8 are pre-decoded to receive row addresses DRA234_i (i = 0-7), DRA56_j (j = 0-3), and DRA78_k (k = 0-3). A semiconductor memory device including a row address predecoder 20 for generating a signal having a combination of? And a row address decoder 30 having 128 main decoders 31 to 3128 will be described as an example.

The predecoded row address output from the row address predecoder 20 is transmitted to the 128 main decoders 31 to 3128 through the predecoded row address signal lines DRA234_i, DRA56_j, and DRA78_k disposed on the second layer. .

That is, 128 main decoders 31 to 3128 are directly connected to the predecoded row address signal lines DRA234_i, DRA56_j, and DRA78_k disposed on the second layer.

However, the main decoders 31 to 3128 consume current flowing through the predecoded row address signal lines DRA234_i, DRA56_j, and DRA78_k due to an operation characteristic.

Therefore, the pre-decoded row address signal line further includes not only a delay component of the signal line itself but also a delay component corresponding to the amount of current consumption of the predetermined number of main decoders 31 to 31 (N) connected thereto.

In the case of a signal line passing through the array region, such as a pre-decoded row address signal line, as the length increases, not only the delay component of the signal line itself but also additional delay components by a circuit connected to the signal line are increased. The delay time of the signal transmitted through the signal line increases rapidly.

In such a case, even if a repeater is inserted into the signal line, there is a problem that the delay caused by the delay component cannot be sufficiently prevented.

Therefore, the conventional semiconductor memory device has a problem that it becomes difficult to support high-speed operation when the chip size is increased due to the increased capacity.

An object of the present invention is to provide a semiconductor memory device having a signal line arrangement structure that can support a high operating speed even if the chip size of the semiconductor memory device increases, and a signal line arrangement method of the device.

A semiconductor memory device of a first aspect of the present invention for achieving the above object comprises a first signal line for transmitting a signal, a second signal line arranged in the same direction as the first signal line, and the first signal line At least one driver for driving a signal of the signal to the second signal line, characterized in that the first signal line and the second signal line is disposed on different layers.

In accordance with another aspect of the present invention, a semiconductor memory device of the present invention may predecode a word line enable signal line, a column select signal line arranged in a direction orthogonal to the word line enable signal line, and a row address. A row address predecoder generating a predecoded signal, a first signal line disposed in the same direction as the column selection signal line and transmitting the predecoded signal, and at least one driver driving a signal of the first signal line A second signal line disposed in the same direction as the column selection signal line and transmitting an output signal of the driver, and decoding the signal of the second signal line to transmit the decoded signal to the word line enable signal line; And a row address decoder, said word line enable signal. And disposed on the column select signal lines are different from each other layer, it characterized in that the arrangement of the first and second signal lines and a layer of the word line enable signal lines are disposed by dividing the other two layers.

A signal line arrangement method of a semiconductor memory device of a first aspect of the present invention for achieving the above object is to arrange a first signal line for transmitting a signal, the second signal line having the same direction as the first signal line And at least one driver for driving a signal of the first signal line to the second signal line with the first signal line and the second signal line, and connecting the first signal line and the second signal line. It is characterized in that arranged in different layers.

A signal line arrangement method of a semiconductor memory device of a second aspect of the present invention for achieving the above object is a first signal line and a second signal line for transmitting the pre-decoded signal in the same direction as the column select signal line; And at least one driver for driving a signal of the first signal line to the second signal line with the first signal line and the second signal line, and the word line enable signal line and the column select signal line. Are arranged on different layers, and the first and second signal lines are divided into two layers different from the layer on which the word line enable signal line is disposed.

Hereinafter, a semiconductor memory device and a signal line arrangement method of the present invention will be described with reference to the accompanying drawings.

4 is a diagram illustrating a memory cell array configuration of a semiconductor memory device according to an exemplary embodiment of the present invention, in which blocks and signal lines identical to those of FIG. 1 are indicated by the same reference numerals as in FIG.

Referring to FIG. 4, the semiconductor memory device of FIG. 4 may include the memory cell array 10, the row address predecoder 20, the row address buffer 21, the row address decoder 30, and the like in FIG. 1. It includes a column address predecoder 40, a column address buffer 41, and a column address decoder 50, and further includes at least one or more drivers 61 to 64.

The drivers 61 to 64 increase the driving capability of the signal without changing the logic level of the signal. The drivers 61 to 64 drive the predecoded row address of the row address predecoder 20 to the row address decoder 30.

In this case, two inverters connected in series may be used as the drivers 61 to 64.

The semiconductor memory device of the present invention adopts a three-layer wiring structure.

In this case, the signal line applied to the third layer has a smaller capacitance value.

This is advantageous when the semiconductor memory device uses a plurality of signal lines, in which a signal line having a relatively low capacitance value is disposed in the upper layer and a signal line having a relatively large capacitance value in the lower layer has an advantageous effect in terms of transmission speed. Because there is.

This is because the capacitance value of the upper layer signal line has a relatively small capacitance value of the lower layer signal line, so that the RC delay can more effectively realize an operation speed improvement due to a decrease in resistance.

FIG. 5 is a view illustrating a signal line arrangement method of the semiconductor memory device of FIG. 4, wherein a signal line disposed on one layer is a dotted line, and a signal line disposed on two layers is a thin solid line; Are respectively shown by the bold solid line.

Before describing the signal line arrangement method of FIG. 4, the arrangement of each block of FIG. 4 will be described.

The block of FIG. 4 is arranged in the same manner as in FIG. 2 except that at least one of the drivers 61 to 64 is disposed between the row address decoder 30 and the row address predecoder 20 of the row address predecoder 20. Are arranged in line.

That is, the one or more drivers 61 ˜ 64 are parallel to the row address decoder 30 in the horizontal direction at the bottom of the row address decoder 30, and are arranged in a line with an equal interval with respect to the row address decoder 30. .

Of course, the one or more drivers 61 to 64 may be arranged at random intervals with respect to the row address decoder 30 according to the designer's design rule.

Signal lines for connecting the blocks arranged in this way are arranged as follows.

Some areas of the word line enable signal line NWE, the local input / output line LIO, the decoded column address signal line DCA, and the column address signal line CA are arranged on the first layer in the same manner as in FIG. do.

A portion of the column select signal line CSL, the global input / output line LIO, the row address signal line RA, and the column address signal lines CA1 to CA2M having a direction orthogonal to the word line enable signal line NWE. Regions are arranged in two layers in the same manner as in FIG.

The predecoded row address signal line DRA connects at least one driver 61 to 64 to the row address decoder 20 and is orthogonal to the word line enable signal line NWE on the row address decoder 30. It is arranged on the second floor as much as possible.

The pre-decoded row address signal line DRA connects the row address predecoder 20 and at least one driver 61 to 64 and the word line enable signal line NWE on the row address decoder 30. It is placed on the third floor to be orthogonal.

In this case, at least one driver is disposed so that the predecoded row address signal line DRA disposed on two layers overlaps the predecoded row address signal line DRA disposed on three layers.

This is to prevent an increase in chip size due to the pre-decoded row address signal lines DRA disposed in the three layers.

FIG. 6 illustrates a delay component of a pre-decoded row address signal line according to the present invention.

In FIG. 6, the row addresses RA / RAB2 to RA / RAB8 are pre-decoded to receive the row addresses DRA234_i (i = 0-7), DRA56_j (j = 0-3), and DRA78_k (k = 0-3). A semiconductor memory device including a row address predecoder 20 for generating a signal having a combination of? And a row address decoder 30 having 128 main decoders 31 to 3128 will be described as an example.

First, the main decoders 31 to 3128 of the row address decoder 30 and the predecoded row address signal lines DRA234_i, DRA56_j, and DRA78_k disposed on the second layer are formed by four drivers 61 to 64 arranged at equal intervals. It is classified into four groups G1-G4.

The pre-decoded row address signal lines DRA234_i, DRA56_j, and DRA78_k are logically or electrically shorted by groups G1 to G4.

The predecoded row addresses output from the row address predecoder 20 are predecoded row address signal lines DRA234_i (i = 0-7), DRA56_j (j = 0-3), and DRA78_k ( k = 0 to 3)) to the four drivers 61 to 64, and each of the drivers 61 to 64 receives the received predecoded row address of the corresponding group of predecoded row address signal lines DRA234_i ( i = 0-7), DRA56_j (j = 0-3), and DRA78_k (k = 0-3).

The pre-decoded row addresses driven from each of the drivers 61 to 64 are pre-decoded row address signal lines DRA234_i (i = 0-7), DRA56_j (j = 0-3), and DRA78_k disposed on two layers. (k = 0 to 3)) to main decoders 31 to 3128 belonging to the group.

That is, the predecoded row addresses output from the row address predecoder 20 are predecoded row address signal lines DRA234_i (i = 0-7), DRA56_j (j = 0-3), and disposed on three layers. DRA78_k (k = 0-3), and predecoded row address signal lines DRA234_i (i = 0-7), DRA56_j (j = 0-3), and DRA78_k (k) disposed on the second layer belonging to the group. 0 = 3)) and transmitted to the corresponding main decoders.

At this time, the pre-decoded row address signal lines of the two layers are logically or electrically shorted by the drivers to have a reduced signal line length, thereby reducing the number of circuits connected to the signal lines.

In addition, not only a small number of drivers are connected to the pre-decoded row address signal lines of the three layers but also have a capacitance value smaller than that of the signal lines arranged in two layers as the signal lines.

That is, the delay components of the predecoded row address signal lines arranged in the second and third layers and the additional delay components by the circuit are drastically reduced, and thus the delay time of the signal is also reduced.

Although the above described the predecoded row address signal line of the semiconductor memory device as a preferred embodiment of the present invention, it is not necessarily applicable only to the predecoded row address signal line of the semiconductor memory device of the above-described embodiment, and various semiconductor memories It can be applied to all internal signal lines of the device.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

 Therefore, the semiconductor memory device and the signal line arrangement method of the present invention distribute the signal lines for transmitting the same signal in two layers and connect the drivers to reduce delay components of the signal lines. Accordingly, even if the semiconductor memory device is highly integrated and chip size is increased, the semiconductor memory device can be operated at high speed.

Claims (18)

A first signal line for transmitting a signal; A second signal line disposed in the same direction as the first signal line; And At least one driver for driving a signal of the first signal line to the second signal line, And the first signal line and the second signal line are disposed on different layers. The method of claim 1, wherein the first signal line is And the second signal line overlapping the second signal line. The method of claim 1, wherein the first signal line is The semiconductor memory device, characterized in that disposed on the upper layer of the different layer. The method of claim 1, wherein the at least one driver A semiconductor memory device comprising two inverters connected in series. Word line enable signal lines; A column select signal line arranged in a direction orthogonal to the word line enable signal line; A row address predecoder for predecoding the row address to generate a predecoded signal; A first signal line arranged in the same direction as the column select signal line and transmitting the pre-decoded signal; At least one driver for driving a signal of the first signal line; A second signal line arranged in the same direction as the column select signal line and transmitting an output signal of the driver; And A row address decoder for decoding the signal of the second signal line and transmitting the decoded signal to the word line enable signal line; The word line enable signal line and the column select signal line may be disposed on different layers, and the first and second signal lines may be divided into two layers different from the layer on which the word line enable signal line is disposed. A semiconductor memory device, characterized in that. The method of claim 5, wherein the first signal line And the second signal line overlapping the second signal line. The method of claim 5, wherein the second signal line is And at the same layer as the column select signal line. The method of claim 5, wherein the at least one driver A semiconductor memory device comprising two inverters connected in series. Arranging a first signal line for transmitting a signal; Disposing a second signal line having the same direction as the first signal line; At least one driver for driving a signal of the first signal line to the second signal line in connection with the first signal line and the second signal line, And arranging the first signal line and the second signal line in different layers. The method of claim 9, wherein the first signal line is And disposing the second signal line so as to overlap the second signal line. The method of claim 9, wherein the first signal line is The signal line arrangement method of the semiconductor memory device, characterized in that disposed on the upper layer of the different layer. The method of claim 9, wherein the driver And arranging the signal lines at equal intervals with respect to the first and second signal lines. The method of claim 9, wherein the driver And arranging the signal lines at random intervals with respect to the first and second signal lines. A row address decoder configured to drive a word line enable signal line by decoding a word line enable signal line, a column select signal line arranged in a direction orthogonal to the word line enable signal line, and decoding the predecoded signal; A signal line arrangement method of a semiconductor memory device, comprising: a row address predecoder generating the predecoded signal; A first signal line and a second signal line for transmitting the pre-decoded signal in the same direction as the column select signal line; At least one driver for driving a signal of the first signal line to the second signal line in connection with the first signal line and the second signal line, The word line enable signal line and the column select signal line are disposed on different layers, and the first and second signal lines are divided into two layers different from the layer on which the word line enable signal line is disposed. A signal line arrangement method of a semiconductor memory device, characterized in that. The method of claim 14, wherein the first signal line is And arranging the second signal line so as to overlap the second signal line. The method of claim 14, wherein the second signal line is And arranging the same layer as the column select signal line. 15. The driver of claim 14 wherein the driver is And arranging the signal lines at equal intervals with respect to the first and second signal lines. 15. The driver of claim 14 wherein the driver is And arranging the signal lines at random intervals with respect to the first and second signal lines.

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