KR20060004171A - Driving method of plasma display panel - Google Patents

Abstract

The present invention relates to a plasma display panel driving method capable of securing more improved contrast characteristics and sufficient driving margin.

In the plasma display panel driving method of the present invention, a plurality of subfields including a selective write subfield and a selective erase subfield having different emission counts are driven by being divided into a reset period, an address period, and a sustain period. In the reset period of the selective write subfield except for the first subfield and the last subfield, the selective reset pulse of the square waveform and the selective reset pulse of the ramp-down to the scan electrodes of the cells discharged by the sustain pulse in the previous selective write subfield. Supplying sequentially a reset discharge, supplying a scan pulse to the scan electrode after the reset discharge, supplying a data pulse to an address electrode in synchronization with the scan pulse, and performing an address discharge, and the address discharge After that, the scan electrode and the sustain electrode are alternately And sustain discharge by supplying a sustain pulse.

Description

Driving Method of Plasma Display Panel {Driving Method of Plasma Display Panel}

1 is a perspective view showing the structure of a conventional three-electrode AC surface discharge type PDP.

2 is a diagram showing a method of expressing image gradation of a conventional PDP.

3 is a view showing a method of driving a plasma display panel according to the prior art.

4 is a view illustrating a driving waveform according to the PDP driving method shown in FIG.

5 is a view showing a driving waveform in the PDP driving method according to the first embodiment of the present invention.

6 is a view showing a driving waveform in the PDP driving method according to the second embodiment of the present invention.

***** Explanation of symbols for the main parts of the drawing *****

10: upper substrate 11: scanning / sustaining electrode

12: common sustain electrode 13a: upper dielectric layer

13b: lower dielectric layer 14: protective film

20: lower substrate 21: partition wall

22: address electrode 23: phosphor layer

The present invention relates to a plasma display panel driving method, and more particularly to a plasma display panel driving method that can improve the contrast characteristics and driving margin of the plasma display panel.

In general, a plasma display panel (hereinafter referred to as "PDP") displays an image including a character or a graphic by emitting phosphors by 147 nm ultraviolet rays generated when a He + Xe or Ne + Xe inert mixed gas is discharged. Done.

1 is a perspective view showing the structure of a conventional three-electrode AC surface discharge type PDP. Referring to FIG. 1, the three-electrode AC surface discharge type PDP includes a scan / sustain electrode 11 and a common sustain electrode 12 formed on the upper substrate 10, and an address electrode formed on the lower substrate 20. 22). Each of the scan / sustain electrode 11 and the common sustain electrode 12 is formed of transparent electrodes 11a and 12a, for example, indium tin oxide (ITO). Each of the scan / sustain electrode 11 and the common sustain electrode 12 is formed with metal bus electrodes 11b and 12b for reducing resistance. An upper dielectric layer 13a and a passivation layer 14 are stacked on the upper substrate 10 having the scan / sustain electrode 11 and the common sustain electrode 12 formed thereon. Wall charges generated during plasma discharge are accumulated in the upper dielectric layer 13a. The protective layer 14 prevents damage to the upper dielectric layer 13a due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 14, magnesium oxide (MgO) is usually used.

Meanwhile, the lower dielectric layer 13b and the partition wall 21 are formed on the lower substrate 20 on which the address electrode 22 is formed, and the phosphor layer 23 is formed on the surfaces of the lower dielectric layer 13b and the partition wall 21. Is applied. The address electrode 22 is formed in the direction crossing the scan / sustain electrode 11a and the common sustain electrode 12a. The partition wall 21 is formed in parallel with the address electrode 22 to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 23 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. An inert mixed gas such as He + Xe or Ne + Xe for discharging is injected into the discharge space of the discharge cells provided between the upper and lower substrates 10 and 20 and the partition wall 21. A method of expressing image gradation of a conventional PDP having such a structure will be described with reference to FIG. 2.

2 shows a method of expressing image gradation of a conventional PDP. As shown, the image gradation of the PDP is driven by dividing one frame into several subfields having different number of emission times. Each subfield is divided into a reset period for uniformly generating a discharge, an address period for selecting a discharge cell, and a sustain period for implementing gray levels according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields. In addition, each of the eight subfields is subdivided into an address period and a sustain period. Here, the reset period and the address period of each subfield are the same for each subfield, while the sustain period increases at a rate of 2n (n = 0,1,2,3,4,5,6,7) in each subfield. do.

Such a driving method of the PDP is roughly divided into a selective writing method and a selective erasing method according to whether or not the discharge cells are lighted up by the address discharge in the address period. First, the selective write driving method turns off the full screen in the reset period, and then turns on the discharge cells selected in the address period. Subsequently, in the sustain period, an image is displayed by sustaining discharge cells selected by the address discharge.

The selective erasing driving method turns on the full screen by writing discharge in the reset period, and then turns off the selected discharge cells in the address period. Subsequently, in the sustain period, an image is displayed by sustaining discharge cells not selected by the address discharge.

Since the selective erasing method is a discharge for removing wall charges in the cell, the scanning pulse width is narrower than that of the selective writing method, that is, the addressing time can be reduced.

On the other hand, the drive waveform of the selective writing method reduces the contrast as the number of lamp pulses increases, so that the more the use of the driving waveform, the lower the image quality.

Therefore, in the driving method of the PDP, as shown in FIG. 3, a selective write and erase method is configured by configuring one frame into subfields SF1 to SF6 of selective write method and subfields SF7 to SF12 of selective erase method. Drive in parallel.

3 is a view showing a method of driving a plasma display panel according to the prior art. Referring to FIG. 3, in the method of driving a three-electrode alternating surface discharge PDP, one frame includes subfields SF1 through SF6 of selective writing and subfields SF7 through SF12 of selective erasing. The first to sixth subfields SF1 to SF6 include a reset period for turning off the full screen, an optional write address period for turning on the selected discharge cells, a sustain period for sustain discharge for the discharge cells selected by the address discharge, and erasing the sustain discharge. It is divided into an erasing period. In the first to sixth subfields SF1 to SF6, the selective write address period and the erase period are the same for each subfield, while the sustain period is 2 n (n = 0,1,2,3, 4,5). The seventh to twelfth subfields SF7 to SF12 have a selective erase address period for turning off selected discharge cells without a full surface writing period in which the full screen is lit, and a sustain period for sustaining discharge cells other than the discharge cells selected by address discharge. Divided into. In the seventh to twelfth subfields SF7 to SF12, not only the selective erasure address period but also the sustain period are set equally. The sustain period of the seventh to twelfth subfields SF7 to SF12 is set to a luminance relative ratio of 25 to have the same luminance relative ratio as that of the sixth subfield SF6.

Each of the seventh to twelfth subfields SF7 to SF12 driven by the selective erasing method must have the previous subfield turned on to turn off unnecessary discharge cells whenever the subfields are consecutive. For example, in order for the seventh subfield SF7 to be turned on, the sixth subfield SF6 driven by the selective write method, which is the previous subfield, must be turned on. After the sixth subfield SF6 is turned on, the unnecessary discharge cells are turned off in the seventh to twelfth subfields SF7 to SF12. For this purpose, in order for the selective erase subfield ESF to be used, cells turned on in the sixth subfield SF6 which is the last selective write subfield WSF must be turned on by sustain discharge. Therefore, the seventh subfield SF7 does not need a separate writing discharge for the selective erase address. In addition, the eighth to twelfth subfields SF8 to SF12 also selectively turn off the cells turned on in the previous subfield without front lighting.

4 is a diagram illustrating a driving waveform according to the PDP driving method illustrated in FIG. 3. Referring to FIG. 4, in the reset period of the selective write subfield SW, the reset pulse RP of the ramp-down waveform is sequentially followed by the reset pulse RP of the ramp-up waveform in the scan electrode lines Y. Supplied. The reset pulse (-RP) of this ramp down falls to the scan reference voltage (Vw) of negative polarity (-). In addition, a positive scan DC voltage DCSC is supplied to the sustain electrode lines Z.

In the address period of the selective write subfield SW, a negative polarity is applied to each of the scan electrode lines Y and the address electrode lines X while a positive scan DC voltage is supplied to the sustain electrode lines Z. A negative selective write scan pulse (-SWSP) and a positive polarity (+) selective write data pulse (SWDP) are supplied to be synchronized with each other. Sustain pulses SUSPy and SUSPz are alternately supplied to the scan electrode lines Y and the sustain electrode lines Z so that sustain discharge occurs for the cells turned on by the address discharge of the selective write subfield SW. All. At the end of each selective write subfield SW, an erase pulse (not shown) is supplied to the sustain electrode lines Z to cause the sustain discharge to be erased.

The reset period of the selective erase subfield SE is omitted. In the address period of the selective erasing subfield SE, the negative selective (-) of the selective erasing scan pulse (-SESP) and the positive polarity (T) for turning off a cell in each of the scan electrode lines Y and the address electrode lines X are applied. The selective erase data pulses SEDP of +) are supplied to be synchronized with each other. The selective erase scan pulse (-SESP) drops to the selective erase scan voltage (-Ve) higher than the scan reference voltage (-Vw). Sustain pulses SUSPy and SUSPz are alternately supplied to the scan electrode lines Y and the sustain electrode lines Z so that sustain discharge occurs for cells that are not turned off by the address discharge of the selective erase subfield SE. do. In the case where the next subfield is the selective erasure field SE, a sustain pulse SUSPy having a relatively large pulse width is supplied to the scan electrode lines Y at the end of the current selective erasure subfield SE. The erase pulse EP and the ramp signal RAMP are supplied to the scan electrode lines Y and the sustain electrode lines Z in the last selective erase subfield in which the next subfield is the selective write subfield SW. Eliminates sustain discharge in lit cells.

In the driving method as described above, the first half is driven by the selective write method and the second half is driven by the selective erase method.

On the other hand, in the PDP driving method in which both the selective writing method and the selective erasing method are performed in this way, in the subfield of the selective erasing method, the address discharge time for selectively turning off the discharge cells is short, thereby sufficiently securing the driving margin. There is a problem in that the contrast characteristic is lowered because the discharge cells of the full screen are turned on during the reset period.

Accordingly, the present invention provides a plasma display panel driving method capable of securing sufficient driving margin and simultaneously improving contrast characteristics in a PDP driven by a selective writing method and a selective erasing method simultaneously. The purpose is.

In accordance with a first embodiment of the present invention for achieving the above object, a plurality of subfields including a selective write subfield and a selective erase subfield having different light emission times are divided into a reset period, an address period, and a sustain period to implement an image. The plasma display panel driving method has a rectangular waveform on a scan electrode of a cell discharged by a sustain pulse in the previous selective write subfield during the reset period of the selective write subfield except for the first subfield and the last subfield of the selective write subfield. Performing a reset discharge by sequentially supplying a reset pulse and a ramp-down reset pulse, after the reset discharge, supplying a scan pulse to the scan electrode, and supplying a data pulse to the address electrode in synchronization with the scan pulse. Performing an address discharge, and after the address discharge, the scan electrode To alternately supply the sustain pulse to the sustain electrode comprises a sustain discharge.

At this time, the voltage of the selective reset pulse supplied to the scan electrode is the same as the voltage of the sustain pulse supplied from the previous subfield.

The sustain period of the selective reset pulse supplied to the scan electrode is smaller than the sustain period of the sustain pulse supplied in the previous subfield.

The sustain period of the selective reset pulse supplied to the scan electrode may be 0.1 ms to 1 ms.

The sustain period of the selective reset pulse supplied to the scan electrode is different within the range of 0.1 k? To 1 k? Depending on the amount of sustain discharge in each subfield.

In the plasma display panel driving method, when a reset pulse of a rampdown waveform is supplied to all subfields of the selective writing, the voltage applied to the sustain electrode is a positive voltage lower than that of the sustain pulse. It features.

The voltage of the scan pulse supplied to the scan electrode is a negative voltage of -100V or less with respect to the base voltage of the scan electrode.

The reset pulse of the ramp-down waveform supplied to the scan electrode when set down is lowered to the voltage of the scan pulse supplied to the scan electrode.

In the plasma display panel driving method, the setup voltage of the reset pulse in the last subfield of the selective write subfield is lower than the setup voltage of the reset pulse in the first subfield of the selective write subfield.

As a second embodiment of the present invention, a plasma display panel driving method in which a plurality of subfields having different number of emission times is divided into a reset period, an address period, and a sustain period to implement an image is performed in the reset period of the remaining subfields except the first subfield. And performing a reset discharge by sequentially supplying a selective reset pulse of a square waveform and a selective reset pulse of a ramp-down to the scan electrodes of the cells discharged by the sustain pulse supplied from the previous subfield. After the reset discharge, the scan is performed. Supplying a scan pulse to the electrode and supplying a data pulse to the address electrode in synchronization with the scan pulse to perform an address discharge, and after the address discharge, supplying a sustain pulse alternately to the scan electrode and the sustain electrode to sustain Discharging.

At this time, the selective reset pulse voltage of the square waveform supplied to the scan electrode is the same as the voltage of the sustain pulse supplied in the previous subfield.

The selective reset pulse sustain period of the rectangular waveform supplied to the scan electrode is smaller than the sustain period of the sustain pulse supplied from the previous subfield.

The selective reset pulse holding period of the square waveform supplied to the scan electrode is 0.1 ms to 1 ms.

The sustain period of the selective reset pulse supplied to the scan electrode is different within the range of 0.1 k? To 1 k? Depending on the amount of sustain discharge in each subfield.

In the plasma display panel driving method, when a reset pulse of a rampdown waveform is supplied to all subfields, the voltage applied to the sustain electrode is a positive voltage lower than that of the sustain pulse.

In addition, in the plasma display panel driving method as described above, the voltage of the scan pulse supplied to the scan electrode is a negative voltage of -100 V or less with respect to the base voltage of the scan electrode.

At this time, the selective reset pulse of the ramp-down waveform supplied to the scan electrode when set down is characterized in that the voltage down to the scan pulse supplied to the scan electrode.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

<First Embodiment>

5 is a view showing a driving waveform in the PDP driving method according to the first embodiment of the present invention. Referring to FIG. 5, the PDP of the present invention which is driven in parallel with the selective write subfield and the selective erase subfield has a ramp-up waveform formed on the scan electrode Y during the reset period of the selective write subfield SW. Following the reset pulse RP, the reset pulse (-RP) of the rampdown waveform is supplied sequentially. However, in the reset periods SU and SD of the remaining selective write subfields except for the first subfield SW1 and the last subfield SW_last of the selective write subfield section, that is, at the time of setup of the reset period (SU) ramp-up. The reset pulse RP 'of the square waveform is supplied instead of the reset pulse RP of the waveform, followed by the reset pulse (-RP') of the ramp-down waveform at the time of set down (SD).

In this way, the reset pulse (RP ') of the square waveform supplied during the set-up (SU) of the reset period and the reset pulse (-RP') of the ramp-down waveform supplied (SD) of the set-down (SD) are sustained in the previous subfield. Irrespective of it, it is not supplied to all the discharge cells, but only to the scan electrodes Y of the cells discharged by the sustain pulses Suspy and Suspz.

In the present invention, as described above, the reset pulses RP 'and -RP' supplied only to the cells discharged by the sustain pulses Suspy and Suspz in the previous subfield are referred to as 'selective reset pulses'.

The setup voltage SU_Vs of the selective reset pulse is supplied at the same voltage as the voltage Vs of the sustain pulse supplied in the previous subfield. That is, the selective reset pulses RP 'and -RP' substantially discharge the sustain pulses by supplying sustain pulses having the same square wave as the sustain pulses Suspy supplied in the previous subfield.

At this time, the reset discharge period caused by the selective reset pulses RP 'and -RP' is to maintain a discharge different from the sustain discharge period generated in the previous subfield. That is, the sustain period t1 of the selective reset pulse has a shorter period than the sustain period t2 of the sustain pulse supplied in the previous subfield. Preferably, the sustain period t1 of the selective reset pulse has a range of 0.1 ms to 1 ms. This is to homogenize the wall charges of the sustain discharge cells and the non-sustain discharge cells in the previous subfield so that the addressing discharge subsequent to the reset discharge by the selective reset pulse is uniformly generated.

Meanwhile, the sustain period t1 of the selective reset pulse may be set differently for each subfield of the selective write subfield. This is because the wall charges of the cells participating in the sustain discharge are not the same after the sustain discharge generated by supplying different numbers of sustain pulses to each subfield. Therefore, it is preferable that the sustain period t1 of the selective reset pulse is set differently according to the sustain discharge amount in each subfield, and the sustain period t1 of the selective reset pulse is differently set within the range of 0.1 ms to 1 ms.

In the address period, while the voltage is applied to the sustain electrode Z, the negative scan pulse (-Swsp ') and the positive data pulse DP are supplied to the scan electrode Y and the address electrode X to be synchronized with each other. do. More specifically, the sustain electrode Z is applied to the scan electrode Y or the sustain electrode Z during the reset period and the address period during which the ramp-down waveform is supplied in all the selective write subfields SW1, SW2, .. SW_last. The positive voltage Vz lower than the voltage Vs of the sustain pulse is supplied. This is to increase the potential difference between the scan electrode (Y) and the sustain electrode (Z) to increase the efficiency of the selective erase discharge that occurs when the selective reset pulse of the ramp-down waveform to the scan electrode (Y).

In addition, the scan electrode Y is formed on the scan electrode Y to sufficiently address the discharge between the scan electrode Y to which the scan pulse (-Swsp ') is supplied and the address electrode X to which the data pulse DP is supplied. A negative voltage (-Vw ') of -100 V or less is applied to the ground voltage (GND) of.

On the other hand, the present invention adjusts the sustain period t1 of the selective reset pulse so that all the discharge cells have a uniform wall charge during the addressing discharge, so a driving deviation may occur in actual driving, causing unstable address discharge. Therefore, the selective reset pulse (-RP ') of the ramp-down waveform supplied to the scan electrode (Y) when set down (SD) is the voltage of the scan pulse (-Swsp') applied to the scan electrode (Y) for the addressing discharge. It is lowered to make stable address discharge.

In addition, since the PDP of the present invention drives the selective write subfield SWSF and the selective erase subfield SESF in parallel, the setup of the reset pulse supplied from the selective write subfield SW_last before the selective erase subfield SESF. When the voltage SU_V 'is equal to the setup voltage SU_V of the reset pulse supplied from the first subfield SW1, over discharge may occur during addressing discharge. Of course, the setup voltage SU_V 'of the reset pulse in the last subfield SW_last of the selective write subfield SWSF may be supplied in the same manner as the setup voltage SU_V of the reset pulse supplied in the first subfield SW1. However, preferably, a voltage lower than the setup voltage SU_V of the reset pulse supplied from the first subfield SW1 is supplied.

As described above, the PDP of the present invention driven according to the PDP driving waveform of the first embodiment selectively resets and discharges only the cells discharged with the same voltage as the sustain voltage Vs in the selective write subfield SWSF. By applying a high voltage to the cell, it is possible to improve the deterioration of the contrast characteristic caused by the reset discharge. In addition, the PDP according to the first embodiment of the present invention can be driven with a shorter reset period (SU, SD) than the reset period in the conventional PDP driving, thereby improving the driving margin.

Second Embodiment

6 is a view showing a driving waveform in the PDP driving method according to the second embodiment of the present invention. Referring to FIG. 6, the PDP of the present invention in which a subfield having a different number of light emission times is divided into a reset period, an address period, and a sustain period is driven, except for the first subfield SW1, and the remaining subfields SW2, SW3, ...). In the reset period (SU, SD) of the interval, the reset pulse (RP ') of the square waveform at the time of setup (SU) is supplied, followed by the reset pulse (-RP') of the ramp-down waveform at the time of set down (SD). do.

In this way, the reset pulse (RP ') of the square waveform supplied during the set-up (SU) of the reset period and the reset pulse (-RP') of the ramp-down waveform supplied (SD) of the set-down (SD) are sustained in the previous subfield. Irrespective of it, it is not supplied to all the discharge cells, but only to the scan electrodes Y of the cells discharged by the sustain pulses Suspy and Suspz.

In the present invention, as described above, the reset pulses RP 'and -RP' supplied only to the cells discharged by the sustain pulses Suspy and Suspz in the previous subfield are referred to as 'selective reset pulses'.

The setup voltage SU_Vs of the selective reset pulse is supplied at the same voltage as the voltage Vs of the sustain pulse supplied in the previous subfield. That is, the selective reset pulses RP 'and -RP' substantially discharge the sustain pulses by supplying sustain pulses having the same square wave as the sustain pulses Suspy supplied in the previous subfield.

At this time, the reset discharge period caused by the selective reset pulses RP 'and -RP' is to maintain a discharge different from the sustain discharge period generated in the previous subfield. That is, the sustain period t1 of the selective reset pulse has a shorter period than the sustain period t2 of the sustain pulse supplied in the previous subfield. Preferably, the sustain period t1 of the selective reset pulse has a range of 0.1 ms to 1 ms. This is to homogenize the wall charges of the sustain discharge cells and the non-sustain discharge cells in the previous subfield so that the addressing discharge subsequent to the reset discharge by the selective reset pulse is uniformly generated.

Meanwhile, the sustain period t1 of the selective reset pulse may be set differently for each subfield of the selective write subfield. This is because the wall charges of the cells participating in the sustain discharge are not the same after the sustain discharge generated by supplying different numbers of sustain pulses to each subfield. Therefore, it is preferable that the sustain period t1 of the selective reset pulse is set differently according to the sustain discharge amount in each subfield, and the sustain period t1 of the selective reset pulse is differently set within the range of 0.1 ms to 1 ms.

In the address period, while the voltage is applied to the sustain electrode Z, the negative scan pulse (-Swsp ') and the positive data pulse DP are supplied to the scan electrode Y and the address electrode X to be synchronized with each other. do. More specifically, the sustain electrode Z is applied to the scan electrode Y or the sustain electrode Z during the reset period and the address period during which the ramp-down waveform is supplied in all the selective write subfields SW1, SW2, .. SW_last. The positive voltage Vz lower than the voltage Vs of the sustain pulse is supplied. This is to increase the potential difference between the scan electrode (Y) and the sustain electrode (Z) to increase the efficiency of the selective erase discharge that occurs when the selective reset pulse of the ramp-down waveform to the scan electrode (Y).

In addition, the scan electrode Y is formed on the scan electrode Y to sufficiently address the discharge between the scan electrode Y to which the scan pulse (-Swsp ') is supplied and the address electrode X to which the data pulse DP is supplied. A negative voltage (-Vw ') of -100 V or less is applied to the ground voltage (GND) of.

On the other hand, the present invention adjusts the sustain period t1 of the selective reset pulse so that all the discharge cells have a uniform wall charge during the addressing discharge, so a driving deviation may occur in actual driving, causing unstable address discharge. Therefore, the selective reset pulse (-RP ') of the ramp-down waveform supplied to the scan electrode (Y) when set down (SD) is the voltage of the scan pulse (-Swsp') applied to the scan electrode (Y) for the addressing discharge. It is lowered to make stable address discharge.

As described above, the PDP of the present invention driven according to the PDP driving waveform of the second embodiment is sustained with the same voltage as the sustain voltage Vs in the remaining subfields SW1, SW2, ... except for the first subfield SW1. Since only a discharge cell is selectively reset discharged, a high voltage is applied to all discharge cells regardless of whether or not sustain discharge is applied in all subfield sections in the related art, thereby improving the reduction in contrast characteristics caused by reset discharge. In addition, the PDP according to the second embodiment of the present invention can be driven in a shorter reset period (SU, SD) than the reset period in the conventional PDP driving, thereby improving the driving margin.

As described above, it will be understood by those skilled in the art that the above-described technical configuration may be implemented in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, the above-described embodiments are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the appended claims rather than the detailed description, and the meaning and scope of the claims and All changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

As described above, the present invention improves the contrast characteristics in both the plasma display panel driven by the selective writing method and the selective erasing method by changing the reset pulses supplied in the reset period or the plasma display panel driven by the selective writing method. The driving margin can be secured at the same time.

Claims (17)

A method of driving a plasma display panel in which a plurality of subfields including an optional write subfield having a different number of emission and a selective erase subfield are divided into a reset period, an address period, and a sustain period to implement an image. In the reset period of the remaining selective write subfield except for the first subfield and the last subfield of the selective write subfield, a rectangular waveform selective reset pulse and a ramp are applied to the scan electrodes of the cells discharged by the sustain pulse in the previous selective write subfield. Supplying a selective reset pulse of the down sequentially to perform a reset discharge; Supplying a scan pulse to the scan electrode after the reset discharge, and supplying a data pulse to the address electrode in synchronization with the scan pulse to perform an address discharge; And After the address discharge, supplying sustain pulses alternately to the scan electrodes and the sustain electrodes to perform sustain discharge; Plasma display panel driving method comprising a. The method of claim 1, And the setup voltage of the selective reset pulse supplied to the scan electrode is the same as the voltage of the sustain pulse supplied in the previous subfield. The method of claim 2, And the sustain period of the selective reset pulse supplied to the scan electrode is smaller than the sustain period of the sustain pulse supplied from the previous subfield. The method of claim 3, wherein And a sustain period of the selective reset pulse supplied to the scan electrode is 0.1 ms to 1 ms. The method of claim 4, wherein The sustain period of the selective reset pulse supplied to the scan electrode is different within the range of 0.1 mW to 1 mW depending on the sustain discharge amount of each subfield. The method of claim 1, And when a reset pulse of a rampdown waveform is supplied in all selective write subfields, the voltage applied to the sustain electrode is a positive voltage lower than that of the sustain pulse. The method of claim 1, The voltage of the scan pulse supplied to the scan electrode is a plasma display panel driving method, characterized in that the negative voltage of -100V or less with respect to the base voltage of the scan electrode. The method of claim 1, And a selective reset pulse of a rampdown waveform supplied to the scan electrode when set down is lowered to a voltage of the scan pulse supplied to the scan electrode. The method of claim 1, And the setup voltage of the reset pulse in the last subfield of the selective write subfield is lower than the setup voltage of the reset pulse in the first subfield of the selective write subfield. A method of driving a plasma display panel in which a plurality of subfields having different emission counts are divided into a reset period, an address period, and a sustain period to implement an image During the reset period of the remaining subfields except the first subfield, a reset waveform of a square waveform and a selective reset pulse of ramp-down are sequentially supplied to the scan electrodes of the cells discharged by the sustain pulses supplied from the previous subfield. Discharging; Supplying a scan pulse to the scan electrode after the reset discharge, and supplying a data pulse to the address electrode in synchronization with the scan pulse to perform an address discharge; And After the address discharge, supplying sustain pulses alternately to the scan electrodes and the sustain electrodes to perform sustain discharge; Plasma display panel driving method comprising a. The method of claim 10, And the setup voltage of the selective reset pulse supplied to the scan electrode is the same as the voltage of the sustain pulse supplied in the previous subfield. The method of claim 11, And the sustain period of the selective reset pulse supplied to the scan electrode is smaller than the sustain period of the sustain pulse supplied from the previous subfield. The method of claim 12, And a sustain period of the selective reset pulse supplied to the scan electrode is 0.1 ms to 1 ms. The method of claim 13, The sustain period of the selective reset pulse supplied to the scan electrode is different within the range of 0.1 mW to 1 mW depending on the sustain discharge amount of each subfield. The method of claim 10, And when a reset pulse of a rampdown waveform is supplied in all subfields, the voltage applied to the sustain electrode is a positive voltage lower than that of the sustain pulse. The method of claim 10, The voltage of the scan pulse supplied to the scan electrode is a plasma display panel driving method, characterized in that the negative voltage of -100V or less with respect to the base voltage of the scan electrode. The method of claim 10, And a selective reset pulse of a rampdown waveform supplied to the scan electrode when set down is lowered to a voltage of the scan pulse supplied to the scan electrode.

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