KR20060003609A - Liquid crystal display having multi domain and panel for the same - Google Patents

Abstract

A storage electrode line including a gate line and a storage electrode is formed on an insulating substrate, and a data line intersecting and intersecting with the gate line and a coupling electrode overlapping the storage electrode are formed on an upper portion of the gate insulating layer covering the insulating line. In the upper portion of the passivation layer covering the gate electrode and the data line, a second pixel capacitively coupled to the first pixel electrode overlapping the first pixel electrode and the coupling electrode connected to the drain electrode and the coupling electrode for each pixel region defined by the intersection of the gate line and the data line. The pixel electrode is formed. In this case, the passivation layer includes a first insulating layer of silicon nitride and a second insulating layer of an organic material, and a portion of the second insulating layer is removed from the overlapping portion of the second pixel electrode and the coupling electrode, so that the second pixel electrode and the coupling electrode are formed of the first insulating layer. The coupling capacitance is formed by overlapping only the insulating film therebetween.

LCD, vertical alignment, cutout, coupling electrode, coupling capacitance

Description

Multi-domain liquid crystal display and display panel used therefor {LIQUID CRYSTAL DISPLAY HAVING MULTI DOMAIN AND PANEL FOR THE SAME}

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a layout view of an opposing display panel for a liquid crystal display according to an exemplary embodiment of the present invention;

3 is a layout view of a liquid crystal display according to an exemplary embodiment of the present invention;

4 is a cross-sectional view of the liquid crystal display of FIG. 3 taken along the line IV-IV ';

5 is a circuit diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

6A, 7A, 8A, and 10A are layout views in an intermediate step of a method of manufacturing the thin film transistor array panel of the liquid crystal display device shown in Figs. 1 to 4 according to one embodiment of the present invention, in the order thereof; The drawings listed,

FIG. 6B is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 6A taken along the line VIb-VIb ′.

FIG. 7B is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 7B taken along the line VIIb-VIIb ′.

FIG. 8B is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 8A taken along the line VIIIb-VIIIb ′.

FIG. 9 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 8A taken along the line VIIIb-VIIIb ′, and illustrates the next step of FIG. 8B.

FIG. 10B is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 10A taken along the line Xb-Xb ′, and illustrates the next step of FIG. 9.

FIG. 11 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 10A taken along the line Xb-Xb ′, and illustrates the next step of FIG. 10.

12 is a layout view illustrating a structure of a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 13 is a cross-sectional view of the liquid crystal display of FIG. 12 taken along the line XII-XII ′. FIG.

121 gate lines, 124 gate electrodes,

131, 133 sustain electrode, 151, 154 semiconductor

161, 163, 165 resistive contact members 176 coupling electrodes,

171 data lines, 173 source electrodes,

175 drain electrodes, 190 pixel electrodes,

191, 192, 193 incisions, 270 counter electrodes,

271, 272, 273 incisions, 801, 802 first and second insulating films

The present invention relates to a multi-domain liquid crystal display device and a display panel used therefor.

In general, a liquid crystal display device injects a liquid crystal material between an upper display panel on which a common electrode and a color filter are formed, and a lower display panel on which a thin film transistor and a pixel electrode are formed. By applying a different voltage to form an electric field to change the arrangement of the liquid crystal molecules, and through this to adjust the transmittance of light to represent the image.

However, it is an important disadvantage that the liquid crystal display device has a narrow viewing angle. In order to overcome these disadvantages, various methods for widening the viewing angle have been developed. Among them, liquid crystal molecules are oriented vertically with respect to the upper and lower display panels, and a method of forming a constant incision pattern or forming protrusions on the pixel electrode and the common electrode that is opposite thereto. This is becoming potent.

As a method of forming an incision pattern, an incision pattern is formed on each of the pixel electrode and the common electrode, and the viewing angle is widened by adjusting the direction in which the liquid crystal molecules lie down using a fringe field formed by the incision patterns. .

The protrusions are formed by forming protrusions on the pixel electrode and the common electrode formed on the upper and lower display panels, respectively, to adjust the lying direction of the liquid crystal molecules using an electric field distorted by the protrusions.

In another method, an incision pattern is formed on the pixel electrode formed on the lower panel, and protrusions are formed on the common electrode formed on the upper panel, so that the liquid crystal lies down using a fringe field formed by the incision pattern and the protrusion. There is a way to form a domain by controlling.

In such a multi-domain liquid crystal display, the gray scale inversion reference viewing angle defined as a contrast ratio reference viewing angle based on a contrast ratio of 1:10 or a limit angle of luminance inversion between gray scales is excellent, more than 80 ° in all directions. However, the gamma curve of the front side and the gamma curve of the side do not coincide with each other, resulting in inferior visibility in the left and right sides. For example, in the patterned vertically aligned (PVA) mode, which makes an incision by domain dividing means, the screen looks brighter and the color tends to shift toward white as the side faces. Occasionally, the picture appears clumped and disappears. However, as liquid crystal display devices are used for multimedia in recent years, visibility has become increasingly important as pictures and moving pictures are viewed.

The technical problem to be achieved by the present invention is to implement a multi-domain liquid crystal display device having excellent visibility.

In order to solve this problem, the present invention divides the pixel electrode into at least two sub pixel electrodes, and different potentials are applied to the sub pixel electrodes.                     

In the thin film transistor array panel according to the exemplary embodiment of the present invention, first and second signal lines that are insulated and intersect each other are formed on the insulating substrate, and the first and second signal lines intersect and define a first pixel area for each pixel region. The pixel electrode is formed. Each pixel region includes a first thin film transistor having three terminals connected to a first signal line, a second signal line, and a first pixel electrode, and at least one second capacitively coupled to the first pixel electrode. The pixel electrode is formed. In this case, the first pixel electrode and the second pixel electrode are connected to the first pixel electrode and electrically connected to each other through a coupling electrode overlapping the second pixel electrode, and a passivation layer between the first and second pixel electrodes and the coupling electrode. Although at least a portion overlapping with the second pixel electrode has a thickness thinner than that of the other portion.

The thin film transistor array panel further includes a storage electrode line having a storage electrode overlapping the coupling electrode to form a storage capacitor, and the boundary of the storage electrode is positioned within the boundary of the coupling electrode.

The passivation layer includes a first insulating film made of an inorganic insulating material and a second insulating film made of an organic insulating material, and the second insulating film is removed at a portion where the coupling electrode and the second pixel electrode overlap, so that the second insulating film exposes the first insulating film. It is preferable to have an opening.

 The coupling electrode is preferably separated from the drain electrode among the three terminals of the thin film transistor.

At least one of the first pixel electrode and the second pixel electrode has domain dividing means, and the first and second pixel electrodes are substantially mirror-symmetrical with respect to the upper and lower bisectors of the pixel region, and the first pixel electrode and the second pixel The long side of the boundary lines adjacent to each other of the electrode preferably forms 45 ° with the first signal line.

In the liquid crystal display according to the exemplary embodiment of the present invention, a gate line including a gate electrode is formed on the first insulating substrate, an amorphous silicon layer is formed on the gate insulating layer covering the gate line, and at least a portion of the amorphous silicon is formed. A data line including a source electrode formed on the layer, at least a portion of which is formed on the amorphous silicon layer, a drain electrode facing the source electrode is formed, a coupling electrode is formed on the gate insulating film, and a data line and the drain electrode And a passivation layer covering the coupling electrode, the upper portion of the coupling electrode having a thickness thinner than the remaining portion, wherein the first pixel electrode connected to the drain electrode and the coupling electrode and at least a portion of the coupling electrode overlap each other. A thin film transistor array panel on which two pixel electrodes are formed; First common electrode on the second insulating substrate which faces the insulating substrate is includes a facing panel is formed.

At this time, the first domain dividing means formed on at least one of the first substrate and the second substrate and at least one of the first substrate and the second substrate, together with the first domain dividing means, form a plurality of small domains. It may include a second domain splitting means for dividing into.

Preferably, the first domain dividing means is a cutout of at least one of the first pixel electrode and the second pixel electrode, and the second domain dividing means is a cutoff of the common electrode.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Next, a structure of a liquid crystal display according to an exemplary embodiment of the present invention and a thin film transistor array panel used therein will be described with reference to the accompanying drawings.

1 is a layout view of a thin film transistor substrate for a liquid crystal display device according to an embodiment of the present invention, FIG. 2 is a layout view of a color filter substrate for a liquid crystal display device according to an embodiment of the present invention, and FIG. 4 is a layout view of a liquid crystal display according to an exemplary embodiment, and FIG. 4 is a cross-sectional view of the liquid crystal display of FIG. 3 taken along the line IV-IV '.

The liquid crystal display device is formed of a liquid crystal molecule that is formed between the thin film transistor array panel 100 on the lower side and the upper opposing display panel 200 facing them, and is substantially perpendicular to the two display panels 100 and 200. It consists of a liquid crystal layer 3 comprising 310. In this case, the alignment layers 11 and 21 are formed inside the display panels 100 and 200, and the alignment layers 11 and 21 form liquid crystal molecules 310 of the liquid crystal layer 3 with respect to the display panels 100 and 200. It is preferred that there is a vertical alignment mode that allows it to be oriented vertically, but may not. In addition, upper and lower polarizers 12 and 22 are attached to outer surfaces of the upper panel 200 and the lower panel 100, respectively.

First, the lower thin film display panel has the following configuration.

The first substrate is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) on the insulating substrate 110 made of a transparent insulating material such as glass, and is separated through the cutouts 191 and 193. And second pixel electrodes 190a and 190b. The first pixel electrode 190a is connected to the thin film transistor to receive an image signal voltage, and the second pixel electrode 190b overlaps the coupling electrode 176 connected to the first pixel electrode 190a to form a first pixel. It is electromagnetically coupled (capacitively coupled) with the pixel electrode 190a. In this case, the thin film transistor is connected to the gate line 121 transmitting the scan signal and the data line 171 transmitting the image signal, respectively, to turn on the image signal applied to the first pixel electrode 190a according to the scan signal. on) off. The second pixel electrode 190b has a cutout 192. Here, the first and second pixel electrodes 190a and 190b may not be made of a transparent material in the case of a reflective liquid crystal display device, and in this case, the lower polarizer 12 is also unnecessary.

Next, the configuration of the upper opposing display panel is as follows.

It is also made of a black matrix 220 to prevent light leakage on the lower surface of the insulating substrate 210 made of a transparent insulating material such as glass, a color filter 230 of red, green, and blue and a transparent conductive material such as ITO or IZO. The common electrode 270 is formed. Here, the cutouts 271, 272, and 273 are formed in the common electrode 270. The black matrix 220 may be formed not only in the peripheral portion of the pixel region but also in the portion overlapping the cutouts 271, 272, and 273 of the common electrode 270. This is to prevent light leakage caused by the cutouts 271, 272, and 273.

Next, the thin film transistor array panel 100 will be described in more detail.

In the thin film transistor array panel 100, a plurality of gate lines 121 may be formed on the lower insulating substrate 110 to transfer gate signals. The gate line 121 mainly extends in the horizontal direction, and a part of each gate line 121 forms a plurality of gate electrodes 124. The gate electrode 124 is formed in the form of a protrusion in the gate line 121, and as shown in the present embodiment, the gate line 121 may have a contact portion for transmitting a gate signal from the outside to the gate line 121. In this case, the end portion 129 of the gate line 121 has a wider width than the other portion, but in other cases, the end portion of the gate line 121 of the gate driving circuit is formed directly on the substrate 110. It is directly connected to the output.

The storage electrode line 131 extends in the horizontal direction on the same layer as the gate line 121, and each of the storage electrode lines 131 includes a storage electrode 133 having a wider width than other portions.

The gate line 121 and the storage electrode line 131 are made of metal such as Al, Al alloy, Ag, Ag alloy, Cr, Ti, Ta, Mo, or the like. Although the gate line 121 and the storage electrode line 131 of the present embodiment are formed of a single layer, the gate line 121 and the sustain electrode line 131 may include a metal layer such as Cr, Mo, Ti, Ta, etc. having excellent physicochemical properties, and an Al or Ag-based metal layer having a small specific resistance. It may be made of a double layer. In addition, the gate line 121 and the storage electrode line 131 may be made of various metals or conductors.

The sidewalls of the gate line 121 and the storage electrode line 131 are inclined, and the inclination angle with respect to the horizontal plane is 30 to 80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) or the like is formed on the gate line 121 and the storage electrode line 131.

A plurality of drain electrodes 175, including a plurality of data lines 171, are formed on the gate insulating layer 140. Each data line 171 extends mainly in a vertical direction and has a source electrode 173 extending from the data line 171 by extending a plurality of branches toward each drain electrode 175. The contact unit 179 located at one end of the data line 171 transfers an image signal from the outside to the data line 171.

In addition, a coupling electrode 176 is formed on the same layer as the data line 171 to form the storage capacitor Cst (see FIG. 5) with the gate insulating layer 140 interposed therebetween. At this time, the coupling electrode 176 is separated from the drain electrode 175, but these 175 and 176 may be connected. In this case, the coupling electrode 176 may be disposed to overlap the storage electrode 133 to prevent the aperture ratio of the pixel from decreasing, and the boundary of the storage electrode 133 may be located within the boundary of the coupling electrode 176.

The data line 171, the drain electrode 175, and the coupling electrode 176 may be formed of chromium (Cr), aluminum (Al), molybdenum (Mo), titanium (Ti), tantalum (Ta), or the like as the gate line 121. Alloys containing an alloying metal of the element (for example, Al-Nd, Mo-N, Mo-Nb) to these conductive materials, and a single film thereof or a multilayer film containing them (for example, Mo / Al -Nd / Mo, Cr / Al).

Under the data line 171 and the drain electrode 175, a plurality of linear semiconductors 151 that extend mainly vertically along the data line 171 are formed. Each linear semiconductor 151 made of amorphous silicon extends toward each gate electrode 124, the source electrode 173, and the drain electrode 175 to have a channel portion 154.

Between the semiconductor 151, the data line 171, and the drain electrode 175, a plurality of linear ohmic contacts 161 and island-like ohmic contacts 165 for reducing contact resistance therebetween, respectively. Is formed. The ohmic contact 161 is made of amorphous silicon doped with silicide or n-type impurities at a high concentration, and has an ohmic contact 163 extending into a branch, and the island-type ohmic contact 165 has a gate electrode 124. Facing the ohmic contact 163.

On the data line 171 and the drain electrode 175, a-Si: C: O, a-Si formed by plasma enhanced chemical vapor deposition (PECVD), an organic material having excellent planarization characteristics, and photosensitivity. A protective film 180 made of a low dielectric constant insulating material such as: O: F or silicon nitride is formed. In this case, the passivation layer 180 may include a first insulating layer 801 made of silicon nitride or silicon oxide and a second insulating layer 802 made of an organic insulating material. In another embodiment in which the red, green, and blue color filters 230 are formed on the thin film transistor array panel 100, the second insulating layer 802 may include or may include an insulating layer of the red, green, and blue color filters 230. It can be replaced by a color filter layer.

The passivation layer 180 includes a plurality of contact holes 182 and 185 exposing at least a portion of the drain electrode 175 and an end portion 179 of the data line 171, respectively, and the end of the gate line 121. A plurality of contact holes 181 exposing a portion of the portion 129 penetrate the gate insulating layer 140 and the passivation layer 180. In addition, the passivation layer 180 is provided with a contact hole 186 exposing the coupling electrode 176. The contact hole 186 is formed only in the first insulating layer 801, and the contact hole is formed in the second insulating layer 802. The opening 188 exposing the first insulating layer 801 over the coupling electrode 176 is provided as well as 186.

A plurality of contact assistants 81 and 82 including a plurality of pixel electrodes are formed on the passivation layer 180. The pixel electrodes 190a and 190b and the contact assistants 81 and 82 may be transparent conductors such as indium tin oxide (ITO) or indium zinc oxide (IZO), or opaque conductors having excellent light reflection characteristics such as aluminum (Al). Is made with.

The plurality of pixel electrodes include a first pixel electrode 190a and a second pixel electrode 190b separated through the cutouts 91 and 193, and the first pixel electrode 190a includes contact holes 186 and 185. The drain electrode 175 and the coupling electrode 176 are connected to each other, and the second pixel electrode 190b overlaps the coupling electrode 176. Accordingly, a coupling capacitor Ccp (see FIG. 5) is formed between the second pixel electrode 190b and the coupling electrode 176, whereby the second pixel electrode 190b is formed on the first pixel electrode 190a by electrons. Miraculously bound (capacitively coupled). At this time, the second pixel electrode 190b is polymerized with the coupling electrode 176 with only the first insulating film 801 exposed through the opening 188 interposed therebetween, so that a narrow overlapping area is sufficient between them 190b and 176. Coupling capacity can be formed. In addition, when the storage capacitor overlaps with the first or second pixel electrodes 190a and 190b to form the storage capacitor, the coupling electrode 176 and the storage electrode 133 connected to the first pixel electrode 190a may have a gate insulating film ( Since only 140 is overlapped, sufficient holding | maintenance capacity can be formed between these 133 and 176 with a narrow overlap area. In addition, in the same structure as in the present embodiment, the coupling electrode 176 and the storage electrode 133 are overlapped with each other while sufficiently securing the coupling capacitance and the storage capacitance, thereby sufficiently securing the aperture ratio of the pixel.

The boundary dividing the first pixel electrode 190a and the second pixel electrode 190b is divided into portions perpendicular to the portions 191 and 193 forming 45 ° with respect to the gate line 121, and forming a 45 ° portion. The length of the two parts 191 and 193 is longer than that of the vertical part. In addition, the two portions 191 and 193 constituting 45 ° are perpendicular to each other.

The second pixel electrode 190b has a cutout 192, and the cutout 192 penetrates from the right side of the second pixel electrode 190b toward the left side, and the inlet is widened.

The first pixel electrode 190a and the second pixel electrode 190b respectively have a line (a line parallel to the gate line) that bisects a pixel area defined by the intersection of the gate line 121 and the data line 171 up and down. It is substantially mirror symmetrical.

The contact auxiliary members 81 and 82 are connected to the end portion 129 of the gate line and the end portion 179 of the data line through the contact holes 181 and 182, respectively.

Meanwhile, a black matrix 220 is formed on the upper insulating substrate 210 to prevent light leakage. The red, green, and blue color filters 230 are formed on the black matrix 220. The common electrode 270 having a plurality of cutouts 271, 272, and 273 is formed on the color filter 230. The common electrode 270 is formed of a transparent conductor such as ITO or indium zinc oxide (IZO).

A pair of cutouts 271, 272, and 273 of the common electrode 270 has a portion 191, 193 formed at 45 ° with respect to the gate line 121 among the boundary of the two pixel electrodes 190a and 190b. It includes a diagonal portion parallel to the side and an end portion overlapping the sides of the pixel electrode 190. At this time, the end is classified into a longitudinal end part and a horizontal end part.

At this time, the incisions (271, 272, 273) that is a domain regulatory means includes a notch cut in a narrow, it may have a triangular or square or trapezoidal or semi-circular shape. The notch may be convex or concave. The notch determines the alignment direction of the liquid crystal molecules 310 positioned at the domain boundary corresponding to the cutouts 271, 272, and 273. Accordingly, the liquid crystal molecules 310 arranged at the boundary of the domain may be stably and regularly arranged through the notches, thereby preventing the occurrence of spots or afterimages at the domain boundary, and incisions 271, 272, and 273. ) Can be narrowed to increase brightness. In this case, one or more notches may be disposed in one domain regulating means, and a plurality of notches may be alternately arranged with concave notches. In addition, although the notches are disposed only on the cutouts 271, 272, and 273 of the common electrode 270, the notches may be disposed on the cutouts 191, 192, and 193 of the pixel electrode 190. The thin film transistor array panel 100 or the opposing display panel 200 may be disposed on both sides.

When the thin film transistor array panel and the color filter display panel having the above structure are aligned and combined, and a liquid crystal material is injected and vertically aligned therebetween, the basic structure of the liquid crystal display according to the exemplary embodiment of the present invention is provided.

When the thin film transistor array panel and the color filter panel are aligned, the cutouts 271, 272, and 273 of the common electrode 270 divide the two pixel electrodes 190a and 190b into a plurality of sub-areas, respectively. In the present embodiment, as illustrated in FIG. 3, the two pixel electrodes 190a and 190b are respectively divided into four sub-regions. As can be seen in FIG. 3, each subregion is elongated to distinguish the width direction from the length direction.

The portion of the liquid crystal layer 3 between each subregion of the pixel electrodes 190a and 190b and the corresponding subregion of the reference electrode 270 is referred to as a subregion in the future, and these small regions are applied with an electric field. Four types are classified according to the average major axis direction of the liquid crystal molecules located inside the cell, which is called a domain in the future.

In the liquid crystal display having the structure, the first pixel electrode 190a receives an image signal voltage through the thin film transistor, whereas the voltage of the second pixel electrode 190b varies due to capacitive coupling with the coupling electrode 176. Therefore, the absolute value of the voltage of the second pixel electrode 190b is always lower than that of the first pixel electrode 190b. As such, when two pixel electrodes having different voltages are disposed in one pixel region, different gamma curves may be formed through the two pixel electrodes, and the gamma curves may be compensated for each other to reduce distortion of the gamma curve. Through this, excellent visibility can be secured.

Next, the reason why the voltage of the first pixel electrode 190a is lower than the voltage of the second pixel electrode 190b will be described with reference to FIG. 5.

5 is a circuit diagram illustrating a liquid crystal display according to a first exemplary embodiment of the present invention.

In FIG. 5, Clca represents a liquid crystal capacitor formed between the first pixel electrode 190a and the common electrode 270, and Cst represents a storage capacitor formed between the first pixel electrode 190a and the storage electrode line 131. . Clcb represents the liquid crystal capacitance formed between the second pixel electrode 190b and the common electrode 270, and Ccp represents between the coupling electrode 176 and the second pixel electrode 190b connected to the first pixel electrode 190a. The binding capacity formed is shown.

When the voltage of the first pixel electrode 190a with respect to the voltage of the common electrode 270 is called Va, and the voltage of the second pixel electrode 190b is called Vb, according to the voltage division law,

Va = Vb × [Ccp / (Ccp + Clcb)]

Since Ccp / (Ccp + Clcb) is always less than 1, Vb is always smaller than Va.

 On the other hand, by adjusting Ccp, the ratio of Vb to Va can be adjusted. The adjustment of Ccp is possible by adjusting the overlapping area and distance of the coupling electrode 176 and the second pixel electrode 190b. The overlapping area can be easily adjusted by changing the width of the coupling electrode 176, and the distance can be adjusted by changing the formation position of the coupling electrode 176. That is, in the exemplary embodiment of the present invention, the coupling electrode 176 is formed on the same layer as the data line 171, but the coupling electrode 176 and the second pixel electrode 190b are formed on the same layer as the gate line 121. You can increase the distance between them.

Then, referring to FIGS. 6A to 11B and FIGS. 1, 3, and 4 for a method of manufacturing the thin film transistor array panel for the liquid crystal display device shown in FIGS. 1, 3, and 4 according to an embodiment of the present invention. This will be described in detail.

6A, 7A, 8A, and 10A are layout views in an intermediate step of a method of manufacturing the thin film transistor array panel of the liquid crystal display device shown in Figs. 1 to 4 according to one embodiment of the present invention, in the order thereof; 6B is a cross-sectional view of the thin film transistor array panel of FIG. 6A taken along the line VIb-VIb ', and FIG. 7B is a cross-sectional view of the thin film transistor array panel of FIG. 7B taken along the line VIIb-VIIb'. 8B is a cross-sectional view of the thin film transistor array panel of FIG. 8A taken along the line VIIIb-VIIIb ', and FIG. 9 is a cross-sectional view of the thin film transistor array panel of FIG. 8A taken along the line VIIIb-VIIIb'. FIG. 8B is a diagram illustrating a next step, and FIG. 10B is a cross-sectional view taken along the line Xb-Xb ′ of the thin film transistor array panel illustrated in FIG. 10A, and illustrates the next step of FIG. 9. Park shown at 10a The transistor panel as a sectional view taken along the Xb-Xb 'line, a diagram illustrating the steps of Figure 10b.

First, two layers of metal films are sequentially stacked on an insulating substrate 110 made of transparent glass by sputtering. In this case, the metal film may be laminated with a metal having excellent contact characteristics with IZO or ITO, for example, a lower film such as molybdenum, molybdenum alloy or chromium and an upper film made of an aluminum-based metal.

6A and 6B, the metal film is patterned by a photolithography process using a photoresist pattern to include a gate line 121 including a plurality of gate electrodes 124 and a plurality of sustain electrodes 133. The storage electrode line 131 is formed.

As shown in FIGS. 7A and 7B, three layers of a gate insulating film 140, intrinsic amorphous silicon, and an impurity amorphous silicon layer are sequentially stacked. Subsequently, the impurity amorphous silicon layer and the intrinsic amorphous silicon layer are photo-etched to form a linear intrinsic semiconductor 151 each including a plurality of linear impurity semiconductors 164 and a plurality of protrusions 154. As the material of the gate insulating film 140, silicon nitride is preferable, and the lamination temperature is preferably 250 to 500 占 폚 and a thickness of about 2,000 to 5,000 Pa.

Next, the aforementioned conductive material is sequentially stacked by sputtering to form a metal film, and as shown in FIGS. 8A and 8B, the metal film is patterned in sequence to form a plurality of coupling electrodes 176 and a plurality of sources. A plurality of data lines 171 and a plurality of drain electrodes 175 respectively including the electrodes 173 are formed.

Subsequently, the impurity semiconductor exposed without being covered with the data line 171, the drain electrode 175, and the coupling electrode 176 while the photoresist layer on the data line 171 and the drain electrode 175 is removed or left as it is. 164, the plurality of linear resistive contact members 161 and the plurality of island resistive contact members 165 each including a plurality of protrusions 163 are completed to remove portions of the intrinsic semiconductor 151 thereunder. Expose

Subsequently, in order to stabilize the surface of the portion of the intrinsic semiconductor 151, oxygen plasma is preferably followed.

Next, as shown in FIG. 9, the protective film 180 is formed by sequentially stacking the first insulating film 801 of the inorganic insulating film such as silicon nitride and the second insulating film 802 of the organic insulating film having a low dielectric constant. The photoresist film is applied to the upper part by spin coating, and then the photoresist patterns 52 and 54 are formed by a photographic process using a mask.

At this time, the thickness of the developed photoresist film varies depending on the position, and the photoresist film is composed of first to third portions whose thickness becomes smaller. The first part located in the area A (hereinafter referred to as "other area") and the second part located in the area C (hereinafter referred to as "coupling area") are denoted by 52 and 54, respectively, and the area B (hereinafter referred to as "contact area"). Reference numerals have not been given to the third portion located at " " because the third portion has a thickness of zero, thereby revealing the second insulating film 802 below.

As described above, there may be various methods of varying the thickness of the photoresist film according to the position, and the transparent mask and the light blocking area as well as the translucent area may be provided in the exposure mask. Yes. The translucent region is provided with a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness.

Next, as shown in FIGS. 10A and 10B, the second insulating film 802 and the first insulating film 801 are sequentially etched using the photoresist patterns 52 and 54 as etch masks, so that the drain electrode 175 and the coupling electrode ( Contact holes 185 and 186 exposing 176, respectively. In this case, contact holes 181 and 82 exposing end portions 129 and 179 of the gate line 121 and the data line 171 are also formed. Subsequently, the second portion 54 remaining in the bonding region C is removed by ashing.

Next, as shown in FIG. 11, a portion of the second insulating film 802 exposed in the bonding region C is etched to form an opening 188 in the second insulating film 802.

At this time, in another embodiment in which the second insulating film 802 is formed of the photosensitive organic insulating material, the second insulating film 802 is formed in the same manner as the photosensitive film patterns 52 and 54, and then the etching process is performed in the above-described order. .

Finally, as illustrated in FIGS. 1, 3, and 4, a 500 μm to 1,500 μm thick IZO or ITO layer is deposited by a sputtering method and etched to photograph the plurality of pixel electrodes 190a and 190b and the plurality of contacts. The auxiliary members 81 and 82 are formed. In the case of using the IZO layer, the etching is preferably a wet etching using an etching solution for chromium such as (HNO 3 / (NH 4) 2 Ce (NO 3) 6 / H 2 O), since the etching solution does not corrode aluminum. ), The aluminum conductive film may be prevented from corroding in the drain electrode 175 and the gate line 121.

Meanwhile, in the liquid crystal display according to another exemplary embodiment, the thin film transistor array panel may have a different structure, which will be described in detail with reference to the accompanying drawings.                     

FIG. 12 is a layout view illustrating a structure of a liquid crystal display according to another exemplary embodiment. FIG. 13 is a cross-sectional view of the liquid crystal display of FIG. 12 taken along the line XII-XII ′.

12 to 13, the layer structure of the thin film transistor array panel for a liquid crystal display device according to the present embodiment is generally the same as the layer structure of the thin film transistor array panel for liquid crystal display devices shown in FIGS. 1, 3, and 4. Do. That is, the plurality of linear semiconductors including the plurality of gate lines 121 including the plurality of gate electrodes 124 is formed on the substrate 110, and the gate insulating layer 140 and the plurality of protrusions 154 thereon. 151, a plurality of linear ohmic contact members 161 each including a plurality of protrusions 163, and a plurality of island type ohmic contact members 165 are sequentially formed. A plurality of data lines 171 including a plurality of source electrodes 153, a plurality of drain electrodes 175, and a plurality of coupling electrodes 176 are formed on the ohmic contacts 161 and 165 and the gate insulating layer 140. The protective film 180 including the first insulating film 801 and the second insulating film 802 is formed thereon. A plurality of contact holes 182, 185, 186, and 181 are formed in the passivation layer 180 and / or the gate insulating layer 140, and the plurality of pixel electrodes 190a and 190b are contacted with the passivation layer 180. Members 81 and 82 are formed.

However, unlike the thin film transistor array panel illustrated in FIGS. 1, 3, and 4, in the thin film transistor array panel according to the present exemplary embodiment, the semiconductor 151 may include the data line 171 except for the protrusion 154 in which the thin film transistor is located. The planar shape is substantially the same as the drain electrode 175 and the ohmic contacts 161 and 165 below. In detail, the linear semiconductor 151 may include the source electrode 173 and the drain electrode (aside from the data line 171 and the drain electrode 175 and the portions below the ohmic contacts 161 and 165 below). 175) has exposed portions between them.

Of course, the thin film transistor array panel for the liquid crystal display according to the present exemplary embodiment includes the coupling electrode 176, and the amorphous silicon layers 156 and 166 are formed under the coupling electrode 176 in the same shape.

In the method of manufacturing the thin film transistor array panel, similarly to the case of patterning the passivation layer 190, a photoresist pattern having a different thickness is formed. This photoresist pattern is composed of first to third portions whose thickness becomes smaller. 9, the first part corresponds to the "wiring area", the second part corresponds to the channel area, and corresponds to the reference numerals 52 and 54, respectively. Subsequently, a plurality of data lines 171, a plurality of drain electrodes 175, and a coupling electrode 176 including a plurality of source electrodes 173 are formed through a series of etching steps, and the plurality of protrusions 163 are formed. A plurality of linear semiconductor contacts 161 including a plurality of linear ohmic contact members 161, a plurality of island type ohmic contact members 165, and a plurality of protrusions 154 are formed.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights. In particular, the arrangement of the cutouts formed in the pixel electrode and the common electrode may be variously modified.

Through the above configuration, the side angle of the liquid crystal display device can be improved, and the viewing angle can be extended. In addition, when forming the storage capacitor, the storage electrode and the coupling electrode are overlapped with only the gate insulating film interposed therebetween, and when the coupling capacitor is formed, the sub pixel electrode and the coupling electrode are overlapped with only a part of the passivation layer interposed therebetween, so that a narrow overlapping area is achieved. By sufficiently securing the storage capacitor and the coupling capacitor, the aperture ratio of the pixel can be ensured.

Claims (16)

Insulation board, A first signal line formed on the insulating substrate, A second signal line insulated from and intersecting the first signal line, A first pixel electrode formed in each pixel region defined by the crossing of the first signal line and the second signal line; A thin film transistor having three terminals connected to the first signal line, the second signal line, and the first pixel electrode, respectively; At least one second pixel electrode formed in each of the pixel regions and capacitively coupled to the first pixel electrode; A coupling electrode connected to the first pixel electrode and overlapping the second pixel electrode; A passivation layer formed between the first and second pixel electrodes and the coupling electrode, wherein at least a portion overlapping with the second pixel electrode has a thickness thinner than that of other portions; Thin film transistor array panel comprising a. In claim 1, And a storage electrode line having a storage electrode overlapping the coupling electrode to form a storage capacitor. In claim 2, The boundary of the sustain electrode is positioned within the boundary of the coupling electrode. In claim 1, The passivation layer may include a first insulating film made of an inorganic insulating material and a second insulating film made of an organic insulating material. In claim 4, And the second insulating film is removed at a portion where the coupling electrode and the second pixel electrode overlap, and the second insulating film has an opening that exposes the first insulating film. In claim 1, And at least one of the first pixel electrode and the second pixel electrode has domain dividing means. In claim 1, And the coupling electrode is separated from a drain electrode among three terminals of the thin film transistor. In claim 1, The thin film transistor array panel of claim 1, wherein the first and second pixel electrodes are substantially mirror-symmetric with respect to upper and lower bisectors of the pixel region. In claim 8, The long side of the adjacent boundary lines between the first pixel electrode and the second pixel electrode is 45 ° with the first signal line. First insulating substrate, A gate line formed on the first insulating substrate and including a gate electrode; A gate insulating film formed on the gate line, An amorphous silicon layer formed on the gate insulating film, A data line formed on the gate insulating layer, the data line including a source electrode formed on at least a portion of the amorphous silicon layer; A drain electrode formed on at least a portion of the amorphous silicon layer and facing the source electrode, A coupling electrode formed on the gate insulating film, A passivation layer formed on the data line, the drain electrode, and the coupling electrode, the upper portion of the coupling electrode having a thickness thinner than the remaining portion; A first pixel electrode formed on the passivation layer and connected to the drain electrode and the coupling electrode; At least one second pixel electrode insulated from the first pixel electrode and overlapping at least a portion of the coupling electrode; A second insulating substrate facing the first insulating substrate, The common electrode formed on the second insulating substrate Liquid crystal display comprising a. In claim 10, And a storage electrode line having a storage electrode overlapping the coupling electrode to form a storage capacitor. In claim 11, The boundary of the sustain electrode is positioned within the boundary of the coupling electrode. In claim 10, The passivation layer may include a first insulating film made of an inorganic insulating material and a second insulating film made of an organic insulating material. In claim 13, And the second insulating film is removed at a portion where the coupling electrode and the second pixel electrode overlap, and the second insulating film has an opening that exposes the first insulating film. In claim 10, First domain dividing means formed on at least one of the first insulating substrate and the second insulating substrate, Second domain dividing means formed on at least one of the first substrate and the second substrate and dividing the pixel region into a plurality of small domains together with the first domain dividing means; Liquid crystal display comprising a. The method of claim 15, And the first domain dividing means is a cutout portion of at least one of the first pixel electrode and the second pixel electrode, and the second domain dividing means is a cut portion of the common electrode.

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