KR20060001406A - Driving method of plasma display panel - Google Patents

Abstract

An object of the present invention is to provide a stable driving method of a plasma display panel.

In order to achieve the above object, the present invention provides a reset period for initializing the state of each cell by the falling ramp signal, the rising ramp signal, and the erasing ramp signal, an address period for selecting one of the cells to be addressed, and an addressed cell. A method of driving a plasma display panel by a drive signal having a sustain discharge period for causing a sustain discharge to occur, the method comprising the steps of: (a) detecting a temperature or a load rate of the panel; (b) controlling the arrival time of the rising final voltage or the falling final voltage in consideration of the slope of each ramp signal that is changed by the detected temperature or load rate; (c) A method of controlling a plasma display panel is provided, wherein the plasma display panel is controlled to have a sustain period of a predetermined period after reaching the rising final voltage or the falling final voltage.

Description

Driving method of plasma display panel {Driving method of plasma display panel}

1 is a view showing the structure of a conventional three-electrode surface discharge plasma display panel.

2 is a timing diagram for explaining an example of a conventional driving signal for driving a plasma display panel.

3 is a timing diagram illustrating a driving signal in which a slope of a rising / falling ramp signal is changed according to a panel temperature or a load ratio in a reset period among conventional driving signals.

4 is a block diagram schematically illustrating a driving apparatus for performing a method of driving a plasma display panel according to the present invention.

5 is a flowchart illustrating a method of stably driving a plasma display panel in a reset period of the present invention.

FIG. 6 is a timing diagram illustrating a driving signal in which a slope of a rising / falling ramp signal changes according to a panel temperature or a load ratio in a reset period of the present invention.

Explanation of symbols on main parts of drawing

Vs ... oil dielectric voltage

Vs + Vset ... Rising final voltage                 

Vnf ... falling final voltage

R1 ... ramp-up signal application time of Figure 6

T1a, T1f, T1s ... Rising final voltage arrival time of Figs. 6 (a), (b) and (c)

T2, Tb, Tc ... Falling ramp signal application time of Figs. 6 (a), (b), (c)

T2a, Tbf, Tcs ... Falling final voltage arrival time of Figs. 6 (a), (b) and (c)

Tr ... FIG. 6 rising final voltage holding period

Tf ... falling duration of falling final voltage of Fig. 6

The present invention relates to a plasma display panel, and more particularly, to a method of driving a plasma display panel.

1 is a view showing the structure of a conventional three-electrode surface discharge plasma display panel.

Referring to FIG. 1, between the front and rear glass substrates 100 and 106 of a conventional surface discharge plasma display panel 1, the address electrode lines A1, A2, ..., Am), As dielectric layer 102, 110, Y electrode lines Y1, ..., Yn, X electrode lines X1, ..., Xn, phosphor layer 112, partition 114 and protective layer, for example A magnesium monoxide (MgO) layer 104 is provided.

Address electrode lines A1, A2, ..., Am) is formed in a predetermined pattern on the front side of the rear glass substrate 106. The lower dielectric layer 110 includes the address electrode lines A1, A2, ..., Am) is applied to the front. In front of the lower dielectric layer 110, barrier ribs 114 may include address electrode lines A1,. A2, ..., It is formed in a direction parallel to Am). The partition walls 114 function to partition a predetermined area of each display cell and to prevent optical interference between each display cell. The phosphor layer 112 is formed between the partition walls 114.

The X electrode lines X1, ..., Xn and the Y electrode lines Y1, ..., Yn are the address electrode lines A1, ... A2, ..., It is formed in a predetermined pattern on the back of the front glass substrate 100 to be orthogonal to Am). Each intersection sets a corresponding display cell. Each X electrode line (X1, ..., Xn) and each Y electrode line (Y1, ..., Yn) have conductivity and transparent electrode line (Xna, Yna) of transparent conductive material such as ITO (Indium Tin Oxide) Metal electrode lines (Xnb, Ynb) to increase the can be formed by combining. The front dielectric layer 102 is formed by applying the entire surface to the rear of the X electrode lines X1, ..., Xn and the Y electrode lines Y1, ..., Yn. A protective layer 104 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying a front surface to the back of the front dielectric layer 102. The plasma forming gas is sealed in the discharge space 108.

2 is a timing diagram for explaining an example of a conventional driving signal for driving a plasma display panel. One subfield SF includes a reset period PR, an address period PA, and a sustain discharge period PS.

The reset period PR applies a reset pulse to all of the scan lines of all groups and forcibly performs a write discharge, thereby initializing the wall charge states of all cells. The reset period PR is carried out before entering the address period PA, which is carried out over the entire screen, thus making it possible to create a fairly even and evenly distributed wall charge arrangement. The cells initialized by the reset period PR have similar wall charge conditions inside the cells. The address period PA is performed after the reset period PR is performed. At this time, in the address period PA, the bias voltage Ve is applied to the sustain electrode X, and the scan electrodes Y1 to Yn and the address electrodes A1 to Am are simultaneously turned on at the cell positions to be displayed. Select the cell. After the address period PA is performed, the sustain pulse Vs is alternately applied to the sustain electrodes X and the scan electrodes Y1 to Yn to perform the sustain discharge period PS. During the sustain discharge period PS, a low level voltage VG is applied to the address electrodes A1-Am. In PDP, the brightness is adjusted by the number of sustain discharge pulses. If the number of sustain discharge pulses in one subfield or one TV field is large, the luminance increases.

3 is a timing diagram illustrating a driving signal in which a slope of a rising / falling ramp signal is changed according to a panel temperature or a load ratio in a reset period among conventional driving signals.

Referring to the drawings, FIG. 3A shows a drive signal having a normal rising ramp slope and falling ramp slope in a reset period. Once the sustain discharge voltage is applied to the scan electrode Y, a rising lamp signal having a slope Vset / (T1a-T1) of Sr is applied from the time of T1 and during the rising final voltage holding period (Trf-T1a). A falling ramp signal with a slope ((Vs-vnf) / (T2a-T2)) of Sf is applied from the time of T2, maintaining the rising final voltage, and falling last during the falling final voltage holding period (Trs-T2a). Keep the voltage. The slope of the rising ramp signal or the slope of the falling ramp signal is affected by the temperature or the load factor of the plasma display panel. Here, the load ratio means the ratio of the cells that are turned on among all the cells, and when all the cells are turned on, the load ratio becomes 100%.

Figure 3 (b) is an embodiment in which the slope of the rising ramp signal and the slope of the falling ramp signal is sharply affected by the temperature of the panel or the load factor. The rising ramp signal having the slope Vset / (T1b-T1) of Srb is applied, and the rising final voltage holding period is (T2-T1b). Further, a falling ramp signal having a slope ((Vs-Vnf) / (T2b-T2)) of Sfb is applied, and the falling final voltage holding period is (Trs-T2b).

3C is another embodiment in which the slope of the rising ramp signal and the slope of the falling ramp signal are sharply affected by the temperature or the load factor of the panel. The rising ramp signal having the slope Vset / (T1c-T1) of Src is applied, and the rising final voltage holding period is (T2-T1c). Further, a falling ramp signal having a slope of Sfc ((Vs-Vnf) / (T2c-T2)) is applied, and the falling final voltage holding period is (Trs-T2c).

In comparison with the inclination of FIG. 3, the rising ramp signal is Srb> Sr> Src and the falling ramp signal is Sfb> Sf> Sfc. This is due to the influence of the temperature of the panel or the load factor. Conventionally, as shown in FIG. Enough time is allowed for + Vset) to be applied. In addition, even when the falling ramp signal is applied, sufficient time is ensured that the falling final voltage Vnf is applied regardless of the influence of the panel state in a certain period from T2 to Trs. However, when the ramp has a steep slope for applying the rising ramp signal or the falling ramp signal in the reset period, the rising end voltage holding period or the falling end voltage holding period is relatively excessively long as shown in FIG. In this case, the rising final voltage holding period or the falling final voltage holding period may be too short, so that reset discharge may not be performed properly.

In order to solve the above problems, an object of the present invention is to provide a stable driving method of a plasma display panel.

In order to achieve the above object, the present invention provides a reset period for initializing the state of each cell by the falling ramp signal, the rising ramp signal, and the erasing ramp signal, an address period for selecting a cell to be addressed among the cells, and the addressing. A method of driving a plasma display panel by a drive signal having a sustain discharge period for causing a sustain discharge to occur in a discharged cell,

(a) detecting the temperature or load factor of the panel;

(b) controlling the arrival time of the rising final voltage or the falling final voltage in consideration of the slope of each ramp signal that is changed by the detected temperature or load rate;

(c) A method of driving a plasma display panel, the control method having a sustain period of a predetermined period after the rising end voltage or the falling end voltage is reached, respectively.

According to another aspect of the present invention, in the step (b), when the detected temperature is higher than the reference temperature, the inclination of each lamp signal is increased, thereby reducing the arrival time of the rising final voltage or the falling final voltage. ,

If the detected temperature is lower than the reference temperature, the slope of each lamp signal is gentle, so that the arrival time of the rising final voltage or the falling final voltage can be increased.

According to still another aspect of the present invention, the step (b) reduces the arrival time of the rising final voltage or the falling final voltage since the slope of each ramp signal becomes sharp when the detected load ratio is smaller than the mood loading ratio. ,

When the detected load ratio is larger than the reference load ratio, the slope of each ramp signal becomes gentle, so that the arrival time of the rising final voltage or the falling final voltage can be increased.

The present invention also provides a computer readable recording medium having recorded thereon a program for executing the method on a computer, in order to achieve the above object.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

4 is a block diagram schematically illustrating a driving apparatus for performing a method of driving a plasma display panel according to the present invention.

Referring to FIG. 4, the driving of the plasma display panel is performed by first receiving an external image signal and outputting an internal image signal as an internal image signal through image processing. Driving the panel 1 by receiving an X driving control signal SX, a Y driving control signal SY, and a logic control unit 402 for outputting an address driving control signal SA and an address driving control signal SA. An address driver 406 for outputting an address drive signal for output, a Y driver 404 for outputting a Y drive signal for driving the panel 1 by receiving the Y drive control signal SY, and an X drive control signal ( An X driver 408 and a panel 1 which receive SX and output an X driving signal for driving the panel 1 are provided.

5 is a flowchart illustrating a method of stably driving a plasma display panel in a reset period of the present invention.

Referring to the drawings, first, the temperature or load rate of the panel is detected (S501).

The temperature of the panel can be detected using a temperature sensor inside the panel, and the load ratio can be detected in the logic controller 402 of FIG. 4.

Next, using the detected temperature or load rate, the arrival time of the rising end voltage or the falling end voltage of the rising ramp signal or the falling ramp signal in the reset period is controlled (S503).

The higher the temperature of the detected panel compared to the previously measured reference temperature, the smaller the RC time constant in the reset period. Since the RC time constant in the ramp signal is inclined, the slope of the ramp signal becomes larger when the RC time constant becomes smaller. In addition, when the panel temperature is lower than the reference temperature, the RC time constant in the reset period is increased, and thus the slope of the lamp signal is decreased.

On the other hand, if the detected load ratio becomes higher than the previously measured reference load ratio (for example, 50%), the RC time constant of the ramp signal becomes large, and thus the slope of the ramp signal becomes small. In addition, when the detected load rate is lower than the reference load rate, the RC time constant of the ramp signal is decreased, and thus the slope of the ramp signal is increased. Here, the load ratio means the ratio of the cells that are turned on among all the cells, so when all the cells are turned on, the load ratio becomes 100%.

Such a result is measured by experiment in advance, and the application time of the rising ramp signal or the falling ramp signal in the reset period is controlled in accordance with the detected temperature or load rate. For example, if a detection result with a large slope is obtained (when the detection temperature is higher than the reference temperature or the detection load ratio is smaller than the reference load ratio), the rising time of the rising or falling end voltage is controlled by controlling the application time of the ramp signal to be short. Allow voltage to be reached. Here, the rising final voltage is defined as the final voltage after the rising ramp signal is applied, and the falling final voltage is defined as the final voltage after the falling ramp signal.

On the other hand, if the detection result of decreasing slope (when the detection temperature is lower than the reference temperature or the detection load ratio is higher than the reference load ratio) is obtained, the ramp signal is applied for a long time to control the rising or falling final voltage. To reach. The control enables the rising or falling ramp signal to stably reach the rising final voltage or the falling final voltage according to the detected temperature or load rate. This may be performed through a microcomputer (not shown) in the logic controller 402 which outputs each driving control signal.

Next, after reaching the rising final voltage or falling final voltage, control is performed to have a final voltage holding period of a predetermined period, respectively (S505).

In step 501 (S501) to step 503 (S503), the inclination of the rising ramp signal or the falling ramp signal in the reset period is changed according to the detected temperature or load rate, and the application time of the ramp signal is also changed. However, the present invention is characterized in that the maintenance period of the final voltage is made constant once the final voltage is reached. Therefore, when the application time of the lamp signal is short due to the small slope and the application time of the lamp signal is shortened due to the increase of the slope, the same time is required to maintain the final voltage after reaching the final voltage. That is, the rising final voltage holding period is controlled to be a predetermined constant period, and the falling final voltage holding period is controlled to be a predetermined constant period. If the panel is hot due to high temperatures or low load rates, the reset period is reduced. Therefore, as compared with the conventional case, the subfield period consisting of the reset period, the address period, and the sustain discharge period is reduced, so that the subfield may be added in a frame composed of a plurality of subfields. When the panel temperature is low or the load factor is large and the slope is small, the reset period is extended, and the subfield period can be increased. This may be performed through a microcomputer (not shown) in the logic controller 402 which outputs each driving control signal.

FIG. 6 is a timing diagram illustrating a driving signal in which a slope of a rising / falling ramp signal changes according to a panel temperature or a load ratio in a reset period of the present invention.

Fig. 6A is a timing diagram showing a scanning signal in a normal reset period. First, the sustain discharge voltage Vs is applied at a predetermined time, and then a rising ramp signal having a slope of Sr is applied at the time of T1. After reaching the rising final voltage (Vs + Vset), the holding period of the rising final voltage becomes Tr, and the falling ramp signal having the slope of Sf (Vset / (T1a-T1)) is maintained at the time of T2, so that the falling final voltage is maintained. After reaching (Vnf), the falling final voltage is maintained for Tf. At this time, the reset period is PR1.

Fig. 6B is a timing chart of the scanning signal in the reset period when the panel temperature of the present invention is high or the load factor is low.

As in FIG. 6A, the rising ramp signal starts to be applied at the time point T1. If the detected panel temperature is higher than the reference temperature or the detected load rate is lower than the reference load rate, the RC time constant affecting the slope of the ramp function decreases, so that the slope becomes sharp. Therefore, the applied time of the lamp function is controlled by using the detected temperature or load rate so that the lamp function can reach the final voltage. By the control, the rising final voltage (Vs + Vset) can be reached at the time of T1f, and thus the slope of the rising ramp function can be Srf (Vset / (T1f-T1)). Since the holding time of the rising final voltage is maintained in the present invention regardless of the temperature or the load rate of the panel, it can be controlled to maintain for the time of Tr. The falling ramp signal starts to be applied at the time Tb, and at this time, the application time of the falling ramp function is controlled by using the detected temperature or load rate. By this control, the falling final voltage can be reached at the time point of Tbf, and accordingly, the slope of the falling ramp function may be Sff ((Vs-Vnf) / (Tbf-Tb)). Since the duration of the falling final voltage is maintained in the present invention regardless of the temperature or the load rate of the panel, it can be controlled to be maintained for the time of Tf. Therefore, as the ramp signal becomes steep, the reset period is reduced to PR2, which is shorter than the normal reset period PR1 shown in Fig. 6A. When the reset period is reduced, the subfield period consisting of the reset period, the address period, and the sustain discharge period is reduced, so that the frame time composed of the plurality of subfields can be reduced, so that the subfield can be further configured during the conventional frame time. It becomes possible.

Fig. 6C is a timing chart of the scanning signal in the reset period when the panel temperature is low or the load factor is high.

As in FIGS. 6A and 6B, the rising ramp signal starts to be applied at the time T1. When the temperature of the detected panel is lower than the reference temperature or the detected load rate is higher than the reference load rate, the RC time constant affecting the slope of the ramp function increases, so that the slope becomes gentle. Since the case where the slope is gentle may not be reached until the final voltage, the present invention controls the application time of the lamp function so that the lamp function can reach the final voltage using the detected temperature or load rate. By the control, the rising final voltage (Vs + Vset) can be reached at the time point of T1s, and the slope of the rising ramp function can be Srs (Vset / (T1s-T1)). Since the sustain time of the rising final voltage is maintained in the present invention regardless of the temperature or the load rate of the panel, it can be controlled to maintain for the time of Tr. The falling ramp signal starts to be applied at the time point Tc, and at this time, the application time of the falling ramp function is controlled by using the detected temperature or load rate. By this control, the falling final voltage can be reached at the time point of Tcs, and accordingly, the slope of the falling ramp function may be Sfs ((Vs-Vnf) / (Tcs-Tc)). Since the duration of the falling final voltage is maintained in the present invention regardless of the temperature or the load rate of the panel, it can be controlled to be maintained for the time of Tf. Therefore, as the ramp signal becomes gentle, the reset period is increased to PR3, which is PR1, which is the normal reset period shown in Fig. 6A, and PR2, which is the reset period shown in Fig. 6B. Done. When the reset period is increased, the subfield period composed of the reset period, the address period, and the sustain discharge period is increased.

The panel driving method according to the present invention can be embodied as computer readable codes on a computer readable recording medium. Computer-readable recording media include any type of recording device that stores programs or data that can be read by a computer system. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, hard disk, floppy disk, flash memory, optical data storage, and the like. Here, the program stored in the recording medium refers to a series of instruction instructions used directly or indirectly in an apparatus having an information processing capability such as a computer to obtain a specific result. Therefore, the term computer is used to mean all devices having information processing capability for performing a specific function by a program including a memory, an input / output device, and an arithmetic device despite the fact that the name is actually used. In the case of a device for driving a panel, its use is limited to a specific field of panel driving, and in reality, it is a kind of computer.

In particular, the panel driving method according to the present invention is written in a schematic or ultra-high-speed integrated circuit hardware description language (VHDL) or the like on a computer, and connected to a computer-programmable integrated circuit such as a field programmable gate array (FPGA). Can be implemented. The recording medium includes such a programmable integrated circuit.

According to the present invention as described above, the following effects can be obtained.

First, in the present invention, by detecting the temperature of the panel affecting the change of the slope of the rising ramp signal or the falling ramp signal within the reset period, or by detecting the load ratio, the application time of each ramp signal is appropriately controlled, thereby increasing the final final voltage in the reset period. Alternatively, the initializing discharge is stably caused by reaching the falling final voltage.

Secondly, by maintaining the rising final voltage holding period and the falling final voltage holding period constant as in the related art, the reset time is selectively reduced or increased so that the subfield can be further configured for the extra period. To make efficient use of.                     

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (4)

A reset period for initializing the state of each cell by the falling ramp signal, the rising ramp signal, and the erasing ramp signal, an address period for selecting one of the cells to be addressed, and a sustaining discharge period for causing sustain discharge in the addressed cells. In the method for driving the plasma display panel by a drive signal provided, (a) detecting the temperature or load factor of the panel; (b) controlling the arrival time of the rising final voltage or the falling final voltage in consideration of the slope of each ramp signal that is changed by the detected temperature or load rate; and (c) controlling to have a sustain period of a predetermined period after reaching the rising final voltage or the falling final voltage, respectively. The method of claim 1, wherein step (b) When the detected temperature is higher than the reference temperature, the slope of each lamp signal is sharp, so that the arrival time of the rising final voltage or the falling final voltage is reduced, And when the detected temperature is lower than the reference temperature, the slope of each lamp signal becomes gentle, thereby increasing the arrival time of the rising final voltage or the falling final voltage. The method of claim 1, wherein step (b) When the detected load ratio is smaller than the reference load ratio, the slope of each ramp signal is sharp, so that the arrival time of the rising final voltage or the falling final voltage is reduced, And when the detected load ratio is greater than a reference load ratio, the slope of each lamp signal becomes gentle, thereby increasing the arrival time of the rising final voltage or the falling final voltage. A computer-readable recording medium having recorded thereon a program for executing the method of any one of claims 1 to 3.

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