KR20050122643A - Method of forming a metal line in a semiconductor device - Google Patents
Method of forming a metal line in a semiconductor device Download PDFInfo
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- KR20050122643A KR20050122643A KR1020040048243A KR20040048243A KR20050122643A KR 20050122643 A KR20050122643 A KR 20050122643A KR 1020040048243 A KR1020040048243 A KR 1020040048243A KR 20040048243 A KR20040048243 A KR 20040048243A KR 20050122643 A KR20050122643 A KR 20050122643A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
Abstract
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 소정의 구조가 형성된 반도체 기판 상부에 희생막을 형성한 후 상기 희생막을 패터닝하여 비아홀 및 트렌치를 형성하는 단계와, 상기 비아홀 및 트렌치가 형성된 희생막을 포함한 전체 구조 상부에 확산 방지막 및 구리층을 형성한 후 연마하여 구리 배선을 형성하는 단계와, 상기 희생막을 제거하여 상기 구리 배선을 잔류시키는 단계와, 전체 구조 상부에 다공성 저유전 절연막을 형성한 후 연마하는 단계를 포함하여 확산 방지막의 불연속적인 증착에 의해 발생되는 구리의 외부 확산을 방지할 수 있어 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법이 제시된다. The present invention relates to a method of forming a metal wiring of a semiconductor device, and comprising forming a via hole and a trench by forming a sacrificial film on a semiconductor substrate having a predetermined structure and then patterning the sacrificial film, and forming a sacrificial film having the via hole and a trench formed therein. Forming a diffusion barrier and a copper layer on the entire structure, and then polishing and forming copper wiring; removing the sacrificial film to leave the copper wiring; and forming a porous low dielectric insulating film on the entire structure. A method of forming a metal wiring of a semiconductor device, including polishing, may prevent external diffusion of copper generated by discontinuous deposition of a diffusion barrier, thereby improving device reliability.
Description
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 희생막 패턴을 이용하여 구리 배선을 먼저 형성한 후 다공성 저유전 절연막을 형성하여 확산 방지막의 불연속적인 증착에 의해 발생되는 구리의 외부 확산을 방지할 수 있어 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device. In particular, copper wirings are first formed using a sacrificial film pattern, and then a porous low dielectric insulating film is formed to prevent external diffusion of copper generated by discontinuous deposition of a diffusion barrier. The present invention relates to a method for forming a metal wiring of a semiconductor device that can be prevented and the reliability of the device can be improved.
반도체 소자의 고집적 및 고속화가 진행되면서, 4.0∼4.2 정도의 유전율을 갖는 SiO2막으로 된 통상의 절연막은 소자의 구동 속도 향상을 방해하는 요인으로 작용하게 된다. 즉, 반도체 소자의 고집적화는 필연적으로 셀 영역의 크기 감소를 수반하게 되는데, 셀 영역의 크기가 감소되면 이웃하는 금속 배선들간의 기생 캐패시턴스가 증가되어 RC 지연이 증가하게 되기 때문에 소자의 구동 속도를 향상시키는데 한계를 갖게 된다. 따라서, 고속 소자를 구현하기 위해 저유전 절연막을 반도체 제조 공정에 적용하려는 연구가 활발하게 진행되고 있다.As the integration and speed of the semiconductor device progress, the conventional insulating film made of SiO 2 film having a dielectric constant of about 4.0 to 4.2 acts as a factor that hinders the driving speed of the device. In other words, high integration of semiconductor devices inevitably entails a reduction in the size of the cell region, and as the size of the cell region decreases, parasitic capacitance between neighboring metal wires increases, resulting in an increase in the RC delay, thereby improving the driving speed of the device. There is a limit to this. Therefore, studies are being actively conducted to apply a low dielectric insulating film to a semiconductor manufacturing process to realize a high speed device.
현재 알려진 저유전 절연막의 종류는 크게 유기물계의 폴리머와 무기물계의 SiOC막, 그리고 막 내부에 기공을 형성한 다공성막으로 분류될 수 있다. 여기서, 폴리머 및 SiOC막은 2.5∼2.7 정도의 낮은 유전율을 갖고 있으며, 특히 폴리머는 SiO2막의 대체 물질로서 그 이용이 점차 확대되고 있는 실정이다. 또한, 폴리머 및 SiOC막은 다공성막보다 상대적으로 높은 유전율을 나타내는 것으로 알려져 있어 다공성막에 대한 연구도 활발하게 진행되고 있다. 다공성막은 막내에 미세한 기공이 형성되어 2.2 이하의 낮은 유전율을 갖고 있어 금속 배선용으로 많은 연구가 이루어지고 있다.Currently known low-k dielectrics can be broadly classified into organic polymers, inorganic SiOC films, and porous films with pores formed therein. Here, the polymer and the SiOC film have a low dielectric constant of about 2.5 to 2.7, and in particular, the polymer is increasingly being used as an alternative material for the SiO 2 film. In addition, since the polymer and the SiOC film are known to exhibit a relatively higher dielectric constant than the porous film, research on the porous film is being actively conducted. Porous membranes have a low dielectric constant of 2.2 or less because fine pores are formed in the membrane, and much research has been made for metal wiring.
그러나, 다공성 저유전 절연막을 이용하여 금속 배선, 특히 구리를 이용한 금속 배선을 형성할 경우에는 다공성 저유전 절연막을 패터닝하여 다마신 패턴을 형성할 때 홀 또는 트렌치 측벽에 기공이 노출된다. 노출된 기공으로 인하여 확산 방지막이 불연속적으로 증착하게 되고, 이에 따라 구리의 외부 확산에 의한 신뢰성 문제가 야기된다. However, in the case of forming a metal wiring using a porous low dielectric insulating film, particularly a metal wiring using copper, pores are exposed in the hole or trench sidewall when the porous low dielectric insulating film is patterned to form a damascene pattern. The exposed pores cause the diffusion barrier to discontinuously deposit, thereby causing reliability problems due to external diffusion of copper.
본 발명의 목적은 다공성 저유전 절연막을 이용하여 구리 배선을 형성할 때 기공에 의한 확산 방지막의 불연속적인 증착에 의해 발생되는 구리의 외부 확산을 방지할 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a metal wiring of a semiconductor device capable of preventing external diffusion of copper caused by discontinuous deposition of a diffusion preventing film by pores when forming a copper wiring using a porous low dielectric insulating film. have.
본 발명의 다른 목적은 희생막 패턴을 이용하여 구리 배선을 먼저 형성한 후 다공성 저유전 절연막을 형성하여 확산 방지막의 불연속적인 증착에 의해 발생되는 구리의 외부 확산을 방지할 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는데 있다. Another object of the present invention is to first form a copper wiring by using a sacrificial film pattern, and then to form a porous low dielectric insulating film to prevent the metal diffusion of the copper caused by the discontinuous deposition of the diffusion barrier film of the metal wiring of the semiconductor device It is to provide a formation method.
본 발명에 따른 반도체 소자의 금속 배선 형성 방법은 소정의 구조가 형성된 반도체 기판 상부에 희생막을 형성한 후 상기 희생막을 패터닝하여 비아홀 및 트렌치를 형성하는 단계와, 상기 비아홀 및 트렌치가 형성된 희생막을 포함한 전체 구조 상부에 확산 방지막 및 구리층을 형성한 후 연마하여 구리 배선을 형성하는 단계와, 상기 희생막을 제거하여 상기 구리 배선을 잔류시키는 단계와, 전체 구조 상부에 다공성 저유전 절연막을 형성한 후 연마하는 단계를 포함한다.In the method of forming a metal wiring of a semiconductor device according to the present invention, after forming a sacrificial layer on a semiconductor substrate having a predetermined structure, patterning the sacrificial layer to form via holes and trenches, and including the sacrificial layer formed with the via holes and trenches. Forming a copper barrier by forming a diffusion barrier layer and a copper layer on top of the structure and removing the sacrificial layer, leaving the copper interconnect on the entire structure, and forming and polishing a porous low dielectric layer on the entire structure Steps.
상기 희생막은 감광막 및 절연막을 포함한다.The sacrificial film includes a photosensitive film and an insulating film.
상기 확산 방지막은 Ta계막, W계막 및 Ti계막중 어느 하나를 이용하여 PVD 방법으로 형성한다.The diffusion barrier is formed by PVD method using any one of Ta-based, W-based and Ti-based films.
상기 Ta계막은 Ta막, TaN막, TaSiN막 및 Ta/TaN막을 포함하고, 상기 W계막은 W막, WN막 및 WSiN막을 포함하며, 상기 Ti계막은 Ti막, TiN막, TiSiN막 및 Ti/TiN막을 포함한다. The Ta-based film includes a Ta film, a TaN film, a TaSiN film, and a Ta / TaN film. The W-based film includes a W film, a WN film, and a WSiN film. The Ti-based film includes a Ti film, a TiN film, a TiSiN film, and a Ti / TaN film. TiN film is included.
이하, 첨부된 도면을 참조하여 본 발명의 실시 예를 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;
도 1(a) 내지 도 1(c)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.1 (a) to 1 (c) are cross-sectional views of devices sequentially shown in order to explain a method for forming metal wirings of a semiconductor device according to the present invention.
도 1(a)를 참조하면, 소정의 구조가 형성된 반도체 기판(11) 상부에 희생막(12)을 형성한 후 소정의 마스크를 이용한 리소그라피 공정 및 현상 공정으로 비아홀 및 트렌치를 형성한다. 그리고, 희생막(12) 패턴을 포함한 전체 구조 상부에 확산 방지막(13) 및 구리층(14)을 형성한 후 이들을 연마하여 구리 배선을 형성한다. 여기서, 희생막(12)은 감광막 및 산화막등의 절연막을 포함한다. 확산 방지막(13)은 Ta계막, W계막 및 Ti계막을 이용하여 PVD 방법으로 형성하는데, Ta계막으로는 Ta, TaN, TaSiN, Ta/TaN의 적층막이 있으며, W계막으로는 W, WN, WSiN등이 있고, Ti계막으로는 Ti, TiN, TiSiN, Ti/TiN의 적층막이 있다.Referring to FIG. 1A, after the sacrificial layer 12 is formed on a semiconductor substrate 11 having a predetermined structure, via holes and trenches are formed by a lithography process and a development process using a predetermined mask. The diffusion barrier film 13 and the copper layer 14 are formed on the entire structure including the sacrificial film 12 pattern and then polished to form a copper wiring. Here, the sacrificial film 12 includes an insulating film such as a photosensitive film and an oxide film. The diffusion barrier 13 is formed by a PVD method using a Ta-based film, a W-based film, and a Ti-based film. The Ta-based film includes a laminated film of Ta, TaN, TaSiN, Ta / TaN, and the W-based film includes W, WN, and WSiN. The Ti-based film includes a laminated film of Ti, TiN, TiSiN, and Ti / TiN.
도 1(b)를 참조하면, 희생막(12)을 제거하여 구리 배선만을 잔류시킨다.Referring to FIG. 1B, the sacrificial film 12 is removed to leave only copper wiring.
도 1(c)를 참조하면, 전체 구조 상부에 다공성 저유전 절연막(15)을 형성한 후 연마하여 구리 배선이 노출되도록 한다. 다공성 저유전 절연막(15)은 다양한 방법으로 형성할 수 있는데, 그중 하나의 방법으로 졸(sol) 상태의 원물질(precursor)을 큐어링(curing)하는 과정에서 막 내부에 10∼30㎚의 작은 크기를 갖는 기공들을 형성시키거나, 원물질인 TEOS 파티클간에 약한 결합을 형성시킨 상태에서 원물질로부터 용매(solvent)를 급격히 제거함으로써 원물질이 다공성 구조를 그대로 유지하도록 하는 방식을 이용하고 있다. 여기서, 다공성막 내부의 실리카 망목과 기공 구조는 용매의 건조 방법에 따라 변화하게 된다. 예컨데, SOG막의 큐어링과 같은 어닐링 공정을 통해 원물질로부터 용매를 휘발시키게 되면 다공성 물질의 수축 과정에서 치밀한 구조를 갖은 물질이 형성되므로 원하는 저유전율의 다공성 실리카의 특성을 갖는 다공성막을 얻지 못하게 된다. 따라서, 다공성막은 용매의 삼중점 이상의 조건에서 용매를 급격히 제거하는 초임계 건조(supercritical drying) 방식에 의해 얻어질 수 있다. 또한, 다공성막을 형성하기 위한 다른 방법으로서 상압에서 특별한 용액으로 숙성하는 방식을 이용하고 있다. Referring to FIG. 1C, a porous low dielectric insulating film 15 is formed on the entire structure and then polished to expose the copper wirings. The porous low dielectric insulating film 15 may be formed by various methods, and in one of the methods, a small film having a thickness of 10 to 30 nm in the film is cured in the process of curing a raw material in a sol state. By forming pores having a size or a weak bond between TEOS particles, which are raw materials, the solvent is rapidly removed from the raw materials to maintain the porous structure. Here, the silica mesh and the pore structure inside the porous membrane are changed depending on the drying method of the solvent. For example, when the solvent is volatilized from the raw material through an annealing process such as curing of the SOG film, a material having a dense structure is formed during shrinkage of the porous material, thereby failing to obtain a porous film having characteristics of porous silica having a desired low dielectric constant. Accordingly, the porous membrane can be obtained by a supercritical drying method in which the solvent is rapidly removed at conditions above the triple point of the solvent. As another method for forming a porous membrane, a method of aging in a special solution at atmospheric pressure is used.
상술한 바와 같이 본 발명에 의하면 희생막 패턴을 이용하여 구리 배선을 먼저 형성한 후 다공성 저유전 절연막을 형성하여 확산 방지막의 불연속적인 증착에 의해 발생되는 구리의 외부 확산을 방지할 수 있어 소자의 신뢰성을 향상시킬 수 있다.As described above, according to the present invention, copper wiring is first formed using a sacrificial layer pattern, and then a porous low dielectric layer is formed to prevent external diffusion of copper generated by discontinuous deposition of the diffusion barrier layer, thereby ensuring reliability of the device. Can improve.
도 1(a) 내지 도 1(c)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도. 1 (a) to 1 (c) are cross-sectional views of devices sequentially shown to explain a method for forming metal wirings of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11 : 반도체 기판 12 : 희생막11 semiconductor substrate 12 sacrificial film
13 : 확산 방지막 14 : 구리층13 diffusion barrier 14 copper layer
15 : 다공성 저유전 절연막 15: porous low dielectric insulating film
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| KR1020040048243A KR20050122643A (en) | 2004-06-25 | 2004-06-25 | Method of forming a metal line in a semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20050122643A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9865810B2 (en) | 2014-12-17 | 2018-01-09 | SK Hynix Inc. | Electronic device and method for fabricating the same |
-
2004
- 2004-06-25 KR KR1020040048243A patent/KR20050122643A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9865810B2 (en) | 2014-12-17 | 2018-01-09 | SK Hynix Inc. | Electronic device and method for fabricating the same |
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