KR20050121443A - Semiconductor nanorod surface-treated with organic material - Google Patents
Semiconductor nanorod surface-treated with organic material Download PDFInfo
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- KR20050121443A KR20050121443A KR1020040046572A KR20040046572A KR20050121443A KR 20050121443 A KR20050121443 A KR 20050121443A KR 1020040046572 A KR1020040046572 A KR 1020040046572A KR 20040046572 A KR20040046572 A KR 20040046572A KR 20050121443 A KR20050121443 A KR 20050121443A
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- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 claims description 3
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- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 claims description 3
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- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- SBIBMFFZSBJNJF-UHFFFAOYSA-N selenium;zinc Chemical compound [Se]=[Zn] SBIBMFFZSBJNJF-UHFFFAOYSA-N 0.000 claims description 3
- 229910052717 sulfur Inorganic materials 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- 229910052720 vanadium Inorganic materials 0.000 claims description 3
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- 238000004381 surface treatment Methods 0.000 abstract 1
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- 239000011701 zinc Substances 0.000 description 2
- HIXDQWDOVZUNNA-UHFFFAOYSA-N 2-(3,4-dimethoxyphenyl)-5-hydroxy-7-methoxychromen-4-one Chemical compound C=1C(OC)=CC(O)=C(C(C=2)=O)C=1OC=2C1=CC=C(OC)C(OC)=C1 HIXDQWDOVZUNNA-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02603—Nanowires
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8611—Planar PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
Abstract
유기물로 표면처리하여 전기적 특성을 향상시킨 반도체 나노막대에 대해 개시한다. 그 나노막대는 비저항은 0.001 Ωcm 이상인 유기물을 이용하여 표면처리되어, 적어도 1층 이상으로 코팅된 다중벽 구조, 양자우물 혹은 초격자 구조, p-n 접합 구조, 이종접합 구조 및 동종접합 구조를 이루며, 전계트랜지스터, 쇼트키(schottky)다이오드, p-n 접합 다이오드, 발광소자, 센서, 로직회로, 나노시스템, 집적회로 및 광소자에 이용될 수 있다. Disclosed is a semiconductor nanorod having surface treatment with an organic material to improve electrical properties. The nanorods are surface-treated with organic materials with a resistivity of at least 0.001 Ωcm, forming a multiwall structure, a quantum well or superlattice structure, a pn junction structure, a heterojunction structure, and a homojunction structure coated with at least one layer. It can be used in transistors, schottky diodes, pn junction diodes, light emitting devices, sensors, logic circuits, nanosystems, integrated circuits and optical devices.
Description
본 발명은 반도체 나노막대에 관한 것으로, 보다 구체적으로 유기물을 이용하여 표면처리된 반도체 나노막대에 관한 것이다. The present invention relates to a semiconductor nanorod, and more particularly to a semiconductor nanorod surface-treated using an organic material.
최근 세계 각국에서는 반도체 나노막대를 이용한 나노소자가 개발이 치열하게 진행되고 있다. 특히, 나노미터 크기의 직경을 가지는 반도체 나노막대의 경우 단결정으로 이루어져 있기 때문에, 기존의 반도체 박막을 이용해서 제조한 트랜지스터보다 상호컨덕턴스(transconductance)와 전하이동도가 크게 향상될 것으로 기대되었다. Recently, the development of nano devices using semiconductor nanorods is intensifying in various countries. In particular, since a semiconductor nanorod having a nanometer diameter is composed of a single crystal, it is expected that the transconductance and the charge mobility are greatly improved compared to a transistor manufactured using a conventional semiconductor thin film.
도 1a는 산화아연 나노막대 전계트랜지스터의 드레인 전류-드레인 전압 (Id-Vd) 곡선이고, 도 2b는 드레인 전류-게이트 전압(Id-Vg) 곡선이다.FIG. 1A is a drain current-drain voltage (I d -V d ) curve of a zinc oxide nanorod field transistor, and FIG. 2B is a drain current-gate voltage (I d -V g ) curve.
도 1a를 참조하면, 실리콘 기판을 게이트로 이용하고 게이트 전압을 20V부터 -20V까지 10V 간격으로 측정한 결과이다. 여기서, Id-Vd 곡선은 선형적이므로 접촉저항이 매우 작은 오믹전극이 형성된 것이다. 또한 음의 방향으로 게이트 전압을 계속 증가시키면, 드레인 전류가 감소하는 n-type 금속-반도체 트랜지스터 특성을 갖는다.Referring to FIG. 1A, a silicon substrate is used as a gate and gate voltages are measured at 10V intervals from 20V to -20V. Here, since the I d -V d curve is linear, an ohmic electrode having a very small contact resistance is formed. In addition, as the gate voltage continues to increase in the negative direction, the drain current decreases, which leads to an n-type metal-semiconductor transistor.
도 1b를 참조하면, 드레인 전압을 0.2V에서 1.0V까지 0.2V 간격으로 측정한 것이다. 여기서, 게이트 전압을 양의 방향으로 증가시키면 드레인 전류는 증가하지만, 음의 방향으로 증가시키면 드레인 전류는 감소한다. 하지만, -20V 이상의 게이트 전압을 인가해도 드레인 전류가 완전히 차단(OFF)되지 않고 많은 양의 전류가 계속 흐른다. 예를 들어, 게이트 전압은 -20V이고 드레인 전압이 1.0V인 경우에 드레인 전류는 약 1.0ㅧ10-6A정도의 값을 갖는다. 이러한 드레인 전류는 소자의 성능을 크게 저하시키는 요인이 된다.Referring to FIG. 1B, drain voltages are measured at 0.2V intervals from 0.2V to 1.0V. Here, increasing the gate voltage in the positive direction increases the drain current, while increasing the negative voltage decreases the drain current. However, even when a gate voltage of -20V or more is applied, a large amount of current continues to flow without completely shutting off the drain current. For example, when the gate voltage is -20V and the drain voltage is 1.0V, the drain current has a value of about 1.0 10 -6 A. Such drain current is a factor that greatly degrades the performance of the device.
한편, 상기 드레인 전류는 나노막대의 표면에 형성된 결함과 가스등과 같은 불순물의 흡착으로 인해 나노소자의 전기적 특성을 떨어뜨리기 때문에 발생하는 것으로 알려져 있다. On the other hand, the drain current is known to occur because the deterioration of the electrical characteristics of the nano device due to the adsorption of impurities such as gas and defects formed on the surface of the nano-rod.
따라서, 본 발명이 이루고자 하는 기술적 과제는 표면에 형성된 결함과 가스등과 같은 불순물의 흡착을 방지하여 전기적 특성을 향상시킬 수 있는 반도체 나노막대를 제공하는 데 있다. Therefore, the technical problem to be achieved by the present invention is to provide a semiconductor nanorod that can improve the electrical properties by preventing the adsorption of impurities such as gas and defects formed on the surface.
상기 기술적 과제를 달성하기 위한 본 발명에 따른 반도체 나노막대는 유기물을 이용하여 표면처리된다.The semiconductor nanorod according to the present invention for achieving the above technical problem is surface treated using an organic material.
상기 유기물은 절연물일 수 있으며, 비저항은 0.001 ??cm 이상일 수 있다..The organic material may be an insulator, and the resistivity may be 0.001 ?? cm or more.
상기 유기물은 하이드로카본(hydrocarbon), 치환된 하이드로카본(substituted hydrocarbon), 카르보닐 컴파운드(carbonyl compound), 카르복시산 유도체(derivatives of carboxylic acids) 및 이들의 혼합물일 수 있다.The organic material may be a hydrocarbon, a substituted hydrocarbon, a carbonyl compound, derivatives of carboxylic acids, and mixtures thereof.
상기 유기물은 비닐(vinyl)계 폴리머와 그 유도체 폴리머, 비닐계가 아닌 폴리머와 그 유도체 폴리머일 수 있으며, 상기 비닐계가 아닌 폴리머는 폴리에테르(polyether)계, 폴리설파이드(polysulfide)계, 폴리카보네이트(polycarbonate)계, 폴리아미드(polyamide)계, 페놀-포름알데히드(phenol-formaldehyde)계, 폴리우레아(polyurea) 계, 폴리이미드(polyimide)계일 수 있다.The organic material may be a vinyl polymer and its derivative polymer, a non-vinyl polymer and its derivative polymer, and the non-vinyl polymer may be polyether, polysulfide, or polycarbonate. ), Polyamide (polyamide), phenol-formaldehyde (phenol-formaldehyde), polyurea (polyurea), polyimide (polyimide) may be.
상기 유기물은 상기 나노막대에 코팅하거나 유기물을 포함한 용액에 함침하여 형성할 수 있다. 상기 유기물은 1시간 내지 30시간 동안 함침하여 형성할 수 있고, 80℃~100℃에서 30분~1시간30분간 건조시키는 것이 바람직하다. The organic material may be formed by coating the nanorods or impregnating the solution including the organic material. The organic material may be formed by impregnation for 1 hour to 30 hours, and preferably dried for 30 minutes to 1 hour 30 minutes at 80 ℃ ~ 100 ℃.
상기 반도체 나노막대의 직경은 1 내지 500 nm이고 길이는 5 nm 내지 50 ??m이 바람직하다.The diameter of the semiconductor nanorod is preferably 1 to 500 nm and the length is 5 nm to 50 ~ m.
상기 나노막대는 ZnO, CdO, In2O3, MgO, Al2O3, AlN, InN, GaN, Si, AlP, InP, GaP, InAs, GaAs, AlAs, InSb, GaSb, ZnSe, ZnS, CdS, CdSe, BiSb 및 이들의 합금으로 이루어질 수 있다. 또한, 상기 반도체 나노막대는 Mg, Zn, Cd, Ti, Li, Cu, Al, Ni, Y, Ag, Mn, V, Fe, La, Ta, Nb, Ga, In, S, Se, P, As, Co, Cr, B, N, Sb 및 H로 이루어진 군중에서 선택된 적어도 하나 이상의 물질을 도핑될 수 있다.The nanorods are ZnO, CdO, In 2 O 3 , MgO, Al 2 O 3 , AlN, InN, GaN, Si, AlP, InP, GaP, InAs, GaAs, AlAs, InSb, GaSb, ZnSe, ZnS, CdS, It may be made of CdSe, BiSb and alloys thereof. In addition, the semiconductor nanorod is Mg, Zn, Cd, Ti, Li, Cu, Al, Ni, Y, Ag, Mn, V, Fe, La, Ta, Nb, Ga, In, S, Se, P, As At least one material selected from the group consisting of Co, Cr, B, N, Sb and H may be doped.
반도체 나노막대는 적어도 1층 이상으로 코팅된 다중벽 구조, 양자우물 혹은 초격자 구조, p-n 접합 구조, 이종접합 구조 및 동종접합 구조를 이룰 수 있다. 상기 반도체 나노막대는 전계트랜지스터, 쇼트키(Schottky)다이오드, p-n 접합 다이오드, 발광소자, 센서, 로직회로, 나노시스템, 집적회로 및 광소자에 이용될 수 있다.The semiconductor nanorods may have a multiwall structure, a quantum well or superlattice structure, a p-n junction structure, a heterojunction structure, and a homojunction structure coated with at least one layer. The semiconductor nanorods may be used in electric field transistors, Schottky diodes, p-n junction diodes, light emitting devices, sensors, logic circuits, nanosystems, integrated circuits, and optical devices.
이하 첨부된 도면을 참조하면서 본 발명의 바람직한 실시예를 상세히 설명한다. 다음에서 설명되는 실시예는 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 아래에서 상술되는 실시예에 한정되는 것은 아니다. 본 발명의 실시예들은 당분야에서 통상의 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위하여 제공되는 것이다. 본 발명의 실시예에서는 반도체 나노막대를 이용한 트랜지스터 및 다이오드를 중심으로 설명하기로 한다. 하지만, 반도체 나노막대는 본 발명의 실시예에 한정하는 것이 아니라 다양한 응용이 가능하다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments described below may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. Embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art. In the embodiment of the present invention, a description will be made of a transistor and a diode using a semiconductor nanorod. However, the semiconductor nanorods are not limited to the embodiment of the present invention and various applications are possible.
<제1 실시예><First Embodiment>
도 2a는 본 발명의 제1 실시예에 의한 전계트랜지스터의 사시도이고, 도 2b는 도 2a에 의한 전계트랜지스터의 평면도이다. FIG. 2A is a perspective view of the field transistor according to the first embodiment of the present invention, and FIG. 2B is a plan view of the field transistor according to FIG. 2A.
도 2a 및 도 2b를 참조하면, 200~500 ㎚정도의 게이트 절연막, 예컨대 실리콘 산화막(102)이 코팅된 실리콘 기판(100) 상에 반도체 나노막대(106)를 분산시킨다. 이때, 반도체 나노막대(106)는 비촉매 방식의 유기금속화학기상증착법을 이용하여 제조한 산화아연(ZnO) 나노막대(106)일 수 있다. 구체적으로, 반도체 나노막대(106)는 에탄올과 같은 유기용매에 혼합된 나노막대(106)를 실리콘 산화막(102)상에 분산시킨 후에 유기용매를 제거한다. 나노막대(106)는 본 발명의 제1 실시예에 의한 트랜지스터(110)의 채널층의 역할을 한다. 여기서, 나노막대(106)의 직경은 1 내지 500 nm이고 길이는 5 nm 내지 50 Ωm일 수 있다. 2A and 2B, the semiconductor nanorods 106 are dispersed on a silicon substrate 100 coated with a gate insulating layer, for example, a silicon oxide layer 102 of about 200 to 500 nm. In this case, the semiconductor nanorod 106 may be a zinc oxide (ZnO) nanorod 106 manufactured by using a non-catalytic organometallic chemical vapor deposition method. Specifically, the semiconductor nanorod 106 removes the organic solvent after dispersing the nanorod 106 mixed with an organic solvent such as ethanol on the silicon oxide film 102. The nanorod 106 serves as a channel layer of the transistor 110 according to the first embodiment of the present invention. Here, the diameter of the nanorod 106 may be 1 to 500 nm and the length may be 5 nm to 50 Ωm.
그 후, 전자현미경 및 원자탐침현미경을 이용하여 나노막대(106)의 정확한 위치를 구한다. 전자빔 식각법 및 금속증착공정을 이용해서 나노막대(106)의 양쪽 끝단에 Ti/Au 오믹콘택(104)을 형성시킨다. 접촉저항이 적은 오믹콘택(104)을 형성시키기 위해서 200℃ 내지 500℃에서 열처리를 더 수행할 수 있다. Thereafter, the exact position of the nanorod 106 is obtained using an electron microscope and an atomic probe microscope. Ti / Au ohmic contacts 104 are formed on both ends of the nanorods 106 using electron beam etching and metal deposition processes. In order to form the ohmic contact 104 having low contact resistance, heat treatment may be further performed at 200 ° C to 500 ° C.
본 발명의 제1 실시예에 의한 나노막대(106)는 ZnO이외에도 CdO, In2O3, MgO, Al2O3, AlN, InN, GaN, Si, AlP, InP, GaP, InAs, GaAs, AlAs, InSb, GaSb, ZnSe, ZnS, CdS, CdSe, BiSb 및 이들의 합금을 사용할 수 있다. 또한, 반도체 나노막대(106)는 Mg, Zn, Cd, Ti, Li, Cu, Al, Ni, Y, Ag, Mn, V, Fe, La, Ta, Nb, Ga, In, S, Se, P, As, Co, Cr, B, N, Sb 및 H로 이루어진 군중에서 선택된 적어도 하나 이상의 물질로 도핑하여 사용할 수 있다.The nanorod 106 according to the first embodiment of the present invention is not only ZnO but also CdO, In 2 O 3 , MgO, Al 2 O 3 , AlN, InN, GaN, Si, AlP, InP, GaP, InAs, GaAs, AlAs , InSb, GaSb, ZnSe, ZnS, CdS, CdSe, BiSb and alloys thereof can be used. In addition, the semiconductor nanorods 106 include Mg, Zn, Cd, Ti, Li, Cu, Al, Ni, Y, Ag, Mn, V, Fe, La, Ta, Nb, Ga, In, S, Se, P Doped with at least one material selected from the group consisting of As, Co, Cr, B, N, Sb and H.
이때, 나노막대(106)는 유기물인 PEG(polyethyleneglicohol)로 표면을 개질하였다. 구체적으로, 나노막대(106)를 채용한 트랜지스터(110)의 전기적 특성을 측정한 다음, 트랜지스터(110)를 PEG 용액 속에 1시간 내지 30시간 정도 담가놓았다. 바람직하게는 3시간 내지 5시간 동안 담가둔다. 그후 탈이온수에 의해 나노막대(106)와 이를 포함하는 트랜지스터(110)를 세정하였다. At this time, the nanorod 106 was modified surface with polyethylene (polyethyleneglicohol) (organic material). Specifically, after measuring the electrical characteristics of the transistor 110 employing the nanorod 106, the transistor 110 was immersed in PEG solution for 1 to 30 hours. Preferably soak for 3 to 5 hours. Thereafter, the nanorod 106 and the transistor 110 including the same were cleaned by deionized water.
도 3a는 PEG에 의해 표면처리된 산화아연 나노막대 전계트랜지스터의 드레인 전류-드레인 전압(Id-Vd) 곡선이고, 도 3b는 드레인 전류-게이트 전압(Id -Vg) 곡선이다.FIG. 3A is a drain current-drain voltage (I d -V d ) curve of a zinc oxide nanorod field transistor surface-treated with PEG, and FIG. 3B is a drain current-gate voltage (I d -V g ) curve.
도 3a를 참조하면, 실리콘 기판(100)을 게이트로 이용하고, 게이트 전압은 20V부터 -20V까지 10V 간격으로 측정하였다. 이때, 게이트 전압에 따른 드레인 전류는 표면처리하지 않은 도 2a의 전류에 비해 급격하게 변화하였다. 특히, -20V의 게이트 전압을 인가한 경우 드레인 전류가 완전히 차단되어 흐르지 않는다. Referring to FIG. 3A, using the silicon substrate 100 as a gate, the gate voltage was measured at 10V intervals from 20V to -20V. At this time, the drain current according to the gate voltage was changed drastically compared to the current of FIG. In particular, when a gate voltage of -20V is applied, the drain current is not completely blocked.
도 3b를 참조하면, 드레인 전압을 0.2V에서 1V까지 0.2V 간격으로 측정한 결과이다. 도시된 바와 같이, 드레인 전압의 변화에 대한 드레인 전류의 변화, 예컨대 상호컨덕턴스, 전하이동도 등과 같은 트랜지스터의 전기적 특성이 크게 향상되었다. Referring to FIG. 3B, the drain voltage is measured at 0.2V intervals from 0.2V to 1V. As shown, the electrical characteristics of the transistor, such as changes in drain current with respect to changes in drain voltage, such as interconductance, charge mobility, etc., have been greatly improved.
<제2 실시예>Second Embodiment
도 2a 및 도 2b를 참조하여 설명한 제1 실시예와 동일한 방법으로 트랜지스터를 제조하였다. 이어서, 나노막대(106)를 채용한 트랜지스터(110)의 전기적 특성을 측정한 다음, 트랜지스터(110)를 폴리이미드(polyimide)로 1000~6000 rpm으로 30~60초 동안 스핀코팅(spin coating)하였다. 그후, 오븐에서 약 80?? 정도에서 10 분 내지 1시간 정도 건조하였다. The transistor was manufactured in the same manner as in the first embodiment described with reference to FIGS. 2A and 2B. Subsequently, the electrical characteristics of the transistor 110 employing the nanorod 106 were measured, and then the transistor 110 was spin coated with polyimide for 30 to 60 seconds at 1000 to 6000 rpm. . After that, about 80 ?? Dry at about 10 minutes to 1 hour.
도 4는 본 발명의 제2 실시예에 의한 트랜지스터(110)에 대해 폴리이미드로 코팅하기 전후에 측정한 드레인 전류-게이트 전압(Id-Vg) 곡선이다. 폴리이미드로 코팅한 경우는 실선, 코팅하지 않은 경우는 일점쇄선으로 표시하였다. 즉, 드레인 전압은 1V로 일정하게 고정하고 게이트 전압을 -20V에서 20V로 변화시키면서 드레인 전류를 측정하였다. 폴리이미드로 코팅을 하면, 게이트 전압에 대한 드레인 전류는 급격히 증가하였다. 이에 따라, 상호컨덕턴스 및 전하이동도는 크게 증가하였고 또한 턴온(turn on) 전압도 -5V로 감소하였다.4 is a drain current-gate voltage (I d -V g ) curve measured before and after coating with polyimide for the transistor 110 according to the second embodiment of the present invention. In the case of coating with polyimide, solid lines are indicated, and in the case of non-coating, a single dashed line is indicated. In other words, the drain voltage was fixed at 1V and the drain current was measured while changing the gate voltage from -20V to 20V. When coated with polyimide, the drain current against the gate voltage increased dramatically. As a result, the interconductance and charge mobility were greatly increased, and the turn on voltage was also reduced to -5V.
<제3 실시예>Third Embodiment
도 2a 및 도 2b를 참조하여 설명한 제1 실시예와 동일한 방법으로 트랜지스터를 제조하였다. 이어서, 나노막대(106)를 채용한 트랜지스터(110)의 전기적 특성을 측정한 다음, 트랜지스터(110)를 고순도 트윈(Tween) 20(sigma aldrich사 제조)용액 속에 1시간 내지 30시간 정도 담가놓았다. 여기서, 트윈 20의 주성분은 폴리에틸렌글리콘 소비탄 모노라우레이트(polyethylene glycol sorbitan monolaurate)이다. 바람직하게는 3시간 내지 5시간 동안 담가둔다. 그후 탈이온수에 의해 나노막대(106)와 이를 포함하는 트랜지스터(110)를 세정하였다. The transistor was manufactured in the same manner as in the first embodiment described with reference to FIGS. 2A and 2B. Subsequently, the electrical characteristics of the transistor 110 employing the nanorod 106 were measured, and the transistor 110 was immersed in a high purity Tween 20 (manufactured by Sigma Aldrich) solution for about 1 hour to 30 hours. Here, the main component of Tween 20 is polyethylene glycol sorbitan monolaurate. Preferably soak for 3 to 5 hours. Thereafter, the nanorod 106 and the transistor 110 including the same were cleaned by deionized water.
도 5는 본 발명의 제3 실시예에 의한 트랜지스터(110)에 대해 트윈 20으로 코팅하기 전후에 측정한 드레인 전류-게이트 전압(Id-Vg) 곡선이다. 트윈 20으로 코팅한 경우는 이점쇄선 그리고 코팅하지 않은 경우는 일점쇄선으로 표시하였다. 즉, 드레인 전압은 1V로 일정하게 고정하고 게이트 전압을 -20V에서 20V로 변화시키면서 드레인 전류를 측정하였다. 트윈 20을 코팅하면, 게이트 전압에 대한 드레인 전류는 급격히 증가하였다. 이에 따라, 상호컨덕턴스 및 캐리어 이동도는 크게 증가하였고 또한 턴온(turn on) 전압도 -5 V로 감소하였다.5 is a drain current-gate voltage (I d -V g ) curve measured before and after coating with a tween 20 for the transistor 110 according to the third embodiment of the present invention. In case of coating with Tween 20, the double-dotted line is indicated. In other words, the drain voltage was fixed at 1V and the drain current was measured while changing the gate voltage from -20V to 20V. Coating tween 20 drastically increased the drain current against the gate voltage. As a result, the interconductance and carrier mobility were greatly increased and the turn on voltage was also reduced to -5V.
본 발명의 제1 실시예, 제2 실시예 및 제3 실시예에 사용되는 유기물은 절연물로써 비저항은 0.001 Ωcm 이상일 수 있다. 예를 들면, 알칸(alkane), 알켄(alkene), 알킨(alkyne), 벤젠(benzene) 등과 같은 하이드로카본(hydrocarbon)계와, 알킬할라이드(alkyl halide), 비닐할라이드(vinyl halide), 알콜(alcohol), 티올(thiol), 아민(amine), 에테르(ether), 설파이드(sulfide) 등과 같은 치환된 하이드로카본(substituted hydrocarbon)계와, 알데히드(aldehyde), 케톤(ketone), 카르복시산(carboxylic acid) 등과 같은 카르보닐 컴파운드(carbonyl compound), 에스테르(ester), 아미드(amide), 산클로라이드(acid chloride) 등과 같은 카르복시산 유도체 및 이들의 혼합물일 수 있다.The organic material used in the first, second and third embodiments of the present invention is an insulator and may have a resistivity of at least 0.001 Ωcm. For example, hydrocarbons such as alkanes, alkenes, alkynes, benzenes, alkyl halides, vinyl halides, alcohols ) Substituted hydrocarbons such as thiol, amine, ether, sulfide, aldehyde, ketone, carboxylic acid, etc. Carboxylic acid derivatives such as carbonyl compounds, esters, amides, acid chlorides, and the like, and mixtures thereof.
또한, 상기 유기물은 절연물로써 폴리비닐클로라이드(polyvinyl chloride), 폴리에틸렌(polyethelene), 폴리스티렌(polystyrene), 폴리아크릴로나이트라이드(polyacrylonitride), 폴리아크릴아미드(polyacrylamide) 등과 같은 비닐(vinyl)계 폴리머와 그 유도체 폴리머, 폴리에테르(Polyether)계, 폴리설파이드(polysulfide)계, 폴리카보네이트(polycarbonate)계, 폴리아미드(polyamide)계, 페놀-포름알데히드(phenol-formaldehyde)계, 폴리우레아(polyurea)계, 폴리이미드(polyimide)계 등과 같은 비닐(vinyl)계가 아닌 폴리머와 그 유도체 폴리머일 수 있다. 나아가, 상기 유기물은 비전도성이며 유전율이 큰 물질을 사용할 수 있다. In addition, the organic material is a vinyl-based polymer such as polyvinyl chloride, polyethylene, polystyrene, polystyrene, polyacrylonitride, polyacrylamide, and the like as an insulator. Derivative polymer, polyether, polysulfide, polycarbonate, polyamide, phenol-formaldehyde, polyurea, poly The polymer may be a non-vinyl polymer such as a polyimide system and the derivative polymer thereof. In addition, the organic material may be a non-conductive material having a high dielectric constant.
<제4 실시예>Fourth Example
도 6은 본 발명의 제4 실시예에 의한 반도체 나노막대를 이용한 쇼트키(schottky)다이오드를 PEG로 코팅하기 전후에 측정한 드레인 전류-게이트 전압(Id-Vg) 곡선이다. 여기서, 역방향 드레인 전류는 절대값으로 변환하여 표시하였다. PEG로 코팅한 경우는 점선선, 코팅하지 않은 경우는 일점쇄선으로 표시하였다. 제4 실시예에 의한 나노막대 쇼트키 다이오드는 일함수가 큰 Au를 쇼트키 전극으로 하였으며, Ti/Au 을 오믹전극으로 제조하였다. 도 5에 도시된 바와 같이, PEG로 코팅한 나노막대 쇼트키 다이오드는 한쪽 방향으로만 전류가 잘 흐르는 뚜렷한 정류특성을 보인다. PEG를 코팅하지 않는 다이오드는 역방향 전압 하에서 누설전류가 커진다. 이에 따라, 정방향과 역방향 전압 하에서 전류의 비가 대략 102-103으로 나타난다. 이에 반해, PEG를 코팅한 경우 역방향 전압 하에서 누설전류가 매우 약하게 나타나며 정방향과 역방향 전압 하에서 전류의 비가 대략 104-107로 크게 증가하였다.6 is a drain current-gate voltage (I d -V g ) curve measured before and after coating a schottky diode using a semiconductor nanorod according to a fourth embodiment of the present invention with PEG. Here, the reverse drain current is converted into an absolute value and displayed. When coated with PEG, it is indicated by a dashed line, and when not coated by a dotted line. In the nanorod Schottky diode according to the fourth embodiment, Au having a large work function was used as a Schottky electrode, and Ti / Au was manufactured as an ohmic electrode. As shown in FIG. 5, the PEG-coated nanorod Schottky diode exhibits a distinct rectification characteristic in which current flows well in only one direction. Diodes that do not coat PEG increase leakage current under reverse voltage. Accordingly, the ratio of the currents under the forward and reverse voltages is approximately 10 2 -10 3 . On the contrary, when PEG was coated, the leakage current was very weak under the reverse voltage, and the ratio of the current under the forward and reverse voltage was increased to about 10 4 -10 7 .
PEG를 코팅한 경우 이외에 폴리이미드나 트윈 20을 적용한 경우에도 이와 동일한 결과를 얻을 수 있다. The same result can be obtained when polyimide or Tween 20 is applied in addition to PEG coating.
본 발명의 실시예들에서는 유기물을 이용하여 표면을 개질시킨 반도체 나노막대를 채널층으로 하여 전기적인 성능이 우수한 나노소자, 예를 들어 전자미세소자를 제조할 수 있다. In the embodiments of the present invention, a nano device, for example, an electronic micro device having excellent electrical performance may be manufactured using a semiconductor nanorod having a surface modified with an organic material as a channel layer.
또한 유기물을 이용한 표면 개질 처리기술에 의해 전기전도도를 제어하는 기술을 응용하여 특정한 나노막대(106) 혹은 나노막대(106) 내의 특정부위만 선택적 개질시킴으로써 나노막대(106)를 이용한 로직회로 및 고집적 나노시스템 개발에 응용될 수 있다. In addition, by applying a technique to control the electrical conductivity by the surface modification treatment technology using the organic material, by selectively modifying only a specific portion of the specific nanorod 106 or the nanorod 106, logic circuits using the nanorod 106 and highly integrated nano It can be applied to system development.
이상, 본 발명은 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되지 않으며, 본 발명의 기술적 사상의 범위 내에서 당분야에서 통상의 지식을 가진 자에 의하여 여러 가지 변형이 가능하다. 예를 들어, 반도체 나노막대는 적어도 1층으로 코팅된 다중벽 구조, 양자우물 혹은 초격자 구조, p-n 접합 구조, 이종접합 구조 및 동종접합 구조를 가질 수 있다. 또한, 반도체 나노막대는 쇼트키(Schottky)다이오드, 발광소자, 센서, 광소자, 로직회로, 나노시스템 및 집적회로 등을 포함한 전자미세소자에 이용될 수 있다. As mentioned above, although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. It is possible. For example, the semiconductor nanorods may have a multiwall structure, a quantum well or superlattice structure, a p-n junction structure, a heterojunction structure, and a homojunction structure coated with at least one layer. In addition, the semiconductor nanorods may be used in electronic microdevices including Schottky diodes, light emitting devices, sensors, optical devices, logic circuits, nanosystems and integrated circuits.
상술한 본 발명에 따른 이미지 센서 및 그 제조방법에 의하면, 표면에 형성된 결함과 가스등과 같은 불순물의 흡착을 방지하여 전기적 특성을 향상시킬 수 있다. According to the image sensor and the manufacturing method according to the present invention described above, the electrical characteristics can be improved by preventing the adsorption of impurities such as gas and defects formed on the surface.
또한, 나노막대를 유기물로 코팅하면 트랜지스터의 상호컨덕턴스와 전하이동도가 크게 향상되었으며, 턴온전압이 크게 감소하였다. In addition, coating the nanorods with an organic material greatly improved the transconductance and charge mobility of the transistor, and greatly reduced the turn-on voltage.
나아가. 유기물을 코팅한 나노막대를 이용한 쇼트키 다이오드의 경우, 역방향 전압 하의 누설전류(reverse bias leakage current)가 크게 감소하는 것으로 나타났다. Furthermore. For Schottky diodes using organic nanorods, reverse bias leakage currents have been significantly reduced.
그리고, 유기물을 이용한 표면 개질 처리기술에 의해 전기전도도를 제어하는 기술을 응용하여 특정한 나노막대 혹은 나노막대 내의 특정부위만 선택적 개질시킴으로써 나노막대를 이용한 로직회로 및 고집적 나노시스템 개발에 응용될 수 있다. In addition, by applying a technique of controlling the electrical conductivity by the surface modification treatment technology using organic materials, it can be applied to the development of logic circuits and highly integrated nanosystems using nanorods by selectively modifying only a specific nanorod or a specific portion within the nanorod.
도 1a는 산화아연 나노막대 전계트랜지스터의 드레인 전류-드레인 전압 (Id-Vd) 곡선이고, 도 2b는 산화아연 나노막대 전계트랜지스터의 드레인 전류-게이트 전압 (Id-Vg) 곡선이다.FIG. 1A is a drain current-drain voltage (I d -V d ) curve of a zinc oxide nanorod field transistor, and FIG. 2B is a drain current-gate voltage (I d -V g ) curve of a zinc oxide nanorod field transistor.
도 2a는 본 발명의 제1 실시예에 의한 전계트랜지스터의 사시도이고, 도 2b는 도 2a에 의한 전계트랜지스터의 평면도이다.FIG. 2A is a perspective view of the field transistor according to the first embodiment of the present invention, and FIG. 2B is a plan view of the field transistor according to FIG. 2A.
도 3a는 PEG에 의해 표면처리된 산화아연 나노막대 전계트랜지스터의 드레인 전류-드레인 전압 (Id-Vd) 곡선이고, 도 3b는 드레인 전류-게이트 전압 (Id -Vg) 곡선이다.FIG. 3A is a drain current-drain voltage (I d -V d ) curve of a zinc oxide nanorod field transistor surface-treated with PEG, and FIG. 3B is a drain current-gate voltage (I d -V g ) curve.
도 4는 본 발명의 제2 실시예에 의한 트랜지스터에 대해 폴리이미드로 코팅하기 전후에 측정한 드레인 전류-게이트 전압(Id-Vg)곡선이다.4 is a drain current-gate voltage (I d -V g ) curve measured before and after coating with a polyimide for the transistor according to the second embodiment of the present invention.
도 5는 본 발명의 제3 실시예에 의한 트랜지스터에 대해 Tween 20으로 코팅하기 전후에 측정한 드레인 전류-게이트 전압(Id-Vg) 곡선이다.5 is a drain current-gate voltage (I d -V g ) curve measured before and after coating with Tween 20 for the transistor according to the third embodiment of the present invention.
도 6은 본 발명의 제4 실시예에 의한 반도체 나노막대를 이용한 쇼트키(schottky)다이오드를 PEG로 코팅하기 전후에 측정한 드레인 전류-게이트 전압(Id-Vg) 곡선이다.6 is a drain current-gate voltage (I d -V g ) curve measured before and after coating a schottky diode using a semiconductor nanorod according to a fourth embodiment of the present invention with PEG.
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