KR20050120296A - Method for forming gate of semiconductor device - Google Patents
Method for forming gate of semiconductor device Download PDFInfo
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- KR20050120296A KR20050120296A KR1020040045591A KR20040045591A KR20050120296A KR 20050120296 A KR20050120296 A KR 20050120296A KR 1020040045591 A KR1020040045591 A KR 1020040045591A KR 20040045591 A KR20040045591 A KR 20040045591A KR 20050120296 A KR20050120296 A KR 20050120296A
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- gate
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- gate polysilicon
- polysilicon film
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 36
- 229920005591 polysilicon Polymers 0.000 claims abstract description 36
- 238000005530 etching Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 5
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 5
- 239000010703 silicon Substances 0.000 claims abstract description 5
- 230000001052 transient effect Effects 0.000 claims abstract description 3
- 235000012431 wafers Nutrition 0.000 abstract description 3
- 238000001514 detection method Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Drying Of Semiconductors (AREA)
Abstract
본 발명은 웨이퍼들간 게이트 임계치수 변동(gate CD variation)이 유발되는 것을 방지할 수 있는 반도체 소자의 게이트 형성방법을 개시한다. 개시된 본 발명의 게이트 형성방법은, 실리콘 기판 상에 게이트 산화막, 게이트 폴리실리콘막, 반사방지막 및 게이트 형성 영역을 한정하는 감광막 패턴을 차례로 형성하는 단계와, 상기 감광막 패턴을 이용해서 반사방지막을 식각하는 단계와, 상기 게이트 폴리실리콘막을 간섭계를 이용하여 잔류 두께를 모니터링하면서 임의의 두께가 잔류되도록 메인 식각하는 단계와, 상기 메인 식각된 게이트 폴리실리콘막의 잔류 두께를 설정된 EPD 시간 동안 랜딩 식각하여 제거하는 단계와, 상기 기판 결과물에 대해 게이트 폴리실리콘막 잔류물이 제거되도록 과도 식각을 수행하는 단계를 포함하는 것을 특징으로 한다. The present invention discloses a method for forming a gate of a semiconductor device capable of preventing a gate CD variation between wafers from occurring. According to the disclosed method of forming a gate, a method of sequentially forming a photoresist pattern defining a gate oxide film, a gate polysilicon film, an antireflection film, and a gate formation region on a silicon substrate, and etching the antireflection film using the photoresist pattern And main etching the gate polysilicon film using an interferometer to monitor the remaining thickness to maintain any thickness, and removing the residual thickness of the main etched gate polysilicon film by landing etching for a set EPD time. And performing a transient etching to remove the gate polysilicon film residue on the substrate resultant.
Description
본 발명은 반도체 소자의 게이트 형성방법에 관한 것으로, 보다 상세하게는, 웨이퍼들간 게이트 임계치수 변동(CD variation)이 유발되는 것을 방지할 수 있는 반도체 소자의 게이트 형성방법에 관한 것이다.The present invention relates to a method of forming a gate of a semiconductor device, and more particularly, to a method of forming a gate of a semiconductor device capable of preventing the gate CD variation between wafers from occurring.
반도체 기술의 진보와 더불어, 반도체 소자의 고속화, 고집적화가 급속하게 진행되고 있고, 이에 수반해서, 패턴의 미세화 및 패턴 치수의 고정밀화에 대한 요구가 점점 높아지고 있다. 따라서, 소자의 임계치수 변동을 방지할 수 있는 기술에 대한 필요성이 대두되고 있다.With the advance of semiconductor technology, the speed and the high integration of a semiconductor element are progressing rapidly, and with this, the demand for refinement | miniaturization of a pattern and high precision of a pattern dimension is increasing. Accordingly, there is a need for a technique capable of preventing the variation of the critical dimension of the device.
예컨대, 통상의 게이트 형성공정시 게이트 폴리실리콘막 메인식각을 시간을 조절하여 진행하며, 메인식각 후 종점검출(EPD, end point detection)시간을 조절하여 폴리실리콘막을 식각하는데, 이때, 식각속도의 변동으로 인해 잔류한 폴리실리콘막의 두께차이가 발생하여 임계치수 변동이 발생한다.For example, in the conventional gate forming process, the gate polysilicon film main etching is performed by adjusting the time, and after the main etching, the polysilicon film is etched by adjusting the end point detection (EPD) time. As a result, a thickness difference of the remaining polysilicon film occurs and a critical dimension variation occurs.
종래기술에 따른 반도체 소자의 게이트 형성방법은, 실리콘 기판 상에 게이트 산화막, 폴리실리콘막, 반사방지막을 차례로 형성한 후 상기 반사방지막 상에 감광막 도포, 노광, 현상공정을 통하여 게이트 형성 영역을 한정하는 감광막 패턴을 형성한다. 그런 다음, 상기 감광막 패턴을 식각장벽으로 이용하여 반사방지막을 식각한다. 이어서, 시간을 조절하여 폴리실리콘막을 소정두께를 남기고 메인식각한 다음, 종점검출(End Point Detection ; 이하,EPD)시간을 조절하여 랜딩 식각한다. 이후, 상기 기판 결과물을 과도 식각하여 잔류한 폴리실리콘막을 제거하여 게이트를 완성한다.The gate forming method of a semiconductor device according to the prior art is formed by sequentially forming a gate oxide film, a polysilicon film, an antireflection film on a silicon substrate, and then limiting the gate formation region through a photoresist coating, exposure, and development process on the antireflection film. A photosensitive film pattern is formed. Then, the anti-reflection film is etched using the photoresist pattern as an etch barrier. Subsequently, the polysilicon film is main-etched with a predetermined thickness by adjusting the time, and then landing etching is performed by adjusting End Point Detection (EPD) time. Thereafter, the substrate is excessively etched to remove the remaining polysilicon film to complete the gate.
그러나, 상기 폴리실리콘막의 메인식각을 시간으로 조절하여 잔류한 폴리실리콘막의 두께가 일정치 않으며, 메인식각 후 랜딩 식각시 웨이퍼간의 EPD 시간의 변동이 발생하여 임계치수 변동이 발생하게 된다.However, the thickness of the polysilicon film remaining by adjusting the main etching of the polysilicon film with time is not constant, and the variation of the EPD time between the wafers occurs during landing etching after the main etching, thereby causing a change in the critical dimension.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, 간섭계를 이용하여 폴리실리콘막을 일정한 두께를 남기고 식각함으로써 임계치수 변동의 발생을 방지할 수 있는 반도체 소자의 게이트 형성방법에 관한 것이다.Accordingly, the present invention has been made to solve the above problems, and relates to a method of forming a gate of a semiconductor device that can prevent the occurrence of the critical dimension variation by etching the polysilicon film leaving a certain thickness using an interferometer.
상기와 같은 목적을 달성하기 위하여, 본 발명은, 실리콘 기판 상에 게이트 산화막, 게이트 폴리실리콘막, 반사방지막 및 게이트 형성 영역을 한정하는 감광막 패턴을 차례로 형성하는 단계; 상기 감광막 패턴을 이용해서 반사방지막을 식각하는 단계; 상기 게이트 폴리실리콘막을 간섭계를 이용하여 잔류 두께를 모니터링하면서 임의의 두께가 잔류되도록 메인 식각하는 단계; 상기 메인 식각된 게이트 폴리실리콘막의 잔류 두께를 설정된 EPD 시간 동안 랜딩 식각하여 제거하는 단계; 및 상기 기판 결과물에 대해 게이트 폴리실리콘막 잔류물이 제거되도록 과도 식각을 수행하는 단계를 포함하는 반도체 소자의 게이트 형성방법을 제공한다. In order to achieve the above object, the present invention comprises the steps of sequentially forming a photoresist pattern defining a gate oxide film, a gate polysilicon film, an antireflection film and a gate formation region on a silicon substrate; Etching the anti-reflection film using the photoresist pattern; Main etching the gate polysilicon layer using an interferometer to monitor the remaining thickness so that any thickness remains; Removing the remaining thickness of the main etched gate polysilicon layer by landing etching for a set EPD time; And performing a transient etching to remove the gate polysilicon film residue on the substrate resultant.
여기서, 상기 게이트 폴리실리콘막의 메인 식각은 바람직하게 500Å이 잔류되도록 수행한다. Here, the main etching of the gate polysilicon film is preferably performed such that 500 kV remains.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 게이트 형성방법을 설명하기 위한 도면이다.1A to 1D are diagrams for describing a gate forming method of a semiconductor device according to an exemplary embodiment of the present invention.
도 1a를 참조하면, 실리콘 기판(11)상에 게이트 산화막(12), 게이트 폴리실리콘막(13), 반사방지막(14)을 차례로 형성한 후 감광막 도포, 노광, 현상공정을 통하여 게이트 형성 영역을 한정하는 감광막 패턴(15)을 형성한다. 상기 게이트 산화막(12)은 기판을 산화시켜 10∼20Å의 두께로 형성하고, 상기 게이트 폴리실리콘막(13)은 게이트 산화막(12) 상에 1500∼2000Å의 두께로 증착한다.Referring to FIG. 1A, a gate oxide film 12, a gate polysilicon film 13, and an antireflection film 14 are sequentially formed on a silicon substrate 11, and then a gate formation region is formed through a photoresist coating, exposure, and development process. The photosensitive film pattern 15 to be defined is formed. The gate oxide film 12 is oxidized to form a thickness of 10 to 20 GPa, and the gate polysilicon film 13 is deposited on the gate oxide film 12 to a thickness of 1500 to 2000 GPa.
도 2b를 참조하면, 상기 감광막 패턴(15)을 식각장벽으로 이용하여 플라즈마를 이용한 건식식각으로 반사방지막(14)을 식각한다. 상기 플라즈마는 HBr, O2, CH4 가스를 일정한 비율로 혼합한 기체를 활성화시켜 사용한다. 그런 다음, 반사방지막(14) 식각시 O2 가스에 의해 발생하는 폴리실리콘막(13) 위의 네이티브(native) 산화막을 제거하기 위하여 브레이크 쓰루(break through)를 실시한다.Referring to FIG. 2B, the anti-reflection film 14 is etched by dry etching using plasma using the photoresist pattern 15 as an etch barrier. The plasma is used by activating a gas mixed with HBr, O2, CH4 gas at a constant ratio. Then, a break through is performed to remove the native oxide film on the polysilicon film 13 generated by the O 2 gas when the antireflection film 14 is etched.
도 2c를 참조하면, 상기 게이트 폴리실리콘막(13)을 500Å의 두께를 남기고 메인식각한다. 이때, 간섭계를 이용하여 남아있는 게이트 폴리실리콘막(13)의 두께를 모니터링하면서 식각공정을 진행한다.Referring to FIG. 2C, the gate polysilicon layer 13 is main etched with a thickness of 500 μm. At this time, the etching process is performed while monitoring the thickness of the remaining gate polysilicon film 13 using an interferometer.
도 1d를 참조하면, 상기 메인식각된 게이트 폴리실리콘막(13)을 랜딩 식각하기 위해 모노크로미터(monochrometer)를 이용하여 식각종점검출(End Point Detection ; 이하, EPD) 시간을 검출하고, 검출된 EPD 시간으로 랜딩 식각을 실시하여 상기 메인 식각된 게이트 폴리실리콘막(13)의 잔류두께를 제거한다. 이후, 상기 기판 결과물에 대해 게이트 폴리실리콘막(13) 잔류물이 제거되도록 과도 식각을 실시한다.Referring to FIG. 1D, an end point detection (EPD) time is detected by using a monochrometer to landing etch the main etched gate polysilicon layer 13, Landing etching is performed in EPD time to remove the remaining thickness of the main etched gate polysilicon layer 13. Thereafter, overetch is performed to remove the gate polysilicon layer 13 residue from the substrate resultant.
여기서, 게이트 폴리실리콘막(13) 메인 식각시 간섭계를 이용하여 잔류 게이트 폴리실리콘막(13) 두께가 일정하도록 모니터링함으로써 임계치수 변동의 발생을 방지할 수 있다.Here, by monitoring the thickness of the remaining gate polysilicon layer 13 to be constant by using an interferometer during the main etching of the gate polysilicon layer 13, it is possible to prevent the occurrence of the threshold dimension variation.
이상에서와 같이, 본 발명은 게이트를 형성함에 있어서. 간섭계를 이용하여 일정한 두께의 잔류한 폴리실리콘막을 얻고, 일정한 EPD 시간으로 폴리실리콘막을 식각함으로써, 임계치수 변동의 발생을 방지하여 안정성 있는 반도체 소자를 얻을 수 있다.As described above, the present invention in forming a gate. By using the interferometer to obtain the remaining polysilicon film of a constant thickness and etching the polysilicon film with a constant EPD time, it is possible to prevent the occurrence of the critical dimension fluctuation and to obtain a stable semiconductor device.
이상, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.As mentioned above, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 게이트 형성방법을 설명하기 위한 도면. 1A to 1D illustrate a method of forming a gate of a semiconductor device in accordance with an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
11 : 반도체 기판 12 : 게이트 산화막11 semiconductor substrate 12 gate oxide film
13 : 게이트 폴리실리콘막 14 : 반사방지막13 gate polysilicon film 14 antireflection film
15 : 감광막 패턴 20 : 간섭계15 photosensitive film pattern 20 interferometer
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100720473B1 (en) * | 2005-12-30 | 2007-05-22 | 동부일렉트로닉스 주식회사 | Method for manufacturing semiconductor transistor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100720473B1 (en) * | 2005-12-30 | 2007-05-22 | 동부일렉트로닉스 주식회사 | Method for manufacturing semiconductor transistor |
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