KR20050118905A - Program test device of fuse circuit - Google Patents

Abstract

The present invention relates to a fuse circuit used in a semiconductor memory device, and more particularly, to a program test apparatus of a fuse circuit for automatically performing a program test by monitoring the programming time of the unit fuse cell during the program test of the fuse circuit.

The fuse circuit program test apparatus of the present invention compares a fuse circuit electrically programmable by a fuse current with first means for detecting the fuse current flowing through the fuse circuit, and compares the fuse current with a predetermined reference current. And second means for sensing whether the fuse circuit has completed the program test and third means for terminating the program operation of the fuse circuit in response to a program completion signal from the second means.

Description

Fuse Circuit Program Test Device {PROGRAM TEST DEVICE OF FUSE CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fuse circuit used in a semiconductor memory device, and more particularly, to automatically perform a program test by monitoring a programming time of a unit fuse cell during a program test of a fuse circuit. Program test apparatus for a fuse circuit.

In general, fuse circuits are used for various purposes in semiconductor memory devices. For example, fuse circuits are used to implement memory redundancy for repairing a chip ID of a memory or repairing a fail bit generated in a memory manufacturing process. That is, fuse circuits are used to replace defective bit cells with redundancy cells in a memory manufacturing process.

Such fuse circuits include a laser fuse circuit using a laser and an E-Fuse circuit using characteristics of a resistor according to voltage application. Among these, the e-fuse circuit is an electrically programmable fuse circuit, and does not require any equipment for mode switching or repair, and the algorithm for implementation thereof is simpler than the laser fuse circuit. There is an advantage. In addition, the e-fuse circuit can perform a mode change or repair at the same time as the test, and has the advantage that it can be used at the package level (package level) is the most popular fuse circuit.

1 is a circuit diagram showing an embodiment of a conventional fuse circuit that is generally used. The fuse circuit 100 of FIG. 1 is U.S. Patent Publication No. 2001-0090149 (published: October 18, 2001) and entitled "FUSE CIRCUIT AND PROGRAM STATUS DETECTING METHOD THEREOF." Pat. No. 6,498,526.

The conventional fuse circuit 100 shown in FIG. 1 includes a first fuse resistor element 102 and a second fuse resistor element 104, and a plurality of PMOS transistors 106 and 108 and NMOS transistors 110, 112, and 114. 116, 120). As shown in FIG. 1, the PMOS transistors 106 and 108 and some NMOS transistors 110 and 112 constitute a complementary latch circuit 122.

On the other hand, the first fuse resistance element 102 is designed to have a value smaller than the resistance value of the second fuse resistance element 104 in the state where no current flows. In addition, when the resistance value gradually increases and the current flows for a predetermined amount or more, the first fuse resistance element 102 is cut according to the amount of current flowing.

The fuse circuit 100 of FIG. 1 is a circuit that outputs state information on whether the first fuse resistor element 102 is cut and programmed or not programmed. In more detail, when an external program signal, that is, a high level fuse cutting signal EN_cut, is applied, the NMOS transistor 120 connected to the node between the first fuse resistor element 102 and the complementary latch circuit 122 is applied. It is turned on, so that current flows through the first fuse resistor element 102. When a current flows through the first fuse resistor element 102, the resistance value of the first fuse resistor element 102 is increased to be larger than the resistance value of the second fuse resistor element 104, and the current is higher than a predetermined amount (10mA). Flows, the first fuse resistance element 102 is cut. In this case, when a high level read command (Read) is applied to the fuse circuit 100, the NMOS transistors 114 and 116 are turned on. As a result, according to the current sensing operation of the PMOS 106, 108 and the NMOS transistors 110, 112 constituting the complementary latch circuit 122, the first fuse resistor element 102 and the second fuse resistor element 104 The voltage difference due to the resistance difference of the n) occurs between the nodes ND10 and ND20. On the other hand, since the resistance value of the first fuse resistance element 102 is larger than the resistance value of the second fuse resistance element 104, the voltage of the node ND20 becomes higher than the voltage of the node ND10. After that, when the read command Read is transitioned from the high level to the low level, the voltages of the nodes previously set become the ground voltage and the power supply voltage V _EXT by the complementary latch circuit 122, respectively. That is, since the voltage at node ND10 is relatively lower than the voltage at node ND20, PMOS transistor 106 and NMOS transistor 112 are turned off, while PMOS transistor 108 and NMOS transistor 110 are turned on. Accordingly, the voltage of the node ND20 becomes the power supply voltage (high level) through the second fuse resistor element 104 and the PMOS transistor 108, and the voltage of the node ND10 is grounded (low level) through the NMOS transistor 110. Becomes As a result, the high level voltage of the node ND20 passes through the inverter 118 (Inverter) and the output of the fuse circuit 100 becomes a low level. This means that the fuse circuit is normally programmed.

However, such a conventional fuse circuit is a hassle to check whether the program is completed normally by inputting a read command (Read) again to the fuse circuit 100 after a predetermined time after applying the program start signal (EN_cut). There is this. In addition, since it is not possible to know exactly when the program test is completed, the test timing margin should be long for the time of reading the command. This results in a problem of long program test time.

An object of the present invention is to provide a program test apparatus for a fuse circuit that can automatically detect whether or not the program completion of the fuse circuit.

Still another object of the present invention is to provide a program test apparatus for a fuse circuit capable of automatically performing continuous program tests on all fuse circuits included in a memory device.

(Configuration)

The fuse circuit program test apparatus of the present invention for achieving the above object has a first means for detecting an electrically programmable fuse circuit by the fuse current and the fuse current flowing through the fuse circuit and the fuse current and A second means for comparing a predetermined reference current and sensing whether or not a program test is completed in the fuse circuit according to a comparison result, and a third step of terminating the program operation of the fuse circuit in response to a program completion signal from the second means. Means.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

(Example)

2 is a circuit diagram showing an embodiment of a fuse circuit program test apparatus proposed in the present invention. Referring to FIG. 2, the fuse circuit program test apparatus 200 according to the present invention includes an input unit 210 for inputting a fuse cut signal EN_cut into the fuse circuit 100 and the fuse circuit 100, and the fuse circuit 100. And a detector 220 for detecting the fuse current FUSE_I flowing through the circuit and a comparator 224 for comparing the fuse current FUSE_I and the reference current REF_I and outputting a fuse state. A current comparator 230 and a pulse generator 240 are included.

The fuse circuit 100 uses the conventional fuse circuit shown in FIG. 1 as it is, and is shown as a block only in FIG. 2 to simplify the drawing. The detection unit 220 is implemented with a PMOS transistor 222 connected between the power supply voltage V _EXT and the fuse circuit 100, and detects a current flowing in the fuse circuit 100 when the fuse resistor 102 is cut. Play a role. That is, when the fuse cutting signal EN_cut is applied to the fuse circuit 100 and the cutting operation of the fuse resistor 102 proceeds, the voltage level of the node A connected to the drain terminal of the PMOS transistor 222 is lowered. When the cutting of the fuse resistor 102 is completed, the voltage level of the node A is increased by a large increase in the resistance.

In the comparator 224, the current comparator 230 compares a current flowing through the fuse circuit 100 with a predetermined reference current, and the pulse generator 240 is based on a result of the current comparison by the current comparator 230. A pulse signal PGM_C indicating whether a fuse is cut is generated. The current comparator 230 is connected between the PMOS transistor 232 and the drain terminal of the PMOS transistor 232 connected to the node A in the form of a current mirror (PMOS transistor 222) of the detector 220 and the ground power supply. And an NMOS transistor 234 using the reference current REF_I as a gate. At this time, the reference current REF_I input to the gate terminal of the NMOS transistor 234 is enough to detect a fuse cut in the complementary latch circuit 122 during a read operation of the fuse circuit 100 in the above-described conventional technique. It is the current value that monitors the fuse current. This reference current REF_I must be supplied constantly regardless of external power or temperature. 3 is a circuit diagram showing an embodiment of a reference current generator for this purpose. When the program start signal PGM is enabled, the reference current generator 300 of FIG. 3 is operated by the transistors MP1, MP2, MN2, and MN3 connected in the form of a current mirror with a resistor R1. It makes constant reference current (REF_I) at all times regardless of external power and temperature. The reference current generator 300 shown in FIG. 3 may be implemented in various ways, and any person skilled in the art may know the detailed description thereof.

On the other hand, as mentioned above, the voltage of the node A is lowered to the low level during the fuse cutting, and then to the high level when the fuse cutting is completed. When the voltage at node A is at the low level, the PMOS transistor 232 of the current comparator 230 is turned on, and the node has a larger current driving capability than the NMOS transistor 234 of the PMOS transistor 232 of the current comparator 230. The voltage at D is at the high level. Thereafter, when the fuse cutting is completed and the voltage of the node A transitions to the high level, the PMOS transistor 232 of the current comparator 230 is turned off so that the voltage of the node D transitions to the low level.

In the comparator 224, the pulse generator 240 inputs the program start signal PGM and the voltage of the node D to the fuse when the voltage of the node D transitions from a high level to a low level during a program operation on the fuse circuit. A high level pulse signal PGM_C is generated to indicate that the cutting is completed.

On the other hand, when the program start signal is enabled and the address information ADDR (x) is input, the NOR gate 214 (NOR gate) of the input unit 210 enables the fuse cutting signal EN_cut to the corresponding fuse circuit. When the fuse cutting is completed and the high level pulse signal PGM_C is applied from the pulse generator 240, the fuse cutting signal EN_cut is disabled to a low level to automatically cut the cutting operation of the fuse circuit 100.

A single memory device includes a plurality of fuse circuits. In the related art, a program test is performed for each fuse circuit by inputting corresponding address information, one for each fuse circuit. In the present invention, in order to reduce such inconvenience and test time, an address generator for automatically generating address information for performing a test is used.

4 is a block diagram illustrating an address generator of the present invention for generating address information sequentially using a test address counter. In the address generator shown in FIG. 4, when the pulse signal PGM_C indicating that the fuse cutting is completed is received from the fuse circuit corresponding to the previous address information, the address flag signal ADDR_Flag is applied through the address flag generator 402. Create The test address counter 404 disables the existing address information and sequentially enables the next address information ADDR (x) in response to the address flag signal ADDR_Flag from the address flag generator 402.

FIG. 5 is a circuit diagram illustrating an embodiment of the address flag generator shown in FIG. 4. The address flag generator 402 inputs the pulse signal PGM_C to the NAND gate 502 through two paths having different delay times. The output of the NAND gate 502 is inverted through the inverter 504 to generate an address flag signal ADDR_Flag.

FIG. 6 illustrates address information for performing a program operation only on a desired fuse circuit using an address decoder as another embodiment of the address generator. That is, the address pad ADDR <0: x> configured in advance is decoded by the address decoder to sequentially generate only the address information ADDR (x) corresponding to the fuse circuit at a desired position and input the same into the corresponding fuse circuit.

Although the program test apparatus of the fuse circuit proposed by the present invention has been described in detail through the above description and drawings, this is only one embodiment and various changes and modifications can be made without departing from the technical spirit of the present invention.

As described above, the fuse circuit program test apparatus of the present invention can shorten the program test time by accurately detecting a cutting time of the fuse during the program test of the fuse circuit. In addition, the fuse circuit program test apparatus of the present invention can simplify the entire test process by automatically performing a sequential program test on the entire fuse circuit of the memory device.

1 is a Korean Patent Application Publication No. 2001-0090149 (published: October 18, 2001) and entitled "FUSE CIRCUIT AND PROGRAM STATUS DETECTING METHOD THEREOF." Pat. 6 is a circuit diagram showing an embodiment of a conventional fuse circuit disclosed in No. 6,498,526.

2 is a circuit diagram showing an embodiment of a fuse circuit program test apparatus proposed in the present invention.

3 is a circuit diagram illustrating an embodiment of a reference current generator for generating a reference current REF_I in FIG. 2.

4 is a block diagram illustrating an address generator of the present invention for generating address information sequentially using a test address counter.

FIG. 5 is a circuit diagram illustrating an embodiment of the address flag generator shown in FIG. 4.

6 is a view showing another embodiment of the address generator according to the present invention.

Claims (11)

In the fuse circuit program test apparatus, A fuse circuit electrically programmable by fuse current; First means for detecting the fuse current flowing in the fuse circuit; Second means for comparing the fuse current with a predetermined reference current and detecting whether the program test of the fuse circuit is completed according to a result of the comparison; And And a third means for terminating the program operation of the fuse circuit in response to a program completion signal from the second means. The method of claim 1, And the first means is a first PMOS transistor connected in series between a power supply voltage and the fuse circuit and using the fuse current as a gate input. The method of claim 1, The second means includes a current comparator for comparing the fuse current and the reference current; And a pulse generator for outputting a pulse signal indicating whether or not a program test of the fuse circuit is completed according to a comparison result from the current comparator during a program operation on the fuse circuit. The method of claim 3, wherein The current comparator includes a second PMOS transistor configured in the form of the first PMOS transistor and the current mirror; And An NMOS transistor connected between the second PMOS transistor and a ground voltage using the reference current as a gate input, And the comparison result is output from a node to which the PMOS transistor and the NMOS transistor are connected. The method of claim 3, wherein And the pulse generator is implemented as a NAND gate. The method of claim 1, The reference current is a fuse circuit program test apparatus, characterized in that the current value determined by monitoring the fuse current flowing in the fuse circuit at the time the fuse is cut. The method of claim 1, And said third means further comprises an address generator for generating address information of a fuse circuit to perform a next program operation in response to a program completion signal from said second means. The method of claim 7, wherein And the address generator is an address decoder that sequentially decodes and generates arbitrary address information previously input from the outside during a program operation of the fuse circuit. The method of claim 7, wherein Wherein the address generator sequentially generates address information of a fuse circuit to perform a next program operation in response to a program completion signal input from a fuse circuit in which a current program operation is being performed during a program operation of the fuse circuit. Circuit program test device. The method of claim 9, The address generator includes an address flag generator for generating an address flag signal in response to a program completion signal input from a fuse circuit in which a current program operation is being performed; And And a test address counter for counting and outputting next address information as the input of the address flag signal. The method of claim 10, The address flag generator may include a delay circuit configured to delay a program completion signal input from a fuse circuit in which a current program operation is being performed through two different delay paths; A NAND gater for inputting delay signals from the delay circuit; And And an inverter configured to invert the output of the NAND gator to generate the address flag signal.