KR20070043193A - Equipment for evaluating fusing imformation of semiconductor memory device - Google Patents

Abstract

The present invention relates to a semiconductor memory fusing information reading apparatus and a method of repeatedly performing a fuse precharge and a fuse cutting reading operation in a semiconductor memory device.

A fusing information reading device of a semiconductor memory device for performing a fuse precharging and fusing information reading operation several times to prevent a fusing reading malfunction may include a precharge pulse generator for generating a repeated fuse precharge enable signal; When the fuse is cut by the fuse cutting signal PCUT, and the fuse precharge is performed by the fuse precharge enable signal generated from the precharge pulse generator, the fuse cutting may be determined according to whether the fuse resistor is cut. A latch precharge enable signal (e.g., a latch storing unit for latch storing the fuse cutting determination signal outputted from the fuse cutting determining unit); and a fuse cutting determination signal latched from the latch unit storing unit. And a delay unit configured to delay output for a predetermined time by PRE_LAT).

After the fuse precharging and the fuse cutting read operation are repeatedly performed a predetermined number of times in the semiconductor memory device, and the fuse cutting state is read even once, the fuse is cut and the semiconductor memory device is prevented from malfunctioning due to the fuse cutting error. do.

 Semiconductor Memory Devices, Redundancy Programs, Fuses, Fuse Cutting Information

Description

EQUIPMENT FOR EVALUATING FUSING IMFORMATION OF SEMICONDUCTOR MEMORY DEVICE}

1 is a circuit diagram of a fusing information reading apparatus of a conventional semiconductor memory device.

2 is an operation waveform diagram of each part of FIG.

3 is a circuit diagram of a semiconductor memory fusing information reading apparatus according to an embodiment of the present invention.

4 is a detailed circuit diagram of the precharge pulse generator 10 of FIG. 3.

5 is an operation waveform diagram of each part of FIG.

          Explanation of symbols on the main parts of the drawings

10: fuse precharge pulse generator 20: fuse cutting determination unit

30: latch storage unit 40: delay unit

The present invention relates to a fusing information reading device of a semiconductor memory device, and more particularly, to a fusing information reading device of a semiconductor memory and a method of repeating a fuse precharge and a fuse cutting read operation in a semiconductor memory device a predetermined number of times. It is about.

In general, a semiconductor memory device has a high degree of integration, which is very likely to be a defective memory cell, and even if no defective memory cells exist in an initial test, there is a possibility of a defective memory cell due to repeated data writing / reading. The semiconductor memory device is divided into memory blocks including a plurality of memory cells. In this case, the possibility of failure of the semiconductor memory device may be concentrated in a specific memory block. In order to test the defect of the memory cell in preparation for the occurrence of such defect, input data into the memory cells included in the semiconductor memory device using an external test equipment, and then output the data again to compare the input data with the output data. Detect memory cells. The detected bad memory cells are repaired to redundant memory cells included in the semiconductor memory device. Yield of the semiconductor memory device is greatly affected by the number of redundant memory cells and a method of replacing defective memory cells with redundant memory cells.

Since each major memory cell is individually designated, in order to replace the defective cell, a fuse circuit must be programmed so that an address corresponding to the defective memory cell is stored. The fuse circuit includes a plurality of fuses for storing a defective address. As is well known to those of ordinary skill in the art, faulty addresses can be stored in fuse circuits through selective disconnection of fuses.

Repair methods currently used include a method of replacing fuse memory with redundant memory cells by cutting a fuse with a laser, and a method of replacing defective memory cells with redundant memory cells by cutting or shorting the fuse with an electrical control signal. In the above methods, after the external test equipment tests all the memory cells, the addresses of the defective memory cells are stored in the external test equipment. The fuse corresponding to the redundant memory cells of the semiconductor memory device is cut or shorted and repaired according to an address designating bad memory cells.

1 is a circuit diagram of a fusing information reading apparatus of a conventional semiconductor memory device.

2 is an operational waveform diagram of each part of FIG. 1.

Referring to FIG. 1 and FIG. 2, the operation of the fusing information reading apparatus of the conventional semiconductor memory device will be described.

A fuse resistor R0 connected to a power supply voltage V _DD and being cut by a heating operation, a drain and a source are connected between the fuse resistor R0 and ground, and receiving a fuse cutting signal PCUT through a gate; An en-MOS transistor NM0 for generating a fuse resistor R0, a reference resistor R1 connected to the power supply voltage V _DD , and a PMOS transistor connected in series between the fuse resistor R0 and ground. PM1) and the NMOS transistor NM3, the PMOS transistor PM2 and the NMOS transistor NM4 connected in series between the reference resistor R1 and the ground, and the drain and N of the PMOS transistor PM1. An NMOS transistor NM1 connected between a connection node A1 connected to the drain of the MOS transistor NM3 and ground, and a connection node connected to a drain of the PMOS transistor PM2 and the drain of the NMOS transistor NM4. Between A2) and ground An inverter I1 connected to the connected NMOS transistor NM2, a drain of the PMOS transistor PM2 and a drain of the NMOS transistor NM4, and an inverter I1 connected to an output terminal of the inverter I1. It consists of a connected inverter I2.

Gates of the PMOS transistor PM1 and the NMOS transistor NM3 are connected in common, and gates of the PMOS transistor PM2 and the NMOS transistor NM4 are connected in common. Gates of the PMOS transistor PM1 and the NMOS transistor NM3 are connected to a drain of the NMOS transistor NM2, and gates of the PMOS transistor PM2 and the NMOS transistor NM4 are connected to the NMOS transistor ( NM1) is connected to the drain.

First, the NMOS transistor NM0 is turned on when a fuse cutting signal such as PMRSET of FIG. 2 is applied to the gate. When the NMOS transistor NM0 is turned on, a large current flows through the fuse resistor R0, and the fuse resistor R0 is cut by the heating operation.

After the fuse cutting signal is applied, a fuse precharge enable signal such as PPRE of FIG. 2 for fuse precharge is applied to the gates of the NMOS transistors NM1 and NM2 so that the NMOS transistors NM1 and NM2 are turned on. Precharged. When the fuse precharge is completed, the NMOS transistors NM1 and NM2 are turned off. Then, when the resistance R0 is cut, the resistance R10 is larger than the resistance value 10R, and the connection node A2 has a high (H) potential, and the high (H) potential is the inverter I1. , I2) is latched and enabled as shown in POUT of FIG. 2. That is, the fuse resistor R0 is recognized as being cut.

However, if the fuse resistor R0 is not cut, the connection node A2 has a low L potential in the fuse read section since the fuse resistor R0 has a relatively small resistance value compared to 10R of the reference resistor R1. The low L potential of the connection node A2 is latched through the inverters I1 and I2 to make the disabled state. That is, the fuse resistor R0 is recognized as not cut.

If the output signal Pout is in the high enable state, the defective cell is not accessed and is replaced with a repair cell.

The connection nodes A1 and A2 perform a precharge operation when the fuse precharge enable signal PPRE applied to the gates of the NMOS transistors NM1 and NM2 is high (H). Then, the fuse read operation is performed in the low L section of the fuse precharge enable signal PPRE of FIG. 2.

 In the conventional semiconductor memory fusing information reading apparatus as described above, since the fuse precharging and the fusing information reading operation are performed only once at power-up, the fuse cut operation is not sufficient, so that the fuse resistor R0 is the reference resistor R1. There was a problem that a malfunction is generated because an unwanted output result value is output when the fusing information reading operation is left at a level similar to the resistance value of.

Accordingly, an object of the present invention is to provide a semiconductor memory fusing information reading apparatus and method for preventing a fusing reading malfunction by executing the fuse precharge and the fusing information reading operation several times in order to solve the above problems. have.

The fusing information reading apparatus of the semiconductor memory device for achieving the above object is a precharge pulse generating unit for generating a repeated fuse precharge enable signal, and cutting the fuse resistor by the fuse cutting signal (PCUT), A fuse cutting determination unit for outputting a fuse cutting determination signal according to whether or not the fuse resistance is cut by the fuse precharge enable signal generated from the precharge pulse generator, and from the fuse cutting determination unit And a latch storage unit configured to latch and store the output fuse cutting determination signal, and a delay unit configured to delay output of the fuse cutting determination signal latched from the latch unit storage for a predetermined time by a latch precharge enable signal PRE_LAT. It features.

The fuse cutting determiner may include a first NMOS transistor configured to receive a fuse cutting signal PCUT to generate the fuse resistor, a reference resistor connected to the power supply voltage, and a first coat connected in series between the fuse resistor and the ground. Periodically by an oss transistor and a fourth enmos transistor, a second PMOS transistor and a fifth enmos transistor connected in series between the reference resistor and ground, and a fuse precharge pulse output from the precharge pulse generator. A precharge unit for precharging the connection nodes A1 and A2;

The gates of the first PMOS transistor and the fourth NMOS transistor are commonly connected, and the gates of the second PMOS transistor and the fifth NMOS transistor are commonly connected.

The latch unit may include a first inverter connected to a connection node to which the drain of the first PMOS transistor and the drain of the fifth NMOS transistor are connected, and the second inverter connected to an output terminal of the first inverter. .

The delay unit may be configured to invert the first pre-gate enable signal PPRE_LAT and the first no-gate for delaying outputting the fuse cutting information output from the output of the second inverter in response to a control signal for delaying the fuse cutting information. A third inverter for outputting and delaying the fuse cutting information by the number of fuse precharges set by the latch precharge enable signal PPRE_LAT inverted by the third inverter in response to the output terminal signal of the first noah gate. And a second inverter for outputting a control signal to the first noble gate, and a fourth inverter for inverting the output signal of the first noble gate to output the fuse cutting determination signal.

The method of reading the fusing information of the semiconductor memory device of the present invention for achieving the above object comprises the steps of: generating a repeated fuse precharge enable signal, the fuse precharge and fuse cutting by the generated fuse precharge enable signal And repeating the read operation for a predetermined number of times to store the fuse cutting read information, and outputting the fuse cutting read information when the preset number of times of the fuse cutting read operations is completed.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

3 is a circuit diagram of a semiconductor memory fusing information reading apparatus according to an embodiment of the present invention.

The fuse resistor R0 is cut by the fuse precharge pulse generator 10 and the fuse cutting signal PCUT, which generates a repeated fuse precharge enable signal, and is generated from the precharge pulse generator 10. A fuse cutting determination unit 20 for outputting a fuse cutting determination signal according to whether the fuse resistor R0 is cut each time the fuse precharge is performed by the fuse precharge enable signal, and the fuse cutting determination unit 20 The latch unit 30 latch-storages the fuse cutting determination signal outputted from the < RTI ID = 0.0 >), < / RTI > It consists of a delay part 40 which makes it possible.

The fuse cutting determination unit 20 is connected to the power supply voltage (V _DD ) and the fuse resistor (R0) is cut by the heating action, the drain and the source is connected between the fuse resistor (R0) and the ground, and the gate A first NMOS transistor NM0 for receiving the fuse cutting signal PCUT to generate heat of the fuse resistor R0, a reference resistor R1 connected to the power supply voltage V _DD , and the fuse resistor R0 A first PMOS transistor PM1 and a fourth NMOS transistor NM3 connected in series between a ground and ground, and a second PMOS transistor PM2 and a fifth connected in series between the reference resistor R1 and ground; The second NMOS transistor NM1 connected between the NMOS transistor NM4, the drain of the first PMOS transistor PM1, the drain of the fourth NMOS transistor NM3, and a connection node A1 connected to ground. And a drain and a fifth enmo of the second PMOS transistor PM2. A third switch connected between the transistor connected to the drain of the (NM4) connected to the node (A2) and the ground yen consists Mohs transistor (NM2).

The latch unit 30 includes an inverter I1 connected to a connection node A2 to which the drain of the second PMOS transistor PM2 and the drain of the fifth enMOS transistor NM4 are connected, and the inverter I1. It consists of an inverter I2 connected to the output terminal of.

The delay unit 40 includes a noar gate NOR1 having an output terminal of the inverter I2 connected to one input terminal, an inverter I3 for inverting and outputting a latch precharge enable signal PPRE_LAT, and the noa gate. The output terminal of NOR1 is connected to one input terminal, the latch precharge enable signal PPRE_LAT inverted by the inverter I3 is input to the other input terminal, and the output terminal of the NOA gate NOR1 is connected to another input terminal. It consists of 2 NOR gates NOR2 and inverter I4 which inverts and outputs the output signal of the NOR gate NOR1.

4 is a detailed circuit diagram of the precharge pulse generator 10 of FIG. 3.

A deflip-flop (FF1) for inputting the precharge pulse generation interval signal (POSC START) to the set terminal (S), receiving a predetermined oscillation frequency (POSC) to the clock terminal (CK), and latching it to the output terminal (Q); A deflip-flop FF2 in which an output terminal Q of the deflip-flop FF1 is connected to a clock terminal CK and a precharge pulse generation interval signal POSC START is input to the set terminal S; A deflip-flop FF3 for connecting the output terminal Q of the flip-flop FF2 to the clock terminal CK and inputting the fuse precharge pulse generation period signal POSC START to the set terminal S; A deflip-flop FF4 for connecting the output terminal Q of the deflip-flop FF3 to the clock terminal CK and inputting the fuse precharge pulse generation period signal POSC START to the set terminal S; The output terminal Q of the flip-flop FF4 is connected to the clock terminal CK, the fuse precharge pulse generation section signal POSC START is input to the set terminal S, and the output terminal Q is connected to the de-terminal. It consists of a D flip-flop (FF5) coupled to the data terminal of the lip-flop (FF1) (D).

5 is an operation waveform diagram of each part of FIG. 3.

3 to 5, the operation of reading the fusing information according to the preferred embodiment of the present invention will be described in detail.

First, the NMOS transistor NM0 is turned on when a fuse cutting signal such as PMRSET of FIG. 5 is applied to the gate. When the first NMOS transistor NM0 is turned on, a large current flows through the fuse resistor R0, and the fuse resistor R0 is cut by the heating operation.

The fuse precharge pulse generator 10 generates a repetitive fuse precharge enable signal such as PRE_OSC of FIG. 5 and is applied to the gates of the second and third NMOS transistors NM1 and NM2. As a result, the second and third NMOS transistors NM1 and NM2 are turned on and precharged in the high section of the repetitive fuse precharge enable signal such as PRE_OSC of FIG. 5. The fuse cutting determination unit 20 reads fuse cutting information in a row section of a repetitive fuse precharge enable signal such as PRE_OSC of FIG. 5. The second and third NMOS transistors NM1 and NM2 are turned off in the low section of the repetitive fuse precharge enable signal such as PRE_OSC of FIG. 5.

Then, when the resistance R0 is cut, the resistance R10 is larger than the resistance value 10R, and the connection node A2 has a high (H) potential, and the high (H) potential is the inverter I1. Latched via I2). The latch precharge enable signal PPRE_LAT such as PPRE_LAT of FIG. 5 is inverted through the inverter I3 and applied to another input terminal of the second NOR gate NOR2. At this time, in the low section of the latch precharge enable signal PPRE_LAT, the second NOR gate NOR2 is inverted and ORed with the output signal of the first NOR gate NOR1 to output a high signal. The high signal output from the second NOR gate NOR2 is applied to the other input terminal of the first NOR gate NOR1. As a result, the first NOR gate NOR1 is low until the latch precharge enable signal PPRE_LAT transitions from the high section to the low state so that the fuse precharge and the fuse cutting read information that have been repeatedly executed are not output for a set number of times. Output the status signal. That is, the delay unit 40 including the NOA gates NOR1 and NOR2 and the inverters I3 and I4 delays the fuse cutting read information stored in the latch storage unit 30 so as not to output the set number of fuse precharges. will be.

When the latch precharge enable signal PPRE_LAT transitions from the high section to the low state, the signal is inverted through the inverter I3 and the high signal is applied to the other input terminal of the second NOR gate NOR2. In this case, since the high signal is input to the other input terminal, the second NOR gate NOR2 outputs a low state signal. The low signal output from the second NOR gate NOR2 is applied to another input terminal of the first NOR gate NOR1, and the first NOR gate NOR1 is fuse cutting information output through the inverter I2. Will print The fuse cutting information output from the first NOR gate NOR1 is inverted and output through the inverter I4.

As described above, the fuse precharge enable signal is repeatedly generated in the fuse precharge pulse generator 10 so that the second and third NMOS transistors NM1 and NM2 are turned on so that the connection nodes A1 and A2 are precharged. After the fuse cutting read information of the connection node A2 is detected as a high state even once, the latch cutting is stored in the inverters I1 and I2 so that the fuse cutting information is high through the first NOR gate NOR1 and the inverter I4. Is output. When the fuse cutting information is output in a high state, the fuse resistor R0 is read in a cut state.

However, when the fuse resistor R0 is not cut, the connection node A2 has a low L potential in the fuse cutting information reading section since the fuse resistor R0 has a relatively small resistance value compared to 10R of the reference resistor R1. The low L potential of the connection node A2 is latched and stored through the inverters I1 and I2. The low potential latch-stored by the inverters I1 and I2 is output after being delayed by the delay unit 40 for a predetermined time to have a fuse cutting disable state in which fuse cutting is not performed.

If the output signal Pout is in the high enable state, the defective cell is not accessed and is replaced with a repair cell.

The connection nodes A1 and A2 are precharged when the fuse precharge enable signal PPRE_OSC applied to the gates of the second and third NMOS transistors NM1 and NM2 is high (H). Further, fuse cutting information is output through the connection node A2 in the row L section of the fuse precharge enable signal PPRE_OSC of FIG. 5.

As described above, according to the present invention, after the fuse precharging and the fuse cutting read operation are repeatedly performed a predetermined number of times in the semiconductor memory device, if the fuse cutting state is read at least once, the fuse is cut and read as a fuse cutting error. There is an advantage that can prevent the malfunction of the semiconductor memory device.

Claims (6)

A fusing information reading apparatus of a semiconductor memory device, A precharge pulse generator for generating a repetitive fuse precharge enable signal; A fuse cutting determination signal according to whether a fuse is cut or not is cut whenever a fuse resistor is cut by a fuse cutting signal PCUT and a fuse precharge is performed by a fuse precharge enable signal generated from the precharge pulse generator. Fuse cutting determination unit for outputting a; A latch storage unit for latch storing the fuse cutting determination signal outputted from the fuse cutting determination unit; And a delay unit configured to delay the fuse cutting determination signal stored in the latch unit from the latch unit storage unit for a predetermined time by a latch precharge enable signal PRE_LAT. The method of claim 1, wherein the fuse cutting determination unit, A first NMOS transistor configured to receive a fuse cutting signal PCUT to generate heat to the fuse resistor; A reference resistor connected to the power supply voltage; A first PMOS transistor and a fourth NMOS transistor connected in series between the fuse resistor and ground; A second PMOS transistor and a fifth NMOS transistor connected in series between the reference resistor and ground; Fusing information of the semiconductor memory, wherein the gates of the first PMOS transistor and the fourth NMOS transistor are commonly connected, and the gates of the second PMOS transistor and the fifth NMOS transistor are commonly connected. Reader. The method of claim 2, And a precharge unit which periodically precharges the connection nodes A1 and A2 by the fuse precharge pulses output from the precharge pulse generator. The method of claim 3, wherein the latch unit, A first inverter connected to a connection node to which the drain of the second PMOS transistor and the drain of the fifth NMOS transistor are connected; And a second inverter connected to an output terminal of the first inverter. The method of claim 4, wherein the delay unit, A first noble gate which delays the fuse cutting information output from the output of the second inverter in response to a control signal for delaying the fuse cutting information; A third inverter for inverting and outputting the latch precharge enable signal PPRE_LAT; A control signal for delaying the fuse cutting information by the number of fuse precharges set by the latch precharge enable signal PPRE_LAT inverted by the third inverter in response to the output terminal signal of the first noah gate; A second noah gate output to the gate, And a fourth inverter for inverting the output signal of the first NOR gate and outputting the fuse signal as a fuse cutting determination signal. In the fusing information reading method of a semiconductor memory device, Generating a repetitive fuse precharge enable signal; Storing fuse cutting read information by repeatedly performing a fuse precharge and a fuse cutting read operation by a predetermined number of times by the generated fuse precharge enable signal; And outputting the fuse cutting read information when the fuse cutting read operation of the preset number of times is completed.

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