KR20050118468A - Method of forming a metal wiring in a semiconductor device - Google Patents
Method of forming a metal wiring in a semiconductor device Download PDFInfo
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- KR20050118468A KR20050118468A KR1020040043599A KR20040043599A KR20050118468A KR 20050118468 A KR20050118468 A KR 20050118468A KR 1020040043599 A KR1020040043599 A KR 1020040043599A KR 20040043599 A KR20040043599 A KR 20040043599A KR 20050118468 A KR20050118468 A KR 20050118468A
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- interlayer insulating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
Abstract
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 소정의 구조가 형성된 반도체 기판 상부에 층간 절연막을 형성하는 단계와, 상기 층간 절연막의 소정 영역을 소정 깊이로 식각하는 단계와, 상기 층간 절연막에 플라즈마 처리를 실시하여 상기 층간 절연막의 탄소기를 제거하는 단계와, 상기 층간 절연막을 패터닝하여 비아홀 및 트렌치를 형성하여 듀얼 다마신 패턴을 형성하는 단계와, 전체 구조 상부에 확산 방지막 및 구리층을 형성한 후 연마하여 구리 배선을 형성하는 단계를 포함함으로써 비아홀의 정상적인 식각 프로파일을 얻을 수 있어 저유전막의 사용에 따른 RC 딜레이를 감소시킬 수 있고, 하드 마스크막을 사용하지 않기 때문에 캐패시턴스 감소 효과를 극대화시킬 수 있는 반도체 소자의 금속 배선 형성 방법이 제시된다. The present invention relates to a method for forming a metal wiring of a semiconductor device, comprising the steps of: forming an interlayer insulating film on a semiconductor substrate having a predetermined structure, etching a predetermined region of the interlayer insulating film to a predetermined depth; Performing a plasma treatment to remove carbon groups from the interlayer insulating film, patterning the interlayer insulating film to form via holes and trenches to form a dual damascene pattern, and forming a diffusion barrier and a copper layer over the entire structure. After the polishing to form a copper wiring, it is possible to obtain a normal etching profile of the via hole to reduce the RC delay due to the use of a low dielectric film, and to maximize the capacitance reduction effect because no hard mask film is used. A method of forming metal wirings of a semiconductor device is provided.
Description
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 저유전 층간 절연막에 플라즈마 처리를 실시한 후 다마신 패턴을 형성하는 반도체 소자의 금속 배선 형성 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming metal wirings in semiconductor devices, and more particularly, to a method of forming metal wirings in semiconductor devices in which a damascene pattern is formed after a plasma treatment is performed on a low dielectric interlayer insulating film.
금속 배선의 저항을 감소시켜 반도체 소자의 고집적화와 고성능화를 실현하기 위해서 최근 가장 큰 관심사로 떠오르는 공정이 구리 배선 공정이다. 그러나, 구리 배선은 일반적인 식각 물질로는 거의 식각되지 않기 때문에 층간 절연막을 먼저 식각한 후 구리를 매립하고 평탄화시키는 다마신(damascene) 공정을 이용하고 있다.BACKGROUND OF THE INVENTION In order to reduce the resistance of metal wirings and to realize high integration and high performance of semiconductor devices, a copper wiring process has recently emerged as a major concern. However, since a copper wiring is hardly etched by a general etching material, a damascene process using an interlayer insulating film first to be etched and then embedded and planarized in copper is used.
도 1(a) 내지 도 1(d)는 일반적인 듀얼 다마신 공정으로 구리 금속 배선을 형성하는 방법을 순서적으로 설명하기 위해 도시한 소자의 단면도이다.1 (a) to 1 (d) are cross-sectional views of devices shown in order to explain a method of forming a copper metal wiring in a general dual damascene process.
도 1(a)를 참조하면, 소정의 구조가 형성된 반도체 기판(11) 상부에 제 1 층간 절연막(12)을 형성한다. 제 1 층간 절연막(12)의 소정 영역을 패터닝한 후 전체 구조 상부에 제 1 확산 방지막(13) 및 제 1 구리층(14)을 형성한다. 제 1 구리층(14) 및 제 1 확산 방지막(13)을 연마하여 하부 구리 배선을 형성한다.Referring to FIG. 1A, a first interlayer insulating layer 12 is formed on a semiconductor substrate 11 on which a predetermined structure is formed. After the predetermined region of the first interlayer insulating layer 12 is patterned, the first diffusion barrier 13 and the first copper layer 14 are formed on the entire structure. The first copper layer 14 and the first diffusion barrier film 13 are polished to form lower copper wirings.
도 1(b)를 참조하면, 전체 구조 상부에 제 2 확산 방지막(15)을 형성한 후 층간 절연막(16) 및 하드 마스크막(17)을 형성한다. 층간 절연막(16)은 유전 상수가 3.0 이하인 저유전막을 이용하여 형성하고, 하드 마스크막(17)은 TEOS막을 이용하여 형성한다.Referring to FIG. 1B, after forming the second diffusion barrier layer 15 over the entire structure, the interlayer insulating layer 16 and the hard mask layer 17 are formed. The interlayer insulating film 16 is formed using a low dielectric film having a dielectric constant of 3.0 or less, and the hard mask film 17 is formed using a TEOS film.
도 1(c)를 참조하면, 비아홀 마스크를 이용한 리소그라피 공정 및 식각 공정으로 제 2 층간 절연막(16)을 패터닝하여 비아홀을 형성한 후 트렌치 마스크를 이용한 리소그라피 공정 및 식각 공정으로 제 2 층간 절연막(16)을 패터닝하여 트렌치를 형성한다. 이에 따라 비아홀 및 트렌치로 구성된 듀얼 다마신 패턴이 형성된다. 그런데, 저유전 물질을 이용하여 형성하는 제 2 층간 절연막(16)이 탄소(carbon)를 많이 함유하고 있는 경우나 식각재가 적절하게 셋업되기 전에는 비아홀을 형성하기 위한 식각 공정에서 비아홀 하부에 탄소 폴리머(A)가 생성되어 비아 식각이 불안정하게 된다. 한편, 탄소 폴리머가 생성되었음에도 불구하고 비아홀이 완전히 형성되었다고 하더라도 후속 트렌치를 형성하기 위해 형성된 감광막을 제거할 때 노출된 제 2 층간 절연막(16)은 플라즈마 처리에 의하여 탄소가 제거되기 때문에 금속 배선간 커플링 캐패시턴스가 증가하게 된다.Referring to FIG. 1C, the second interlayer insulating layer 16 is patterned by a lithography process and an etching process using a via hole mask to form via holes, followed by a lithography process and an etching process using a trench mask. ) To form trenches. As a result, a dual damascene pattern formed of via holes and trenches is formed. However, when the second interlayer insulating layer 16 formed by using a low dielectric material contains a large amount of carbon or before the etching material is properly set up, the carbon polymer ( A) is generated and the via etching becomes unstable. On the other hand, even though the via holes are completely formed even though the carbon polymer is formed, the second interlayer insulating film 16 exposed when removing the photoresist film formed to form the subsequent trenches is removed from the plasma by plasma treatment, so that the inter-wire interconnection couples Ring capacitance will increase.
도 1(d)를 참조하면, 듀얼 다마신 패턴을 포함한 전체 구조 상부에 제 3 확산 방지막(18)을 형성한 후 전기 도금 방법으로 제 2 구리층(19)을 형성한다. 그리고, 제 2 구리층(19), 제 2 확산 방지막(18) 및 하드 마스크막(17)을 연마하여 상부 구리 배선을 형성한다. Referring to FIG. 1D, after forming the third diffusion barrier 18 over the entire structure including the dual damascene pattern, the second copper layer 19 is formed by an electroplating method. Then, the second copper layer 19, the second diffusion barrier film 18 and the hard mask film 17 are polished to form upper copper wiring.
상기와 같이 일반적인 방법으로 듀얼 다마신 패턴을 형성할 경우 비아홀을 형성하기 위한 식각 공정에서 비아홀 하부에 탄소 폴리머가 생성되어 비아홀 식각이 불안정하게 되고, 탄소 폴리머에도 불구하고 비아홀이 완전히 형성되었다고 하더라도 트렌치를 형성하기 위한 감광막을 제거할 때 제 2 층간 절연막(16)이 플라즈마 처리에 의하여 탄소가 제거되기 때문에 금속 배선간 커플링 캐패시턴스가 증가하게 된다. When the dual damascene pattern is formed as described above, a carbon polymer is formed in the lower part of the via hole in the etching process for forming the via hole, so that the via hole etching becomes unstable, even though the via hole is completely formed despite the carbon polymer. When the photosensitive film to be formed is removed, carbon is removed from the second interlayer insulating film 16 by plasma treatment, thereby increasing the coupling capacitance between the metal wires.
본 발명의 목적은 저유전 층간 절연막에 플라즈마 처리를 실시하여 층간 절연막의 탄소기를 제거한 후 듀얼 다마신 패턴을 형성함으로써 상기한 문제점을 해결할 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는데 있다. An object of the present invention is to provide a method for forming a metal wiring of a semiconductor device that can solve the above problems by performing a plasma treatment on the low dielectric interlayer insulating film to form a dual damascene pattern after removing the carbon group of the interlayer insulating film.
본 발명에 따른 반도체 소자의 금속 배선 형성 방법은 (a) 소정의 구조가 형성된 반도체 기판 상부에 층간 절연막을 형성하는 단계와, (b) 상기 층간 절연막의 소정 영역을 소정 깊이로 식각하는 단계와, (c) 상기 층간 절연막에 플라즈마 처리를 실시하여 상기 층간 절연막의 탄소기를 제거하는 단계와, (d) 상기 층간 절연막을 패터닝하여 비아홀 및 트렌치를 형성하여 듀얼 다마신 패턴을 형성하는 단계와, (e) 전체 구조 상부에 확산 방지막 및 구리층을 형성한 후 연마하여 구리 배선을 형성하는 단계를 포함한다.The method of forming a metal wiring of a semiconductor device according to the present invention includes the steps of (a) forming an interlayer insulating film on a semiconductor substrate having a predetermined structure, (b) etching a predetermined region of the interlayer insulating film to a predetermined depth; (c) plasma treatment of the interlayer insulating film to remove carbon groups from the interlayer insulating film, (d) patterning the interlayer insulating film to form via holes and trenches to form a dual damascene pattern, and (e ) Forming a diffusion barrier film and a copper layer on the entire structure and then polishing to form a copper wiring.
상기 층간 절연막은 유전 상수가 3.0 이하인 저유전막을 이용하여 형성한다.The interlayer insulating film is formed using a low dielectric film having a dielectric constant of 3.0 or less.
상기 층간 절연막 상부에 하드 마스크막을 형성하는 단계를 더 포함한다.The method may further include forming a hard mask layer on the interlayer insulating layer.
상기 하드 마스크막은 TEOS막을 이용하여 형성한다. The hard mask film is formed using a TEOS film.
상기 (b) 단계는 비아홀 마스크를 이용한 리소그라피 공정 및 식각 공정으로 실시한다.Step (b) is performed by a lithography process and an etching process using a via hole mask.
상기 플라즈마 처리는 CO2 또는 O2 플라즈마를 이용하여 실시한다.The plasma treatment is carried out using a CO 2 or O 2 plasma.
상기 플라즈마 처리는 10 내지 1000W의 파워, 2 내지 10Torr의 압력, 200 내지 1000sccm의 유량 조건으로 60초 미만 실시한다.The plasma treatment is carried out in less than 60 seconds at a power of 10 to 1000W, a pressure of 2 to 10Torr, a flow rate of 200 to 1000sccm.
상기 (d) 단계는 트렌치 마스크를 이용한 리소그라피 공정 및 식각 공정으로 실시한다.Step (d) is performed by a lithography process and an etching process using a trench mask.
상기 (d) 단계는 상기 탄소기가 제거된 부분이 소정 두께로 잔류하도록 실시한다. Step (d) is carried out so that the portion from which the carbon group is removed remains at a predetermined thickness.
이하, 첨부된 도면을 참조하여 본 발명의 실시 예를 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;
도 2(a) 내지 도 2(d)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.2 (a) to 2 (d) are cross-sectional views of devices sequentially shown to explain a method for forming metal wirings of a semiconductor device according to the present invention.
도 2(a)를 참조하면, 소정의 구조가 형성된 반도체 기판(21) 상부에 제 1 층간 절연막(22)을 형성한다. 제 1 층간 절연막(22)의 소정 영역을 패터닝한 후 전체 구조 상부에 제 1 확산 방지막(23) 및 제 1 구리층(24)을 형성한다. 제 1 구리층(24) 및 제 1 확산 방지막(23)을 연마하여 하부 구리 배선을 형성한다.Referring to FIG. 2A, a first interlayer insulating layer 22 is formed on the semiconductor substrate 21 on which a predetermined structure is formed. After the predetermined region of the first interlayer insulating film 22 is patterned, the first diffusion barrier 23 and the first copper layer 24 are formed on the entire structure. The first copper layer 24 and the first diffusion barrier 23 are polished to form lower copper wirings.
도 2(b)를 참조하면, 전체 구조 상부에 제 2 확산 방지막(25)을 형성한 후 제 2 층간 절연막(26)을 형성한다. 제 2 층간 절연막(26)은 유전 상수가 3.0 이하인 저유전막을 이용하여 형성한다. 그리고, 비아홀 마스크를 이용한 리소그라피 공정 및 식각 공정으로 제 2 층간 절연막(26)을 소정 깊이로 식각한다. 상기에서 제 2 층간 절연막(26) 상부에 하드 마스크막을 형성할 수 있는데, 하드 마스크막을 형성할 경우 유전 상수가 4.0 이하의 막, 예를들어 TEOS막을 500Å 미만의 두께로 형성한다.Referring to FIG. 2B, after forming the second diffusion barrier layer 25 on the entire structure, the second interlayer insulating layer 26 is formed. The second interlayer insulating film 26 is formed using a low dielectric film having a dielectric constant of 3.0 or less. The second interlayer insulating layer 26 is etched to a predetermined depth by a lithography process and an etching process using a via hole mask. The hard mask layer may be formed on the second interlayer insulating layer 26. When the hard mask layer is formed, a dielectric constant of 4.0 or less, for example, a TEOS layer is formed to a thickness of less than 500 GPa.
도 2(c)를 참조하면, 제 2 층간 절연막(26)에 플라즈마 처리를 실시한다. 이에 의해 제 2 층간 절연막(26)의 소정 영역의 탄소기가 제거된다(27). 플라즈마 처리는 CO2 또는 O2 플라즈마를 사용하며, 10∼1000W의 파워, 2∼10Torr의 압력, 200∼1000sccm의 유량 조건으로 60초 미만 처리한다.Referring to FIG. 2C, a plasma treatment is performed on the second interlayer insulating film 26. As a result, the carbon group in the predetermined region of the second interlayer insulating film 26 is removed (27). Plasma treatment uses CO 2 or O 2 plasma, and is treated for less than 60 seconds under conditions of power of 10 to 1000 W, pressure of 2 to 10 Torr, and flow rate of 200 to 1000 sccm.
도 2(d)를 참조하면, 트렌치를 형성하기 위한 마스크를 이용한 리소그라피 공정 및 식각 공정으로 제 2 층간 절연막(26)을 패터닝하여 비아홀 및 트렌치를 형성한다. 이때의 식각 공정은 제 2 층간 절연막(26)의 실링 효과를 주기 위해 탄소기가 제거된 부분(27)이 300Å 정도의 두께로 남도록 한다. 그리고, CO2 또는 H2를 이용한 애싱 공정을 실시하고, 전체 구조 상부에 제 3 확산 방지막(28) 및 제 2 구리층(29)을 형성한 후 연마하여 상부 구리 배선을 형성한다.Referring to FIG. 2 (d), via holes and trenches are formed by patterning the second interlayer insulating layer 26 by a lithography process and an etching process using a mask for forming a trench. At this time, in order to give a sealing effect of the second interlayer insulating layer 26, the etching process leaves the portion 27 where the carbon group is removed to a thickness of about 300 kPa. Then, an ashing step using CO 2 or H 2 is performed, and the third diffusion barrier film 28 and the second copper layer 29 are formed over the entire structure, followed by polishing to form the upper copper wiring.
상술한 바와 같이 본 발명에 의하면 층간 절연막에 플라즈마 처리를 실시하여 탄소기를 제거한 후 비아홀 및 트렌치로 구성된 듀얼 다마신 패턴을 형성함으로써 비아홀의 정상적인 식각 프로파일을 얻을 수 있어 저유전막의 사용에 따른 RC 딜레이를 감소시킬 수 있고, 하드 마스크막을 사용하지 않기 때문에 캐패시턴스 감소 효과를 극대화시킬 수 있다.As described above, according to the present invention, plasma treatment is performed on the interlayer insulating film to remove the carbon group, thereby forming a dual damascene pattern consisting of via holes and trenches, thereby obtaining a normal etching profile of the via holes, thereby reducing the RC delay according to the use of the low dielectric film. It can be reduced, and the capacitance reduction effect can be maximized because no hard mask film is used.
도 1(a) 내지 도 1(d)는 종래의 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.1 (a) to 1 (d) are cross-sectional views of devices sequentially shown to explain a conventional metal wiring forming method.
도 2(a) 내지 도 2(d)는 본 발명에 따른 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도. 2 (a) to 2 (d) are cross-sectional views of devices sequentially shown to explain the method for forming metal wirings according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
21 : 반도체 기판 22 : 제 1 층간 절연막21 semiconductor substrate 22 first interlayer insulating film
23 : 제 1 확산 방지막 24 : 제 1 구리층23: first diffusion barrier film 24: first copper layer
25 : 제 2 확산 방지막 26 : 제 2 층간 절연막25 second diffusion barrier layer 26 second interlayer insulating film
27 : 탄소기가 제거된 영역 28 : 제 3 확산 방지막27: region where carbon group is removed 28: third diffusion barrier film
29 : 제 2 구리층 29: second copper layer
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100717502B1 (en) * | 2005-12-29 | 2007-05-14 | 동부일렉트로닉스 주식회사 | Fabricating method of metal line in semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100717502B1 (en) * | 2005-12-29 | 2007-05-14 | 동부일렉트로닉스 주식회사 | Fabricating method of metal line in semiconductor device |
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