KR20050116424A - Method of forming contact plug - Google Patents

Method of forming contact plug Download PDF

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Publication number
KR20050116424A
KR20050116424A KR1020040041314A KR20040041314A KR20050116424A KR 20050116424 A KR20050116424 A KR 20050116424A KR 1020040041314 A KR1020040041314 A KR 1020040041314A KR 20040041314 A KR20040041314 A KR 20040041314A KR 20050116424 A KR20050116424 A KR 20050116424A
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contact hole
interlayer insulating
photoresist pattern
insulating layer
etching
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KR1020040041314A
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Korean (ko)
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김상호
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삼성전자주식회사
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Priority to KR1020040041314A priority Critical patent/KR20050116424A/en
Publication of KR20050116424A publication Critical patent/KR20050116424A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

콘택홀의 상부를 확장시켜 보이드나 틈이 없는 콘택 플러그의 형성방법에 개시한다. 그 방법은 반도체 기판 상에 형성된 층간절연막 상의 포토레지스트 패턴을 식각마스크로 하여 층간절연막의 상부를 등방성 습식식각으로 제거하여, 포토레지스트 패턴의 하부에 언더컷이 발생하도록 제1 콘택홀을 형성한 다음, 이방성 건식식각으로 기판이 노출되도록 층간절연막을 제거하여 제2 콘택홀을 형성한 후, 제1 콘택홀 및 제2 콘택홀이 매립되도록 증착된 금속배선용 물질층을 제거하여 평탄화하는 것을 포함한다. Disclosed is a method of forming a contact plug without extending a contact hole and having no voids or gaps. The method removes the upper portion of the interlayer insulating layer by isotropic wet etching using the photoresist pattern on the interlayer insulating layer formed on the semiconductor substrate as an etch mask, and forms a first contact hole in the lower portion of the photoresist pattern to generate an undercut. Removing the interlayer insulating layer to expose the substrate by anisotropic dry etching to form the second contact hole, and then removing and planarizing the material layer for the metal wiring deposited to fill the first contact hole and the second contact hole.

Description

콘택 플러그 형성방법{Method of forming contact plug}Method of forming contact plug

본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는 보이드나 틈이 없는 콘택 플러그 형성방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact plug without voids or gaps.

일반적으로 다마신 공정은 일련의 사진 공정과 식각 공정을 통해 패터닝하는 기존의 방식과는 다르게, 사진 공정 및 식각 공정을 진행한 후에 식각한 패턴 내부에 금속배선용 물질층을 형성하고 화학적-기계적 폴리싱 공정을 사용하여 패터닝하는 공정을 의미한다. 최근 반도체 소자의 디자인 룰이 작아짐에 따라 금속배선을 위하여 다마신 공정을 많이 적용하고 있다.In general, the damascene process is different from the conventional method of patterning through a series of photolithography and etching processes. After the photolithography and etching processes, a damascene material layer is formed inside the etched pattern and a chemical-mechanical polishing process is performed. Means a process of patterning using. Recently, as the design rules of semiconductor devices become smaller, many damascene processes are applied for metal wiring.

도 1 내지 도 4는 종래의 다마신 공정을 설명하기 위한 단면도들이다. 1 to 4 are cross-sectional views illustrating a conventional damascene process.

도 1을 참조하면, 반도체 기판(10) 상에는 게이트(26)가 형성된다. 게이트(26)는 게이트 절연막(20), 도전층(22) 및 하드 마스크(24)가 순차적으로 적층된 구조를 포함한다. 게이트(26) 측벽에는 자기정렬을 위한 스페이서(28)를 형성한다. 게이트(26) 양측의 반도체 기판(10) 내에 불순물을 주입하여 소오스/드레인 영역(12)을 형성한다. Referring to FIG. 1, a gate 26 is formed on a semiconductor substrate 10. The gate 26 includes a structure in which the gate insulating film 20, the conductive layer 22, and the hard mask 24 are sequentially stacked. Spacers 28 for self-alignment are formed on the sidewalls of the gate 26. Impurities are implanted into the semiconductor substrate 10 on both sides of the gate 26 to form the source / drain regions 12.

도 2에 의하면, 게이트(26)가 형성된 기판(10)의 전면에 층간절연막(30)이 증착된다. 층간절연막(30)에는 금속배선을 위하여 기판(10)이 노출된 콘택홀(32)이 형성되어 있다. 이때, 콘택홀(32)은 비트라인 콘택일 수도 있고 워드라인 콘택일 수도 있다.Referring to FIG. 2, an interlayer insulating film 30 is deposited on the entire surface of the substrate 10 on which the gate 26 is formed. In the interlayer insulating layer 30, a contact hole 32 in which the substrate 10 is exposed is formed for metal wiring. In this case, the contact hole 32 may be a bit line contact or a word line contact.

도 3에 의하면, 콘택홀(32)을 채우도록 기판(10)의 전면에 금속배선용 물질층(34)을 증착한다. 금속배선용 물질층은 예를 들어 폴리실리콘일 수도 있고 텅스텐일 수도 있다. 그런데, 최근 메모리 셀이 고집적화됨에 따라 콘택홀(32)의 임계치수는 점점 작아지고 종횡비는 커지고 있다. 이에 따라, 금속배선용 물질층(34)이 콘택홀(32)을 완전히 채우지 못하여 보이드(void)나 틈(seam; 36)이 생기기도 한다. Referring to FIG. 3, the metal layer 34 is deposited on the entire surface of the substrate 10 to fill the contact hole 32. The material layer for metal wiring may be, for example, polysilicon or tungsten. However, as the memory cells become more integrated in recent years, the critical dimension of the contact hole 32 becomes smaller and the aspect ratio becomes larger. As a result, the material layer 34 for the metal wiring may not completely fill the contact hole 32, and thus voids or gaps 36 may be generated.

도 4에 의하면, 층간절연막(30)의 상면이 노출되도록 CMP를 이용하여 금속배선용 물질층(34)을 제거하여 평탄화한다. 결과적으로, 층간절연막(30)에는 금속배선을 위한 콘택플러그(34')가 형성된다. 그런데, 틈(36) 및 보이드는 콘택 플러그(34')에 그대로 잔존하게 된다. 이러한 보이드나 틈은 금속배선 불량이나 누설전류를 증가시킨다. Referring to FIG. 4, the material layer 34 for metal wiring is removed and planarized using CMP so that the top surface of the interlayer insulating film 30 is exposed. As a result, a contact plug 34 ′ for metal wiring is formed in the interlayer insulating film 30. By the way, the gap 36 and the void remain in the contact plug 34 'as it is. These voids or gaps increase metal wiring defects or increase leakage current.

따라서, 본 발명이 이루고자 하는 기술적 과제는 보이드나 틈이 없는 콘택 플러그의 형성방법을 제공하는 데 있다. Accordingly, a technical object of the present invention is to provide a method for forming a contact plug having no voids or gaps.

상기 기술적 과제를 달성하기 위한 본 발명에 따른 콘택 플러그 형성방법은 먼저, 반도체 기판을 제공한 다음, 상기 반도체 기판 상에 층간절연막을 형성한다. 그후, 상기 층간절연막 상에 제2 콘택홀을 정의하는 포토레지스트 패턴을 형성한다. 상기 포토레지스트 패턴을 식각마스크로 하여 상기 층간절연막의 상부를 등방성 습식식각으로 제거하여, 상기 포토레지스트 패턴의 하부에 언더컷이 발생하도록 제1 콘택홀을 형성한다. 상기 포토레지스트 패턴을 식각마스크로 하여 이방성 건식식각으로 상기 반도체 기판이 노출되도록 상기 층간절연막을 제거하여 제2 콘택홀을 형성한다. 상기 제1 콘택홀 및 제2 콘택홀이 매립되도록 금속배선용 물질층을 증착한다. 상기 층간절연막이 노출되도록 상기 금속배선용 물질층을 제거하여 평탄화한다. In the method of forming a contact plug according to the present invention for achieving the above technical problem, first, a semiconductor substrate is provided, and then an interlayer insulating film is formed on the semiconductor substrate. Thereafter, a photoresist pattern defining a second contact hole is formed on the interlayer insulating film. The upper portion of the interlayer insulating layer is removed by isotropic wet etching using the photoresist pattern as an etch mask, and a first contact hole is formed in the lower portion of the photoresist pattern to generate an undercut. The second contact hole is formed by removing the interlayer insulating layer so that the semiconductor substrate is exposed by anisotropic dry etching using the photoresist pattern as an etching mask. A metal layer material layer is deposited to fill the first contact hole and the second contact hole. The metal wiring material layer is removed and planarized to expose the interlayer insulating layer.

상기 제1 콘택홀의 깊이는 디자인 룰에 의해 결정되는 콘택홀 사이의 간격을 확보할 수 있는 정도인 것이 바람직하다. 상기 제1 콘택홀의 깊이는 식각율과 식각시간에 의하여 결정되는 것이 바람직하다. 또한, 상기 제1 콘택홀은 아래로 갈수록 직경이 작아지는 것이 바람직하다. The depth of the first contact hole is preferably such that a gap between the contact holes determined by the design rule can be secured. The depth of the first contact hole is preferably determined by an etching rate and an etching time. In addition, it is preferable that the diameter of the first contact hole decreases downward.

상기 습식식각은 희석된 HF 또는 NH4F, HF 및 탈이온수의 혼합액인 BOE(Buffered Oxide Etchant)를 이용할 수 있다.The wet etching may use BOE (Buffered Oxide Etchant), which is a mixture of diluted HF or NH 4 F, HF and deionized water.

상기 제2 콘택홀의 직경은 상기 포토레지스트 패턴에 의해 결정될 수 있다. 이하 첨부된 도면을 참조하면서 본 발명의 바람직한 실시예를 상세히 설명한다. 다음에서 설명되는 실시예는 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 아래에서 상술되는 실시예에 한정되는 것은 아니다. 본 발명의 실시예들은 당분야에서 통상의 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위하여 제공되는 것이다. The diameter of the second contact hole may be determined by the photoresist pattern. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments described below may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. Embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art.

도 5 내지 도 10은 본 발명의 실시예에 의한 콘택 플러그 형성방법을 나타낸 단면도들이다. 5 to 10 are cross-sectional views illustrating a method for forming a contact plug according to an embodiment of the present invention.

도 5를 참조하면, 반도체 기판(100) 상에 게이트(116)를 형성된다. 게이트(116)는 게이트 절연막(110), 도전층(112) 및 하드 마스크(114)가 순차적으로 적층된 구조를 포함한다. 게이트(116) 측벽에는 자기정렬을 위한 스페이서(118)를 형성한다. 게이트(116) 양측의 반도체 기판(100) 내에 불순물을 주입하여 소오스/드레인 영역(102)을 형성한다. Referring to FIG. 5, a gate 116 is formed on a semiconductor substrate 100. The gate 116 includes a structure in which the gate insulating layer 110, the conductive layer 112, and the hard mask 114 are sequentially stacked. Spacers 118 for self-alignment are formed on the sidewalls of the gate 116. Impurities are implanted into the semiconductor substrate 100 at both sides of the gate 116 to form the source / drain regions 102.

도 6에 의하면, 게이트(116)가 형성된 기판(100)의 전면에 층간절연막(120)을 증착한다. 층간절연막(120)은 SiOF, SiOC, SiO2 또는 이들의 결합일 수 있다. 층간절연막(120)은 4000Å 내지 7000Å의 두께 범위 내로 형성된다. 다음에, 층간절연막(120) 상에 콘택홀을 형성하기 위한 포토레지스트 패턴(200)을 형성한다.Referring to FIG. 6, an interlayer insulating film 120 is deposited on the entire surface of the substrate 100 on which the gate 116 is formed. The interlayer insulating film 120 may be SiOF, SiOC, SiO 2, or a combination thereof. The interlayer insulating film 120 is formed in a thickness range of 4000 kPa to 7000 kPa. Next, a photoresist pattern 200 for forming a contact hole is formed on the interlayer insulating film 120.

도 7을 참조하면, 포토레지스트 패턴(200)을 식각마스크로 하여 층간절연막(120)의 상부를 등방성 습식식각하여 제1 콘택홀(122)을 형성한다. 등방성 습식식각은 제1 콘택홀(122)의 개구부가 포토레지스트 패턴(200)의 하부로 확장된 언더컷이 발생시킨다.Referring to FIG. 7, the first contact hole 122 is formed by isotropic wet etching the upper portion of the interlayer insulating layer 120 using the photoresist pattern 200 as an etching mask. In the isotropic wet etching, an undercut in which the opening of the first contact hole 122 extends below the photoresist pattern 200 is generated.

이때, 습식식각은 희석된 HF 또는 NH4F, HF 및 탈이온수의 혼합액인 BOE(Buffered Oxide Etchant)를 이용하여 실시할 수 있다. 이때, 제1 콘택홀(122)은 직경이 아래로 갈수록 작아지는 반구형의 형상을 갖는다. 한편, 식각율과 식각시간을 조절하여 층간절연막(120)의 상부에 형성되는 제1 콘택홀(122)의 깊이와 직경을 결정할 수 있다. 식각깊이는 디자인 룰에 의해 결정되는 콘택홀 사이의 간격을 확보할 수 있는 정도가 바람직하다. 후속공정에서 콘택 플러그(도 10의 126')가 연결되지 않을 정도로 마진을 확보하는 것이 바람직하다. 예를 들어 500Å 내지 1000Å의 깊이로 식각할 수 있다.In this case, the wet etching may be performed using a mixed solution of diluted HF or NH 4 F, HF and deionized water, BOE (Buffered Oxide Etchant). In this case, the first contact hole 122 has a hemispherical shape in which the diameter decreases downwards. Meanwhile, the depth and diameter of the first contact hole 122 formed on the interlayer insulating layer 120 may be determined by adjusting the etching rate and the etching time. The etching depth is preferably such that an interval between contact holes determined by the design rule can be secured. In a subsequent process, it is desirable to secure a margin such that the contact plug (126 'in FIG. 10) is not connected. For example, it can be etched to a depth of 500 kPa to 1000 kPa.

도 8에 의하면, 포토레지스트 패턴(200)을 식각마스크로 하여 층간절연막(120)을 이방성 건식식각으로 기판(100)이 노출되도록 제2 콘택홀(124)을 형성한다. 이방성 건식식각은 통상적으로 CF4/CHF3/Ar 가스 분위기에서 진행한다. 제2 콘택홀(124)의 직경은 포토레지스트 패턴(200)에 의해 결정된다. 따라서, 거의 동일한 직경을 가진 원통형의 형상을 갖는다.Referring to FIG. 8, the second contact hole 124 is formed to expose the substrate 100 by anisotropic dry etching the interlayer insulating layer 120 using the photoresist pattern 200 as an etching mask. Anisotropic dry etching typically proceeds in a CF 4 / CHF 3 / Ar gas atmosphere. The diameter of the second contact hole 124 is determined by the photoresist pattern 200. Thus, it has a cylindrical shape with almost the same diameter.

습식식각에 의해 형성된 제1 콘택홀(1220과 건식식각에 의해 형성된 제2 콘택홀(124)은 본 발명의 실시예에 의한 금속배선을 위한 콘택홀(125)을 형성한다. 이어서, 포토레지스트 패턴(200)은 통상적인 방법, 예컨대 산소 플라즈마를 사용하여 에슁(ashing)한 다음 유기 스트립으로 제거할 수 있다.The first contact hole 1220 formed by wet etching and the second contact hole 124 formed by dry etching form a contact hole 125 for metal wiring according to an embodiment of the present invention. 200 may be ashed using conventional methods such as oxygen plasma and then removed with an organic strip.

도 9를 참조하면, 기판(100)의 전면에 콘택홀(125)을 채우도록 금속배선용 물질층(126)을 증착한다. 금속배선용 물질층(126)의 증착은 CVD법이나 ALD법 등이 사용될 수 있다. 금속배선용 물질층(126)으로는 폴리실리콘, 텡스텐, TiN, Al, Ag Au 또는 이들의 합금이 사용될 수 있다. Referring to FIG. 9, the material layer 126 for metallization is deposited to fill the contact hole 125 on the front surface of the substrate 100. The deposition of the metallization material layer 126 may be performed by a CVD method or an ALD method. As the metal layer 126, polysilicon, tungsten, TiN, Al, Ag Au, or an alloy thereof may be used.

도 10에 의하면, 층간절연막(120)의 상부면을 종료점으로 하여 금속배선용 물질층(126)을 제거하여 금속배선 물질층(126)의 상부면을 평탄화한다. 그 결과, 층간절연막(120)에는 금속배선을 위한 콘택 플러그(126')가 형성된다. 금속배선용 물질층(126)은 CMP 공정이나 에치-백 공정을 사용하여 제거될 수 있다. 금속배선용 물질층(120)을 제거는 콘택 플러그(126')간에 연결되지 않을 정도인 것이 바람직하다. 경우에 따라, 상부의 직경이 하부보다 큰 콘택 플러그(126')가 형성될 수 있다. 이는 후속 금속배선 형성시 오버랩 마진을 확보하는 데 도움이 된다. Referring to FIG. 10, the upper surface of the interlayer insulating film 120 is removed to planarize the upper surface of the metallization material layer 126 by removing the metallization material layer 126. As a result, a contact plug 126 ′ for metal wiring is formed in the interlayer insulating film 120. The metallization material layer 126 may be removed using a CMP process or an etch-back process. The removal of the metallization material layer 120 may be such that it is not connected between the contact plugs 126 '. In some cases, a contact plug 126 ′ having an upper diameter greater than the lower portion may be formed. This helps to ensure overlap margin in subsequent metallization.

본 발명의 실시예에 의한 콘택 플러그 형성방법은 콘택홀(125) 상부의 직경을 확장시킴으로써 금속배선용 물질층(126)의 매립이 용이하게 이루어진다. 이에 따라, 콘택홀(125) 내부에는 보이드나 틈이 발생하지 않는다. 또한, 콘택 플러그(126')의 상부면의 면적이 증가하여, 후속 금속배선 형성시 오버랩 마진을 확보할 수 있는 이점을 갖는다. In the method for forming a contact plug according to an exemplary embodiment of the present invention, the material layer 126 for metal wiring is easily formed by expanding the diameter of the upper portion of the contact hole 125. Accordingly, voids or gaps do not occur in the contact hole 125. In addition, the area of the upper surface of the contact plug 126 ′ is increased, and thus, an overlap margin may be secured during subsequent metallization.

이상, 본 발명은 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되지 않으며, 본 발명의 기술적 사상의 범위 내에서 당분야에서 통상의 지식을 가진 자에 의하여 여러 가지 변형이 가능하다. As mentioned above, although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. It is possible.

상술한 본 발명에 의한 콘택 플러그 형성방법에 따르면, 콘택홀의 상부를 확장시킴으로써 보이드나 틈이 없는 콘택 플러그를 제공할 수 있다. According to the method for forming a contact plug according to the present invention described above, a contact plug having no voids or gaps can be provided by expanding an upper portion of the contact hole.

도 1 내지 도 4는 종래의 다마신 공정을 설명하기 위한 단면도들이다.1 to 4 are cross-sectional views illustrating a conventional damascene process.

도 5 내지 도 10은 본 발명에 의한 콘택 플러그 형성방법을 나타낸 단면도들이다. 5 to 10 are cross-sectional views showing a method for forming a contact plug according to the present invention.

*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

100; 반도체 기판 116; 게이트100; Semiconductor substrate 116; gate

120; 층간절연막 122; 제1 콘택홀120; Interlayer insulating film 122; 1st contact hole

124; 제2 콘택홀 125; 콘택홀124; Second contact hole 125; Contact hole

126'; 콘택 플러그126 '; Contact plug

Claims (6)

반도체 기판을 제공하는 단계;Providing a semiconductor substrate; 상기 반도체 기판 상에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on the semiconductor substrate; 상기 층간절연막 상에 제2 콘택홀을 정의하는 포토레지스트 패턴을 형성하는 단계;Forming a photoresist pattern defining a second contact hole on the interlayer insulating film; 상기 포토레지스트 패턴을 식각마스크로 하여 상기 층간절연막의 상부를 등방성 습식식각으로 제거하여, 상기 포토레지스트 패턴의 하부에 언더컷이 발생하도록 제1 콘택홀을 형성하는 단계;Removing the upper portion of the interlayer insulating layer by isotropic wet etching using the photoresist pattern as an etch mask to form a first contact hole to undercut the lower portion of the photoresist pattern; 상기 포토레지스트 패턴을 식각마스크로 하여 이방성 건식식각으로 상기 반도체 기판이 노출되도록 상기 층간절연막을 제거하여 제2 콘택홀을 형성하는 단계; Forming a second contact hole by removing the interlayer insulating layer so that the semiconductor substrate is exposed by anisotropic dry etching using the photoresist pattern as an etching mask; 상기 제1 콘택홀 및 제2 콘택홀이 매립되도록 금속배선용 물질층을 증착하는 단계;Depositing a metal wiring material layer to fill the first contact hole and the second contact hole; 상기 층간절연막이 노출되도록 상기 금속배선용 물질층을 제거하여 평탄화하는 단계를 포함하는 것을 특징으로 하는 콘택 플러그 형성방법. And removing the planarization material layer to planarize the interlayer insulating layer so as to expose the interlayer insulating layer. 제1항에 있어서, 상기 제1 콘택홀의 깊이는 디자인 룰에 의해 결정되는 콘택홀 사이의 간격을 확보할 수 있는 정도인 것을 특징으로 하는 콘택 플러그 형성방법. The method of claim 1, wherein the depth of the first contact hole is such that a gap between the contact holes determined by a design rule can be secured. 제1항에 있어서, 상기 제1 콘택홀의 깊이는 식각율과 식각시간에 의하여 결정되는 것을 특징으로 하는 콘택 플러그 형성방법.The method of claim 1, wherein the depth of the first contact hole is determined by an etching rate and an etching time. 제1항에 있어서, 상기 제1 콘택홀은 아래로 갈수록 직경이 작아지는 것을 특징으로 하는 콘택 플러그 형성방법.The method of claim 1, wherein the diameter of the first contact hole decreases downwardly. 제1항에 있어서, 상기 습식식각은 희석된 HF 또는 NH4F, HF 및 탈이온수의 혼합액인 BOE(Buffered Oxide Etchant)를 이용하는 것을 특징으로 하는 콘택 플러그 형성방법.The method of claim 1, wherein the wet etching is performed using a buffered oxide etchant (BOE), which is a mixture of diluted HF or NH 4 F, HF, and deionized water. 제1항에 있어서, 상기 제2 콘택홀의 직경은 상기 포토레지스트 패턴에 의해 결정되는 것을 특징으로 하는 콘택 플러그 형성방법.The method of claim 1, wherein the diameter of the second contact hole is determined by the photoresist pattern.
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