KR20050113072A - In plane switching mode liquid crystal display device and method of fabricating thereof - Google Patents

Abstract

The method of manufacturing the transverse electric field mode liquid crystal display device of the present invention is to simplify the manufacturing method and reduce the manufacturing cost. The method of manufacturing the transverse electric field mode liquid crystal display device includes a gate electrode and a gate on a first substrate using a first mask. Forming a common electrode, a pixel electrode, and a pad forming a line, a transverse electric field, and forming a first insulating layer and a semiconductor layer on the gate electrode by using a second mask, and on and side surfaces of a part of the common electrode. Forming a second insulating layer on the substrate; forming a source electrode and a drain electrode on the semiconductor layer using a third mask; forming a data line on the second insulating layer; and stacking a protective layer on the substrate. And opening the pad.

Description

Transverse electric field mode liquid crystal display device and manufacturing method therefor {IN PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transverse electric field mode liquid crystal display device, and more particularly, to a transverse electric field mode liquid crystal display device having a simplified process and a reduction in manufacturing cost and an improved aperture ratio.

Recently, with the development of various portable electronic devices such as mobile phones, PDAs, and notebook computers, there is a growing demand for flat panel display devices for light and thin applications. Such flat panel displays are being actively researched, such as LCD (Liquid Crystal Display), PDP (Plasma Display Panel), FED (Field Emission Display), VFD (Vacuum Fluorescent Display), but mass production technology, ease of driving means, Liquid crystal display devices (LCDs) are in the spotlight for reasons of implementation.

The liquid crystal display device has various display modes according to the arrangement of the liquid crystal molecules. However, the liquid crystal display device of the TN mode is mainly used because of the advantages of easy monochrome display, fast response speed, and low driving voltage. In such a TN mode liquid crystal display device, liquid crystal molecules aligned horizontally with the substrate are almost perpendicular to the substrate when a voltage is applied. Therefore, there is a problem that the viewing angle is narrowed upon application of voltage due to the refractive anisotropy of the liquid crystal molecules.

In order to solve this viewing angle problem, liquid crystal display devices of various modes having wide viewing angle characteristics have recently been proposed, but among them, the liquid crystal display device of the lateral field mode (In Plane Switching Mode) is applied to actual production. It is produced. The IPS mode liquid crystal display device aligns liquid crystal molecules in a plane by forming at least one pair of electrodes arranged in parallel in a pixel to form a transverse electric field substantially parallel to the substrate.

1 is a view showing the structure of a conventional IPS mode liquid crystal display device, in which FIG. 1 (a) is a plan view and FIG. 1 (b) is a sectional view taken along the line II ′ of FIG. As shown in FIG. 1A, the pixels of the liquid crystal panel 1 are defined by gate lines 3 and data lines 4 arranged vertically and horizontally. Although only the (n, m) th pixels are shown in the drawing, in the liquid crystal panel 1, n and m gate lines 3 and data lines 4 are disposed, respectively, and thus the liquid crystal panel 1 is disposed. N x m pixels are formed throughout. The thin film transistor 10 is formed at the intersection of the gate line 3 and the data line 4 in the pixel.

The thin film transistor 10 includes a gate electrode 11 to which a scan signal is applied from the gate line 3, and a semiconductor layer formed on the gate electrode 11 and activated as a scan signal is applied to form a channel layer. 12 and a source electrode 13 and a drain electrode 14 formed on the semiconductor layer 12 and to which an image signal is applied through the data line 4. The image signal input from the outside is applied to the liquid crystal layer. do.

In the pixel, a plurality of common electrodes 5 and a pixel electrode 7 are arranged substantially parallel to the data line 4. In addition, a common line 16 connected to the common electrode 5 is disposed in an upper region of the pixel, and a pixel electrode line 18 connected to the pixel electrode 7 is disposed on the common line 16. It overlaps with the common line 16. Storage capacitance is formed in the transverse electric field mode liquid crystal display by overlapping the common line 16 and the pixel electrode line 18.

In the IPS mode liquid crystal display device configured as described above, the liquid crystal molecules are aligned substantially in parallel with the common electrode 5 and the pixel electrode 7. When the thin film transistor 10 is operated to apply a signal to the pixel electrode 7, a transverse electric field substantially parallel to the liquid crystal panel 1 is generated between the common electrode 5 and the pixel electrode 7. Since the liquid crystal molecules rotate on the same plane along the transverse electric field, gray level inversion due to the refractive anisotropy of the liquid crystal molecules can be prevented.

The conventional IPS mode liquid crystal display device having the above structure will be described in more detail with reference to the cross-sectional view of FIG.

As shown in FIG. 1B, a gate electrode 11 is formed on the first substrate 20, and a gate insulating layer 22 is stacked over the entire first substrate 20. The semiconductor layer 12 is formed on the gate insulating layer 22, and the source electrode 13 and the drain electrode 14 are formed thereon. In addition, a passivation layer 24 is formed on the entire first substrate 20.

In addition, a plurality of common electrodes 5 are formed on the first substrate 20, and a pixel electrode 7 and a data line 4 are formed on the gate insulating layer 22 to form the common electrode 5. The transverse electric field E is generated between the pixel electrodes 7.

The black matrix 32 and the color filter layer 34 are formed on the second substrate 30. The black matrix 32 is to prevent light leakage into an area where the liquid crystal molecules do not operate. As shown in the drawing, the black matrix 32 is formed between the region of the thin film transistor 10 and between the pixel and the pixel (ie, the gate line and the data line). Area). The color filter layer 34 is composed of R (Red), B (Blue), and G (Green) to realize actual colors.

The liquid crystal layer 40 is formed between the first substrate 20 and the second substrate 30 to complete the liquid crystal panel 1.

As described above, in the IPS mode liquid crystal display device, the transverse electric field E is formed inside the liquid crystal layer 40 by the common electrode 5 and the pixel electrode 7 formed on the substrate 20 and the gate insulating layer 22, respectively. Is generated to drive the liquid crystal molecules inside the liquid crystal layer 40.

2 (a) to 2 (e) show a method of manufacturing a conventional IPS mode liquid crystal display device having the above structure. In this case, in order to specifically explain the manufacturing method of the IPS mode liquid crystal display device, the substrate is divided into a display area in which pixels are formed to form an actual image, and a pad area in which pads and driving elements are formed to apply a signal to the display area. .

First, as shown in FIG. 2A, after the metal is stacked on the first substrate 20, the gate electrode 11 and the common electrode 5 are formed in the display area using the first mask, and then the pad area. The gate pad 52 is formed in this. Subsequently, as shown in FIG. 2B, after the gate insulating layer 22 is formed over the entire first substrate 20, semiconductors are stacked and the semiconductors are patterned by using a second mask. The semiconductor layer 12 is formed on the gate insulating layer 22. Although not shown in the drawing, an ohmic contact layer is formed on the semiconductor layer 12.

After that, as shown in FIG. 2C, the metals are stacked and the metals are etched using the third mask to form the source electrode 13 and the drain electrode 14 on the semiconductor layer 12, and the gate insulating layer. The pixel electrode 7 is formed over the 22. Subsequently, as shown in FIG. 2 (d), a passivation layer 24 is formed over the entire first substrate 20 and then the passivation layer 24 and the gate of the pad region are formed using the fourth mask. The insulating layer 22 is etched to expose the gate pad 52. In addition, a transparent conductive material such as indium tin oxide (ITO) is stacked on the protective layer 24 and then etched using a fifth mask to form a transparent conductive layer 54 on the gate pad 52. The reason for forming the transparent conductive layer 54 is to prevent the gate pad 52 from being oxidized by being exposed to oxygen during the process.

Subsequently, as shown in FIG. 2E, the black matrix 32 for blocking light transmitted to the image non-display area on the second substrate 30 and the color filter layer 34 for realizing color are provided. After forming the first substrate 20 and the second substrate 30, the liquid crystal layer 40 is formed between the first substrate 20 and the second substrate 30 to form an IPS mode liquid crystal display device. To complete.

As described above, in the conventional IPS mode liquid crystal display device manufacturing method, a mask for forming a gate electrode and a common electrode, a mask for forming a semiconductor layer, a mask for forming a source / drain electrode and a pixel electrode, a mask for forming a protective layer, and a layer for forming a transparent conductive layer. A total of five masks, such as a mask, are required. Therefore, in the conventional IPS mode liquid crystal display device manufacturing process, the process is complicated, the manufacturing cost increases, and there is a problem that requires a large installation cost.

An object of the present invention is to provide a transverse electric field mode liquid crystal display device having a simplified process and a reduced manufacturing cost, and a method of manufacturing the same.

Another object of the present invention is to provide a transverse electric field mode liquid crystal display device which can efficiently insulate the data line and the common electrode by placing a gate insulating layer between the data line and the common electrode disposed near the data line.

It is still another object of the present invention to provide a transverse electric field mode liquid crystal display device capable of improving the aperture ratio by reducing the gap between the data line and the common electrode disposed near the data line.

In order to achieve the above object, the transverse electric field mode liquid crystal display device according to the present invention comprises a plurality of gate lines and data lines defining a plurality of pixels, a thin film transistor disposed in each pixel, and arranged horizontally in the pixel. At least one pair of common and pixel electrodes forming an electric field, and a first insulating layer having a data line disposed above and a side surface of the common electrode facing the data line disposed below.

In addition, a method of manufacturing a transverse electric field mode liquid crystal display device according to the present invention may include forming a common electrode, a pixel electrode, and a pad to form a gate electrode, a gate line, and a transverse electric field on a first substrate using a first mask; Forming a first insulating layer and a semiconductor layer on the gate electrode by using a second mask, and forming a second insulating layer on and at a side of a portion of the common electrode; and using the third mask. Forming a source electrode and a drain electrode on the layer, forming a data line on the second insulating layer, and laminating a protective layer on the substrate and opening a pad.

In the present invention, the number of masks used in the manufacture of the IPS mode liquid crystal display device is minimized, thereby simplifying the manufacturing process and reducing the manufacturing cost. While five masks are required to fabricate a conventional IPS mode liquid crystal display device, the present invention requires only three masks, thereby simplifying the photolithography process and greatly reducing the manufacturing cost.

Meanwhile, in the present invention, since the common electrode and the pixel electrode are directly formed on the substrate and made of a transparent conductive material, not only the luminance of the IPS mode liquid crystal display device is improved but also the aperture ratio is improved. The data line is formed over the gate insulating layer. Therefore, since the data line and the common electrode disposed in the vicinity thereof are insulated from each other by the gate insulating layer, it is possible to prevent a defect of the IPS mode liquid crystal display device due to a short circuit. In addition, the presence of the gate insulating layer means that the gap between the data line and the common electrode can be further narrowed, and the reduction of the gap means the improvement of the aperture ratio of the IPS mode liquid crystal display.

Hereinafter, an IPS mode liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.

3 (a) to 3 (g) are views showing a manufacturing method of an IPS mode liquid crystal display device according to the present invention.

First, as shown in FIG. 3 (a), a transparent conductive layer and a metal layer are successively stacked on a first substrate 120 made of a transparent material such as glass and including a display area and a pad area. The transparent conductive layer and the metal layer are etched together to form two layers of gate electrodes 111a and 111b, common electrodes 105a and 105b and pixel electrodes 107a and 107b in the display area, and two layers in the pad area. Gate pads 152a and 152b are formed.

The metal and the transparent conductive material are laminated by evaporation or sputtering. The metal is mainly composed of Cu, Cu alloy, Al, Al alloy, Cr, Mo, Ag, Ta, Ti, MoW, and the like. The transparent conductive material mainly consists of indium tin oxide (ITO) or indium zinc oxide (IZO).

Meanwhile, the gate electrode, the common electrode, and the pixel electrode may be formed of three layers. In this case, the first metal layer made of Cu, Cu alloy, Al, Al alloy, etc., the second metal layer made of Ti, Mo, Ta, Cr, Ag, MoW, etc. and the agent made of Cu, Cu alloy, Al, Al alloy, etc. The gate electrode, the common electrode, and the pixel electrode may be formed by sequentially stacking three metal layers (or a combination thereof) and then etching them all at once.

Thereafter, as shown in FIG. 3B, a semiconductor including an insulating layer 122 such as SiNx or SiOx, silicon (Si), or the like is formed over the entire first substrate 120 by CVD (Chemical Vapor Deposition). After sequentially stacking the layers 112, the photoresist is stacked on the semiconductor layer 112 and etched using a second mask to form first photoresist patterns 162a and 162b.

In this case, although not shown, an impurity semiconductor layer doped with impurities is formed on the semiconductor layer 112.

Subsequently, as shown in FIG. 3C, the insulating layer 122 and the semiconductor layer 112 are etched using the first photoresist patterns 162a and 162b to form the gate electrodes 111a and 111b. Gate insulating layers 122a and 122b and semiconductor layers 112a and 112b are formed on upper and part portions and side surfaces of the common electrode 105a, respectively. At this time, the common electrodes 105a and 105b and the pixel electrodes 107a and 107b are exposed to the outside by the etching as described above.

After stripping the first photoresist pattern 162, Cr, Mo, and / or sputtering methods are performed over the entire first substrate 120 by deposition or sputtering, as shown in FIG. Ta, Ti, Ag, MoW, Cu, Cu alloy, Al or Al alloy, etc. are laminated to form a metal layer 104. Subsequently, a photoresist is stacked on the metal layer 104 and developed by a third mask to form a gate insulating layer 122a and an upper portion of the semiconductor layer 112a (that is, an upper portion of the gate electrodes 111a and 111b) and gate insulation. Second photoresist patterns 164a and 164b are formed on the layer 122b and the semiconductor layer 112b, respectively. In this case, the photoresist pattern 164a on the gate insulating layer 122a and the semiconductor layer 112a is formed to have a wider width than the gate insulating layer 122a and the semiconductor layer 112a and the gate insulating layer 122b and the semiconductor. The photoresist pattern 164b over the layer 112b is formed to have a smaller width than the gate insulating layer 122b and the semiconductor layer 112b.

In this case, the third mask is a diffraction mask. That is, it is a diffraction mask which consists of a transmission area which permeate | transmits light (for example, an ultraviolet-ray) incident to a photoresist layer, the blocking area which blocks | blocks light, and the diffraction area | region (or semi-transmissive area | region) which transmits only a part of light. . Therefore, when developing the photoresist layer, a part of the photoresist layer on the gate electrodes 111a and 111b is removed (this region is a region where the channel layer of the thin film transistor is formed).

Subsequently, as illustrated in FIG. 3E, the metal layer 104 is etched using the second photoresist patterns 164a and 164b, and the second photoresist patterns 164a and 164b are ashed. By exposing the metal layer 104 on the gate electrodes 111a and 111b to the outside and then etching the exposed metal layer 104, the source electrode 113 and the drain electrode 114 are formed on the semiconductor layer 112a. The data line 104a is formed on the gate insulating layer 122b.

Meanwhile, when etching the metal layer 104, the common electrode 105b, the pixel electrode 107b, and the gate pad 152b made of an opaque metal are also etched. However, the transparent conductive layer such as ITO or IZO remains unetched due to the difference in etching selectivity with the metal. In other words, the common electrode 105a, the pixel electrode 107a, and the gate pad 152a are eventually formed of a single layer made of a transparent conductive material made of ITO or IZO. In addition, the semiconductor layer 112b on the gate insulating layer 122b is removed using the second photoresist pattern 164b on the data line 104a to leave the semiconductor layer 112c only under the data line 104a. .

In addition, when the metal layer 104 is etched, an impurity semiconductor layer (not shown) in the channel region is removed to form an ohmic contact layer.

3 (f), the protective layer 124 is formed by stacking an inorganic material such as SiNx or SiOx or an organic material such as BCB (Benzo Cyclo Butene) or photoacryl over the first substrate 120. After forming, the gate pad 152a is exposed to the outside by exposing the pad region to plasma or dipping in an acid such as HF to remove the protective layer 124 of the pad region. Since the gate pad 152a is formed of a transparent conductive layer such as ITO or IZO, since the gate pad 152a is not oxidized by oxygen even when exposed to the outside, a separate antioxidant layer for preventing oxidation of the pad is not required.

Subsequently, as shown in FIG. 3 (g), a black matrix 132 made of Cr / CrOx, black resin, or the like is formed on the second substrate 130, and then the color filter layer 134 is formed. The first substrate 120 and the second substrate 130 are bonded to each other, and the liquid crystal layer 140 is formed between the first substrate 120 and the second substrate 130 to complete the IPS mode liquid crystal display device. Although not shown in the drawing, an overcoat layer may be formed on the color filter layer 134 to protect the color filter layer 134 and planarize the second substrate 130.

The liquid crystal layer 140 is typically formed by bonding the first substrate 120 and the second substrate 130 and then vacuum injecting liquid crystal therebetween. However, the liquid crystal drop 140 has recently been spotlighted. It may be formed by a liquid crystal dispensing process. That is, after directly dropping the liquid crystal onto the first substrate 120 or the second substrate 130, the first substrate 120 and the second substrate 130 are bonded to each other to form the liquid crystal by pressure. ), The liquid crystal layer 140 may be formed by uniformly distributing the same.

Although not shown in the drawing, not only the gate pad 152a for applying the signal to the gate line 103 but also the data pad for applying the signal to the data line 104a may be formed in the pad region. At this time, the data pad is formed on the same layer as the data line 104a by the same process, and the protective layer 124 thereon will be exposed to the outside by plasma exposure and immersion into acid.

As described above, in the IPS mode liquid crystal display device manufacturing method according to the present invention, a first mask for forming a gate electrode, a gate pad (and a data pad), a common electrode and a pixel electrode, a second mask for forming a semiconductor layer, and a source There is a need for a third mask for forming electrodes and drain electrodes. That is, in order to manufacture a conventional IPS mode liquid crystal display device, a total of five masks are required, whereas a total of three masks are required in the present invention. Accordingly, it can be seen that the manufacturing method of the IPS mode liquid crystal display device according to the present invention is greatly simplified as compared to the conventional method of manufacturing the IPS mode liquid crystal display device. As a result, the manufacturing cost of the IPS mode liquid crystal display device can be greatly reduced. do.

On the other hand, referring to Figure 3 (g) looks at the structure of the IPS mode liquid crystal display device according to the present invention.

As shown in FIG. 3 (g), in the IPS mode liquid crystal display device according to the present invention, the gate electrodes 111a and 111b of the thin film transistor have two layers. That is, the gate electrode includes a transparent conductive layer 111a made of a transparent conductive material such as ITO or IZO and a metal layer 111b made of an opaque metal.

At least one common electrode 105a and the pixel electrode 107a disposed in the pixel in the display area to form a transverse electric field substantially parallel to the surface of the substrate 120 are directly formed on the first substrate 120. . That is, the common electrode 105a and the pixel electrode 107a are formed in the same layer. By arranging the common electrode 105a and the pixel electrode 107a in the same layer, a uniform transverse electric field is applied to the liquid crystal layer 140. In addition, since a gate insulating layer is not formed on the common electrode 105a and the pixel electrode 107a, trapping of charges by the gate insulating layer can be prevented.

The common electrode 105a and the pixel electrode 107a are formed of a transparent conductive layer such as ITO and IZO. Accordingly, the luminance (white luminance) and the aperture ratio are improved as compared with the conventional IPS mode liquid crystal display device in which the common electrode and the pixel electrode are formed of an opaque metal.

The data line 104a is formed on the gate insulating layer 122b, and the gate insulating layer 122b is partially formed on the common electrode 105a disposed near the data line 104a. In other words, a gate insulating layer 122b exists in the data line 104a and the common electrode 105a. Such a presence of the gate insulating layer 122b effectively insulates the data line 104a and the common electrode 105a, thereby effectively preventing a defect in the IPS mode liquid crystal display device due to a short circuit.

In addition, the gate insulating layer 122b improves the aperture ratio of the IPS mode liquid crystal display device. In general, the data line 104a and the common electrode 105a should be arranged at a predetermined interval or more to prevent a short circuit. In addition, the data line 104a and the common electrode 105a disposed near the data line 104a and the gap therebetween are blocked by the black matrix 132 formed on the second substrate 130 to prevent leakage of light. When the gate insulating layer 122b is formed between the data line 104a and the common electrode 105a as in the IPS mode liquid crystal display device of the present invention, the gap between the data line 104a and the common electrode 105a is reduced. In the case of narrower than before, the data line 104a and the common electrode 105a are not shorted. Therefore, the width of the black matrix 132 formed on the data line 104a and the common electrode 105a of the second substrate 130 can be reduced, thereby improving the aperture ratio of the IPS mode liquid crystal display device. It will be possible.

The structure of the IPS mode liquid crystal display device 101 configured as described above will be described in more detail with reference to the plan view shown in FIG. 4.

As shown in FIG. 4, a thin film transistor 110 is formed at an intersection of the gate line 103 and the data line 104a, and the common electrode 105a and the pixel electrode 107a made of a transparent conductive material are formed. It is disposed substantially parallel in the pixel to form a transverse electric field.

The common electrode 105a is disposed on both sides of the data line 104a, because the common electrode 105a shields an electric field generated between the data line 104a and the pixel electrode 107a and transverses it. This is to prevent distortion in the electric field. As shown in the drawing, the data line 104a is formed on the gate insulating layer 122b and the side surface of the common electrode 105a facing the data line 104a is formed under the gate insulating layer 122b. As a result, the gate insulating layer 122b is positioned between the data line 104a and the common electrode 105a which face each other. As such, since the data line 104a and the common electrode 105a are insulated by the gate insulating layer 122b, the gap b between the data line 104a and the common electrode 105a is shown in FIG. In the conventional IPS mode liquid crystal display device, the gap between the data line 104a and the common electrode 105a can be made smaller (b <a). As described above, as the distance b between the data line 104a and the common electrode 105a decreases, the aperture ratio of the IPS mode liquid crystal display device is improved.

On the other hand, the common line 116 and the pixel electrode line 118 are disposed in the upper region (or may be formed in the central region) of the pixel with the gate insulating layer 122b interposed therebetween to form a storage capacitor. Like the gate lines 111a and 111b of the thin film transistor 110, the common line 116 may be formed of a transparent conductive layer and an opaque metal layer, or may be formed of a transparent conductive layer like the common electrode 105a. That is, the common line 116 is formed by the same process as the gate electrodes 111a and 111b or the common electrode 105a of the thin film transistor.

The pixel electrode line 118 is formed of the same metal by the same process as the source electrode 113 and the drain electrode 114 of the thin film transistor 110. In this case, the pixel electrode line 118 and the pixel electrode 107b are electrically connected to each other by the second contact hole 119b formed in the gate insulating layer 122b. In addition, the pixel electrode 107b is electrically connected to the drain electrode 114 of the thin film transistor 110 by the first contact hole 119a.

On the other hand, in the above drawings, the IPS mode liquid crystal display device having a specific structure is disclosed, but the present invention is not limited to the IPS mode liquid crystal display device having such a structure. For example, although a specific number of common electrodes 105a and pixel electrodes 107a are disposed in the pixel, the number of the common electrodes 105a and the pixel electrodes 107a need not be limited. In addition, the structures of the common electrode 105a and the pixel electrode 107a disposed in the pixel need not be limited.

5 is a plan view showing another structure of the IPS mode liquid crystal display device according to the present invention. The IPS mode liquid crystal display device 201 having the structure shown in FIG. 5 has a structure similar to that of the IPS mode liquid crystal display device having the structures shown in FIGS. 3G and 4, and has only a common electrode 205a and a pixel electrode. Only the structure of 207a is different. That is, in the IPS mode liquid crystal display device having this structure, the common electrode 205a and the pixel electrode 207a are formed on the substrate as a transparent conductive layer, and between the data line 204a and the common electrode 205a disposed therebetween. A gate insulating layer 222b is formed to safely insulate the data line 204a and the common electrode 205a.

On the other hand, in the IPS mode liquid crystal display device having this structure, the common electrode 205a and the pixel electrode 207a are bent in the pixel. This bending is for dividing the pixel into a plurality of domains. That is, the liquid crystal molecules of each domain are arranged symmetrically with the adjacent domains to compensate for the field of view, thereby improving the viewing angle characteristic. In the drawing, the common electrode 205a and the pixel electrode 207a are bent once to form two domains in the pixel, but the common electrode 205a and the pixel electrode 207a are bent several times to form three or more domains. It may be formed. In addition, as shown in the drawing, the pixel itself is not bent (that is, the data line is bent), but the pixel itself is not bent (that is, the data line is not bent) and the common electrode 205a and the pixel electrode are disposed in the pixel. You may bend only 207a.

As described above, in the present invention, an IPS mode liquid crystal display device is manufactured using three masks. Thus, the number of masks used by the conventional manufacturing method is reduced, resulting in a simplified manufacturing process and a significant reduction in manufacturing cost. In addition, in the present invention, a gate insulating layer may be disposed between the data line and the common electrodes disposed on both sides thereof, thereby preventing the data line and the common electrode from being shorted. Further, in the present invention, since the gap between the data line and the common electrode can be reduced by the gate insulating layer between the data line and the common electrode, the aperture ratio of the IPS mode liquid crystal display device can be improved.

Figure 1 (a) is a plan view of a conventional transverse electric field mode liquid crystal display device.

(B) is sectional drawing along the II 'line | wire of (a).

2 (a) to 2 (e) show a method of manufacturing a conventional IPS mode liquid crystal display device.

3 (a) to 3 (g) show a method of manufacturing an IPS mode liquid crystal display device according to the present invention.

4 is a plan view showing the structure of an IPS mode liquid crystal display device according to the present invention;

5 is a plan view showing another structure of the IPS mode liquid crystal display device according to the present invention.

Explanation of symbols on main parts of drawing

103: gate line 104a: data line

105a: common electrode 107a: pixel electrode

110: thin film transistor 111a, 111b: gate electrode

112a: semiconductor layer 113: source electrode

114: drain electrode 120,130: substrate

122a, 122b: gate insulating layer

Claims (16)

A plurality of gate lines and data lines defining a plurality of pixels; A thin film transistor disposed in each pixel; At least one pair of common electrode and pixel electrode disposed in the pixel to form a transverse electric field; And And a first insulating layer having a data line disposed above and a side surface of the common electrode facing the data line below. The method of claim 1, wherein the thin film transistor, A gate electrode formed on the first substrate; A second insulating layer formed on the gate electrode; A semiconductor layer formed on the gate insulating layer; And The transverse electric field mode liquid crystal display device comprising a source electrode and a drain electrode formed on the semiconductor layer. The method of claim 2, wherein the gate electrode, Transparent conductive layer; And The transverse electric field mode liquid crystal display device comprising a metal layer formed on the transparent conductive layer. The transverse electric field mode liquid crystal display device of claim 2, wherein the common electrode and the pixel electrode are formed on a first substrate. The transverse electric field mode liquid crystal display device of claim 4, wherein the common electrode and the pixel electrode are formed of a transparent conductive layer. The transverse electric field mode liquid crystal display device of claim 2, further comprising a pad configured to apply a signal to the gate line and the data line. The transverse electric field mode liquid crystal display device of claim 6, wherein the pad is formed of a transparent conductive layer. The transverse electric field mode liquid crystal display device of claim 3, wherein the transparent conductive layer is made of indium tin oxide (ITO) or indium zinc oxide (IZO). The method of claim 1, Second substrate; A black matrix formed on the second substrate to block light from being transmitted to the image non-display area; And The transverse electric field mode liquid crystal display device further comprising a color filter layer for realizing color. A first step of forming a common electrode, a pixel electrode, and a pad forming a gate electrode, a gate line, and a transverse electric field on a first substrate using a first mask; A second step of forming a first insulating layer and a semiconductor layer on the gate electrode by using a second mask and forming a second insulating layer on a portion of the common electrode and on a side thereof; A third step of forming a source electrode and a drain electrode on the semiconductor layer using a third mask and forming a data line on a second insulating layer; And a fourth step of stacking a protective layer on the substrate and opening a pad. The method of claim 10, wherein the first step, Continuously laminating the transparent conductive layer and the metal layer over the entire first substrate; And Etching the transparent conductive layer and the metal layer by a photolithography method. The method of claim 11, wherein the transparent conductive layer is made of indium tin oxide (ITO) or indium zinc oxide (IZO). The method of claim 10, wherein the second step, Sequentially stacking an insulator and a semiconductor over the first substrate; And Etching the insulator and the semiconductor by a photolithography method. The method of claim 10, wherein the third step, Forming a metal layer over the first substrate; Stacking the photoresist on the metal layer and developing the photoresist pattern by a diffraction mask; And And forming a source electrode, a drain electrode, and a data line using the developed photoresist. The method of claim 14, wherein the forming of the source electrode, the drain electrode, and the data line comprises: Etching the metal layer using the photoresist pattern; Acing the photoresist pattern to expose a metal layer on the gate electrode; And Etching the metal layer over the gate electrode. The method of claim 10, wherein the fourth step includes exposing the gate insulating layer and the protective layer formed on the pad to plasma or to immerse in acid.