KR20050110725A - Plasma display panel - Google Patents

Abstract

According to the present invention, a plasma display panel is disclosed. The plasma display panel includes a transparent upper substrate, a lower substrate disposed parallel to the upper substrate, a first partition wall disposed between the upper substrate and the lower substrate, defining discharge cells together with the upper substrate and the lower substrate, and formed of a dielectric. And upper discharge electrodes disposed in the first partition wall to surround the discharge cells, extending in one direction, disposed in the first partition wall to surround the discharge cells, extending in parallel with the upper discharge electrodes, and spaced apart from the upper discharge electrodes. A predetermined width narrower than the width of one discharge cell is formed by embedding address electrodes and address electrodes which extend in a direction crossing the lower discharge electrodes, the upper discharge electrodes and the lower discharge electrodes, and are disposed below the upper substrate. And a discharge layer in the discharge cell. According to the disclosed plasma display panel, light transmittance and luminous efficiency are improved, and smooth addressing is possible at a low driving voltage.

Description

Plasma display panel {Plasma display panel}

The present invention relates to a plasma display panel that implements an image using gas discharge.

Recently, a device employing a plasma display panel as a flat panel display device has a large screen and has excellent characteristics of high definition, ultra-thin, light weight, and wide viewing angle, and is easier to manufacture than other flat panel display devices. It is attracting attention as a large flat panel display device.

The plasma display panel is classified into a direct current (DC) type, an alternating current (AC) type, and a hybrid type according to an applied discharge voltage, and classified into a counter discharge type and a surface discharge type according to a discharge structure. Recently, most plasma display panels produced at home and abroad are three-electrode surface discharge plasma display panels.

1 illustrates a conventional three-electrode surface discharge plasma display panel. The illustrated plasma display panel includes an upper substrate 11 and a lower substrate 21 disposed to face the upper substrate 11. Discharge sustaining electrode pairs 16 are disposed on the lower surface of the upper substrate 11, and the upper dielectric layer 14 and the protective film 15 covering the upper dielectric layer 14 are embedded in this order. Here, one electrode of the discharge sustaining electrode pair 16 is the scan electrode 12, the other electrode is the common electrode 13, and the scan electrode 12 and the common electrode 13 are transparent electrodes 12a and 13a, respectively. ) And bus electrodes 12b and 13b.

On the other hand, an upper surface of the lower substrate 21 is formed with an address electrode 22 extending to intersect with the discharge sustaining electrode pair 16 and a lower dielectric layer 23 embedded therein. A partition wall 24 is formed on the lower dielectric layer 23 to partition the plurality of discharge cells. The phosphor layer 25 is disposed on the lower dielectric layer 23 over the partition wall 24, and the space inside the discharge cell is filled with discharge gas.

In such a plasma display panel, plasma is formed by discharge performed by the discharge sustaining electrode pair 16, and the phosphor layer 25 is excited by vacuum ultraviolet rays emitted from the formed plasma to emit visible light, thereby realizing an image. do.

By the way, in the conventional three-electrode surface discharge structure shown in the drawing, while diverging visible light passes through the discharge sustaining electrode pair 16 formed on the lower side of the upper substrate 11, the upper dielectric layer 14, and the protective film 15, Visible light is absorbed by these structures, so there is a problem that the luminous efficiency is very low.

In addition, when the same image is displayed for a long time, there is a problem that the charged particles of the discharge gas strike the phosphor layer 25 and cause permanent afterimages.

An object of the present invention is to provide an improved plasma display panel in which the luminous efficiency and driving efficiency are improved and the degradation of the phosphor layer is prevented in order to solve the above and other problems.

Another object of the present invention is to provide a plasma display panel having an improved structure such that smooth addressing can be performed at a low driving voltage.

In order to achieve the above objects and other objects, the plasma display panel of the present invention,

Transparent upper substrate;

A lower substrate disposed in parallel with the upper substrate;

A first partition wall disposed between the upper substrate and the lower substrate and defining discharge cells together with the upper substrate and the lower substrate and formed of a dielectric;

Upper discharge electrodes disposed in a first partition wall to surround the discharge cells and extending in one direction;

Lower discharge electrodes disposed in a first partition wall to surround the discharge cell, extending in parallel with the upper discharge electrode, and spaced apart from an upper discharge electrode;

Address electrodes extending in a direction crossing the upper discharge electrodes and the lower discharge electrodes and disposed below the upper substrate;

Filling the address electrodes, wherein the dielectric layer has a predetermined width narrower than the width of one discharge cell;

A phosphor layer disposed in the discharge cell; And

And a discharge gas in the discharge cell.

The dielectric layer may be formed on an upper side of the first partition wall.

The address electrode may be formed to surround the inside of the discharge cell.

On the other hand, the plasma display panel according to another aspect of the present invention,

Transparent upper substrate;

A lower substrate disposed in parallel with the upper substrate;

A first partition wall disposed between the upper substrate and the lower substrate and defining discharge cells together with the upper substrate and the lower substrate and formed of a dielectric;

Upper discharge electrodes disposed in a first partition wall to surround the discharge cells and extending in one direction;

Lower discharge electrodes disposed in a first partition wall to surround the discharge cell, extending in parallel with the upper discharge electrode, and spaced apart from an upper discharge electrode;

Address electrodes extending in a direction crossing the discharge electrodes and disposed under the upper substrate;

A dielectric layer having a groove formed inside the discharge cell by filling the address electrode;

A phosphor layer disposed in the discharge cell; And

And a discharge gas in the discharge cell.

In the plasma display panel of the present invention, a second partition wall defining a discharge cell may be further provided together with the first partition wall. In this case, the phosphor layer is preferably disposed at the same level as the second partition wall.

In the plasma display panel of the present invention, the upper discharge electrodes and the lower discharge electrodes preferably have a ladder shape extending in one direction.

At least the side surface of the first partition wall is preferably covered with a protective film.

Next, the plasma display panel according to the first embodiment of the present invention will be described in detail with reference to FIGS. 2 to 5. 2 is an exploded perspective view illustrating a plasma display panel according to a first embodiment of the present invention, FIG. 3 is a cross-sectional view taken along line III-III of FIG. 2, and FIG. 4 is taken along line IV-IV of FIG. 3. Fig. 5 is a perspective view showing the electrode structure of the first embodiment. Referring to FIG. 2, the plasma display panel according to the present exemplary embodiment includes an upper substrate 111 and a lower substrate 121 disposed on a lower side thereof (as opposed to z). The upper substrate 111 and the lower substrate 121 are typically formed of a material mainly containing glass. In particular, when the upper substrate 111 is used as the image display surface, it is preferable that the upper substrate 111 is formed of a transparent substrate having excellent light transmittance. The upper substrate 111 and the lower substrate 121 define the discharge cells 130 in the vertical direction, where the discharge cells 130 are formed of one of red subpixels, green subpixels, and blue subpixels constituting one pixel. Subpixels. The discharge cell 130 is defined in the up and down direction by the upper substrate 111 and the lower substrate 121. The one discharge cell 130 of FIG. 3 is in the up and down direction from the lower surface of the upper substrate 111 to the lower substrate ( It means to include the area up to the top surface of 121, and more specifically, it includes the address electrode 122, the dielectric layer 123, the discharge space formed in the panel, the phosphor layer 125. .

As shown in FIG. 2, a first partition wall 114 is formed below the upper substrate 111. Prevent discharge. The first partition wall 114 illustrated in FIG. 4 may extend in the x and y directions to form a matrix. The first partition wall 114 of the present invention is not limited to such a matrix shape, but may also be an open partition wall such as a stripe or the like and a closed partition wall such as a waffle or a delta. The first partition wall 114 formed of a dielectric material prevents the upper discharge electrode 112 and the lower discharge electrode 113 from being directly energized during discharge and induces accumulation of wall charges. Dielectrics forming the first partition 114 include PbO, B ₂ O ₃ , SiO _2, and the like.

Referring to FIG. 2, the side surface of the first partition wall 114 is preferably covered by the protective film 115. The protective film 115 may be damaged when charged particles due to discharge collide with the first partition wall 114. To prevent a lot of secondary electrons. The protective film 115 may typically be formed of an MgO film.

An upper discharge electrode 112 and a lower discharge electrode 113 are embedded in the first partition wall 114. The upper discharge electrode 112 and the lower discharge electrode 113 are disposed to be spaced apart from each other in the vertical direction. The sustain discharge is performed by these discharge electrodes 112 and 113 to realize an image. Referring to FIG. 5, the upper discharge electrode 112 and the lower discharge electrode 113 are disposed in parallel to each other, and are formed in a ladder shape to surround four side surfaces of the discharge cell 130 and extend in the x direction. One of the discharge electrodes 112 and 113 serves as a scan electrode, and the other electrode serves as a common electrode. When the scan electrode is disposed adjacent to the address electrode 122, the address voltage can be lowered. In this embodiment, the upper discharge electrode 112 adjacent to the address electrode 122 acts as the scan electrode. The upper discharge electrode 112 and the lower discharge electrode 113 are formed of a metal material having excellent electrical conductivity, for example, Ag, Cu, Al, or the like. In the conventional plasma display panel, the discharge sustaining electrode pair is formed below the upper substrate, and the discharge sustaining electrode pair includes a transparent electrode such as ITO for the upward transmission of visible light. In the present invention, since the discharge electrodes 112 and 113 are disposed in the first partition wall 114, the discharge electrodes 112 and 113 may be formed of a metal electrode having excellent electrical conductivity. Therefore, the voltage drop caused by the electrode itself is minimized, driving efficiency and response speed are improved, and a uniform voltage can be applied to the discharge cells disposed at a relatively long distance from the point of application of the voltage.

Meanwhile, referring to FIG. 2, an address electrode 122 is disposed below the upper substrate 111, for example, on a lower surface of the upper substrate 111. The address electrodes 122 may be formed in a stripe pattern along the discharge cells 130 in one row (y direction). As shown in FIG. 5, the address electrodes 122 intersect with the extension directions (x directions) of the discharge electrodes 112 and 113. It extends in the direction (y direction). The address electrode 122 may be formed of a metal material having excellent electrical conductivity, for example, a metal electrode such as Ag, Cu, Al, or the like. However, when the address electrode 122 is formed of a metal electrode, since upward transmittance of visible light may decrease, it may be formed of a transparent electrode material, for example, a transparent electrode such as indium tin oxide (ITO). In this case, the address electrode 122 may be formed of only the transparent electrode, or the transparent electrode and the metal electrode may be used together to reinforce the electric conductivity.

The address electrode 122 is used to generate an address discharge for facilitating sustain discharge between the upper discharge electrode 112 and the lower discharge electrode 113. More specifically, the address electrode 122 serves to lower the voltage at which the sustain discharge starts. . The address discharge is a discharge occurring between the scan electrode and the address electrode 122. When the address discharge is completed, cations accumulate on the scan electrode side and electrons accumulate on the common electrode side, thereby making it easier to sustain discharge between the scan electrode and the common electrode. Done. In the conventional plasma display panel, an address electrode is formed below the phosphor layer, and there is a problem that the phosphor layer is deteriorated and the luminance characteristic is deteriorated due to the impact of the charged particles due to the address discharge, that is, ion sputtering. In the above, since the address electrode 122 is formed below the upper substrate 111, deterioration of the phosphor layer 125 can be prevented. In the conventional structure, the address discharge between the address electrode and the scan electrode is performed through the phosphor layer. However, in the present invention, the address discharge can be directly performed between the address electrode 122 and the scan electrode. Therefore, improvement in driving efficiency by electric field enhancement is expected. Can be.

As shown in FIG. 2, the address electrodes 122 are buried by the dielectric layer 123. The dielectric layer 123 damages the address electrode 122 because charged particles of the discharge gas collide directly with the address electrode 122. It is prevented from inducing and induces wall charge. Examples of the dielectric for forming the dielectric layer 123 include PbO, B ₂ O ₃ , and SiO ₂ . The dielectric layer 123 has a light transmittance of about 70% and about 30% of visible light is absorbed by the dielectric layer 123. As can be seen in FIG. 3, in the present invention, while covering the address electrode 122 with the dielectric layer 123 to protect the electrode, the width w2 of the dielectric layer 123 is greater than the width w1 of the one discharge cell 130. It is narrowly formed. 4, the region 100 in which the dielectric layer 123 is not formed is formed along both sides of the dielectric layer 123 extending in one direction (y direction) in the discharge cell 130. This is to minimize the light efficiency of the plasma display panel. The width of the region is the sum of d1 and d2, which are the width w2 of the dielectric layer 123 at the width w1 of the discharge cell 130 defined by the first partition wall 114.

Meanwhile, referring to FIG. 2, a second partition wall 124 is formed on the lower substrate 121. The second partition 124 together with the first partition 114 defines a side surface of the discharge cell 130. In the embodiment of Figure 2, it is formed in a matrix shape extending in the x direction and the y direction. The second partition wall 124 of the present invention can be formed in a variety of structures other than such a matrix shape, for example, as well as an open partition structure of a stripe pattern, formed of a closed partition structure such as waffle, delta type. May be

The phosphor layer 125 is formed at the same level as the second barrier 124, which means that the phosphor layer 125 is disposed at the same height as the second barrier 124. More specifically, in the present embodiment, the phosphor layer 125 is disposed on the lower substrate 121 surrounded by the second partition wall 124 over the side surface of the second partition wall 124. The phosphor layer 125 receives vacuum ultraviolet rays emitted from the plasma generated by the discharge and converts the visible rays into visible light. In the present invention, since the address electrode 122 is disposed below the upper substrate 111, even if the height of the phosphor layer 125, that is, the height of the second partition wall 124, there is no effect on addressing. Therefore, by increasing the height of the phosphor layer 125, it is possible to increase the luminous efficiency.

Each of the discharge cells 130 is divided into a red light emitting subpixel, a green light emitting subpixel, and a blue light emitting subpixel according to the type of the phosphor layer 125 disposed. The phosphor layer formed on the red light emitting subpixel may include phosphors such as Y (V, P) O ₄ : Eu, and the like, and the phosphor layer 25 formed on the green light emitting subpixel includes Zn ₂ SiO ₄ : Mn, YBO ₃ : It may include a phosphor such as Tb, and the phosphor layer 25 formed in the blue light emitting subpixel may include a phosphor such as BAM: Eu.

The discharge cells 130 are filled with discharge gases such as Ne, Xe, and the like and mixed gases thereof. In the present invention including this embodiment, the discharge surface can be increased and the discharge region can be enlarged, so that the amount of plasma formed is increased, thereby enabling low voltage driving. Therefore, in the case of the present invention, even when a high concentration of Xe gas is used as the discharge gas, low voltage driving is possible, thereby significantly improving the luminous efficiency. This solves the problem of low voltage driving when using a high concentration of Xe gas as a discharge gas in a conventional plasma display panel.

Referring to FIG. 3, in the plasma display panel according to the first exemplary embodiment of the present invention, the address discharge is caused by applying an address voltage between the address electrode 122 and the upper discharge electrode 112. As a result of this address discharge, the discharge cells 130 in which sustain discharge is to be generated are selected.

Thereafter, when a sustain discharge voltage of AC is applied between the upper discharge electrode 112 and the lower discharge electrode 113 of the selected discharge cell 130, the sustain discharge is discharged between the upper discharge electrode 112 and the lower discharge electrode 113. This happens. Ultraviolet rays are emitted while the energy level of the discharged gas excited by this sustain discharge is lowered. The ultraviolet rays excite the phosphor layer 125 coated in the discharge cell 130. As the energy level of the excited phosphor layer 125 decreases, visible light is emitted, and the emitted visible light forms an image. .

In the conventional plasma display panel shown in Fig. 1, the sustain discharge between the scan electrode 12 and the common electrode 13 occurs in the horizontal direction, so that the discharge area is relatively narrow. However, since the sustain discharge of the plasma display panel according to the present embodiment occurs in the vertical direction in all aspects defining the discharge cell 130, there is an advantage that the discharge area is relatively large.

In addition, the sustain discharge in this embodiment is formed in a closed curve along the side of the discharge cell 130 and gradually diffuses to the center portion of the discharge cell (130). As a result, the volume of the region in which the sustain discharge occurs is increased, and the space charge in the discharge cell 130 which is not well used in the past also contributes to light emission. Such matters result in the improvement of the luminous efficiency of the plasma display panel.

In addition, in the plasma display panel according to the present embodiment, as shown in FIG. 3, since the sustain discharge is performed only at the portion defined by the first partition wall 114, the phosphor layer by the charged particles, which has been a problem of the conventional plasma display panel. Ion sputtering of 125 is prevented, and thus there is an advantage that a permanent afterimage does not occur even if the same image is displayed for a long time. In particular, in the present invention, since the address electrode 122 is not disposed below the phosphor layer 125 but disposed below the upper substrate 111, ion sputtering due to address discharge is fundamentally prevented. It is possible to prevent deterioration of the layer 125 and to thereby improve luminance characteristics.

6 to 9 illustrate a plasma display panel according to a second embodiment of the present invention. FIG. 6 is an exploded perspective view, FIG. 7 is a sectional view taken along the line VII-VII of FIG. 6, and FIG. 8 is a view of FIG. 7. Fig. 9 is a sectional view taken along the line VII-VII, and is a perspective view showing an electrode arrangement state of the second embodiment. Hereinafter, a description will be given focusing on differences from the first embodiment.

The plasma display panel according to the present embodiment includes an upper substrate 211 and a lower substrate 221 disposed to face the first substrate 211, and between the upper substrate 211 and the lower substrate 221, the first partition wall 214 and the second substrate. The partition wall 224 is disposed to partition the discharge cell 230. The upper discharge electrode 212 and the lower discharge electrode 213 are buried in the first partition 214 so as to be spaced apart from each other up and down, and an address electrode 222 is disposed below the upper substrate 211. In this embodiment, the address electrodes 222 are not arranged in a row in the center of the discharge cells 230, but are disposed at the edges of the discharge cells 230 so as to surround the inside of one discharge cell. This means that the discharge plane between the scan electrodes, for example, the upper discharge electrode 212 and the address electrode 222 is increased, and as compared with the case where the address electrodes 222 are arranged in one row, a lower address voltage is obtained. Even when applied, the equivalent wall charge accumulation effect can be achieved. As shown in FIG. 7, the address electrode 222 is disposed at the inner edge of the discharge cell 230, thereby being disposed adjacent to the scan electrode, for example, the upper discharge electrode 212. By shortening the discharge distance between the scan electrode and the address electrode 222, the address discharge by the electric field strengthening can be promoted, the discharge surface can be increased, and the address driving at low voltage can be performed.

The address electrode 222 is filled by the dielectric layer 223. As shown in FIGS. 7 and 8, the dielectric layer 223 is formed along the address electrode 222. In order to minimize the light loss caused by the dielectric layer 223, the width w2 + w3 of the dielectric layer 223 is formed to be narrower than the width w1 of the discharge cell 230. This means that there is a region 200 in which the dielectric layer 223 is not formed in the center portion and the edge portion of the discharge cell 230. In this region 200, the upper transmittance of visible light is improved to improve the plasma display panel. The light efficiency of the is improved. However, in the present embodiment, the width w1 + w2 of the dielectric layer 223 is the sum of the dielectric layer widths w1 + w2 of this column disposed in one discharge cell 130, and the dielectric layer 223 is not formed. The width of the non-existing region 200 becomes the limit value d1 + d2 + d3 of the width w2 + w3 of the dielectric layer 223 at the width w1 of the one discharge cell 230.

In addition, the matters concerning the protective film 215 and the phosphor layer 225 are substantially the same as those of the first embodiment.

10 and 11 show a plasma display panel according to a third embodiment of the present invention. FIG. 10 is an exploded perspective view and FIG. 11 is a cross-sectional view taken along line XI-XI of FIG. 10. Hereinafter, description will be made focusing on differences from the first embodiment. In the lower surface of the upper substrate 311, the address electrodes 322 are formed in a stripe pattern along the discharge cells 330 arranged in one row (y direction), and the dielectric layer 323 fills the address electrodes 322. Is formed. Also in this embodiment, the width w2 of the dielectric layer 323 is formed to be narrower than the width w1 of one discharge cell 330. In the present embodiment, unlike the first embodiment, the dielectric layer 323 is also formed on the upper surface 314a of the first partition wall 314. The dielectric layer 323 of the present embodiment may be formed by stacking the dielectric layer 323 on the entire upper substrate 311 and etching a predetermined portion. The width of the etched predetermined portion is d1 + d2.

12 and 13 illustrate a plasma display panel according to a fourth embodiment of the present invention. 12 is an exploded perspective view, and FIG. 13 is a cross-sectional view taken along the line XIII-XIII of FIG. 12. Also in this embodiment, the address electrodes 422 are formed in a stripe pattern on the lower surface of the upper substrate 411 so as to extend over the discharge cells 430 in one row (y direction). In this embodiment, the dielectric layer 423 filling the address electrode 422 is formed over the entire surface of the lower surface of the upper substrate 411. A groove 400 is formed in the dielectric layer 423, and the groove 400 may be formed by etching a predetermined portion of the dielectric layer 423. As shown in FIG. 13, the groove 400 may be formed inside the discharge cell 430, specifically, on both sides of the address electrode 422. The widths of the grooves 400 are d1 and d2, respectively. When the thickness of the dielectric layer 423 through which the visible light is transmitted decreases, the light transmittance increases, so that a predetermined portion of the dielectric layer 423 is etched to increase the upward transmittance of the visible light. In FIG. 13, reference numeral t1 denotes the thickness of the dielectric layer 423 stacked on the lower surface of the upper substrate 411, and reference numeral t2 denotes the thickness of the dielectric layer 423 of the etched portion.

In addition, the upper substrate 411, the lower substrate 421, the first partition 414, the second partition 424, the phosphor layer 425, the protective film 415, the upper discharge electrode 412, the lower discharge electrode ( 413) may be referred to the first embodiment.

Meanwhile, in the drawings attached to the present specification, partition walls defining side surfaces of the discharge cells are illustrated to be separated up and down, but the present invention is not limited thereto, and the partition walls may be applied to a case where the partition walls are integrally formed. .

According to the plasma display panel according to the present invention, the following effects can be obtained.

First, light transmittance and luminous efficiency of the plasma display panel are improved. In the plasma display panel of the present invention, the light transmittance of visible light is improved by forming the dielectric layer in the minimum range for electrode protection while protecting the address electrode with the dielectric layer. In addition, the address electrode of the present invention is disposed on the upper side of the phosphor layer rather than on the lower side, and thus, the light emitting efficiency can be improved by increasing the height of the phosphor layer.

Second, addressing is possible with a low address voltage. In the plasma display panel of the present invention, an address electrode is disposed below the upper substrate so that address discharge is performed without passing through the phosphor layer. Therefore, addressing can be performed smoothly even with a low voltage address voltage.

Third, deterioration of the phosphor layer is prevented. Since the address electrode of the present invention is not disposed below the phosphor layer, but disposed above, the ion sputtering due to the address discharge can be prevented. Thus, the luminance characteristics of the plasma display panel are improved, and the lifespan is improved.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is an exploded perspective view showing a conventional plasma display panel;

2 is an exploded perspective view showing a plasma display panel according to a first embodiment of the present invention;

3 is a cross-sectional view taken along line III-III of FIG. 2,

4 is a cross-sectional view taken along line IV-IV of FIG. 3,

5 is a perspective view illustrating an electrode structure of the plasma display panel of FIG. 2;

6 is an exploded perspective view showing a plasma display panel according to a second embodiment of the present invention;

7 is a cross-sectional view taken along the line VII-VII of FIG. 6,

8 is a cross-sectional view taken along the line VII-VII of FIG. 7;

9 is a perspective view illustrating an electrode structure of the plasma display panel of FIG. 6;

10 is an exploded perspective view showing a plasma display panel according to a third embodiment of the present invention;

FIG. 11 is a cross-sectional view taken along the line XI-XI of FIG. 10;

12 is an exploded perspective view showing a plasma display panel according to a fourth embodiment of the present invention;

FIG. 13 is a cross-sectional view taken along the line XIII-XIII of FIG. 12.

<Description of Symbols for Major Parts of Drawings>

111,211,311,411: upper substrate 112,212,312,412: upper discharge electrode

113,213,313,413: lower discharge electrode 114,214,314,414: first bulkhead

115,215,315,415: Protective film 121,221,321,421: Lower substrate

122, 222, 322, 422: address electrode 123, 223, 323, 423: dielectric layer

124,224,324,424: second bulkhead 125,225,325,425: phosphor layer

      130,230,330,430: discharge cell

Claims (6)

Transparent upper substrate; A lower substrate disposed in parallel with the upper substrate; A first partition wall disposed between the upper substrate and the lower substrate and defining discharge cells together with the upper substrate and the lower substrate and formed of a dielectric; Upper discharge electrodes disposed in a first partition wall to surround the discharge cells and extending in one direction; Lower discharge electrodes disposed in a first partition wall to surround the discharge cell, extending in parallel with the upper discharge electrode, and spaced apart from an upper discharge electrode; Address electrodes extending in a direction crossing the upper discharge electrodes and the lower discharge electrodes and disposed below the upper substrate; Filling the address electrodes, wherein the dielectric layer has a predetermined width narrower than the width of one discharge cell; A phosphor layer disposed in the discharge cell; And And a discharge gas in the discharge cell. The plasma display panel of claim 1, wherein the dielectric layer is formed on an upper side of the first partition wall. The plasma display panel of claim 1, wherein the address electrode is formed to surround the inside of the discharge cell. Transparent upper substrate; A lower substrate disposed in parallel with the upper substrate; A first partition wall disposed between the upper substrate and the lower substrate and defining discharge cells together with the upper substrate and the lower substrate and formed of a dielectric; Upper discharge electrodes disposed in a first partition wall to surround the discharge cells and extending in one direction; Lower discharge electrodes disposed in a first partition wall to surround the discharge cell, extending in parallel with the upper discharge electrode, and spaced apart from an upper discharge electrode; Address electrodes extending in a direction crossing the discharge electrodes and disposed under the upper substrate; A dielectric layer having a groove formed inside the discharge cell by filling the address electrode; A phosphor layer disposed in the discharge cell; And And a discharge gas in the discharge cell. The method according to claim 1 or 4, And a second partition wall defining a discharge cell together with the first partition wall. And the phosphor layer is disposed at the same level as the second partition wall. The method according to claim 1 or 4, The upper discharge electrodes and the lower discharge electrodes have a ladder shape extending in one direction, And at least a side surface of the first partition wall is covered by a protective film.