KR20050104605A - Light emitting display - Google Patents

Abstract

The present invention provides a light emitting display device having an arrangement structure in which a pixel circuit can be efficiently arranged in a pixel region.

In the light emitting display device according to the present invention, first, second, and third light emitting devices that emit light based on an applied current are arranged in a pixel area where a pixel circuit is disposed. In the pixel region, first and second conductive layers substantially symmetrically disposed with respect to the semiconductor layer region electrically connected to the pixel circuit of the second light emitting device through the contact hole, and the first and second conductive layers. The third and fourth conductive layers which are insulated from each other and overlap each other are disposed. That is, the first conductive layer and the third conductive layer form one capacitor, the second conductive layer and the fourth conductive layer form the other capacitor, and the two capacitors are arranged symmetrically with each other.

Description

Light emitting display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting display device, and more particularly, to an organic EL display device using electroluminescence of an organic material (hereinafter referred to as "organic EL").

In general, an organic EL display device is a display device for electrically exciting a fluorescent organic compound to emit light. An organic EL display device displays an image by driving N × M organic light emitting elements arranged in a matrix form.

Since the organic light emitting diode has a diode characteristic, it is also called an organic light emitting diode (OLED) and has a structure of an anode (ITO), an organic thin film, and a cathode electrode layer (metal). The organic thin film has a multilayer structure including an emitting layer (EML), an electron transport layer (ETL), and a hole transport layer (HTL) to improve the emission efficiency by improving the balance between electrons and holes. It also includes a separate electron injecting layer (EIL) and a hole injecting layer (HIL). These organic light emitting diodes are arranged in an N × M matrix to form an organic EL display panel.

The organic EL display panel is driven by a simple matrix method and an active matrix method using a thin film transistor (hereinafter, referred to as TFT). In the simple matrix method, the anode and the cathode are orthogonal and the line is selected and driven, whereas the active driving method drives the organic EL device by sequentially turning on a plurality of thin film transistors connected to the data line and the scan line according to the scan selection signal. That's the way it is.

Hereinafter, a pixel circuit of a general active driving organic EL display device will be described.

FIG. 1 is an equivalent circuit diagram of one pixel of N × M pixels, that is, a pixel located in a first row and a first column.

As shown in FIG. 1, one pixel 10 is formed of three subpixels 10r, 10g, and 10b, and red (R) and green (G) are respectively present in the subpixels 10r, 10g, and 10b. And organic EL elements OLEDr, OLEDg, and OLEDb that emit light of blue (B). In the structure in which the subpixels are arranged in a stripe shape, the subpixels 10r, 10g, and 10b are connected to the separate data lines D1r, D1g, and D1b and the common scan line S1, respectively.

The red subpixel 10r includes two transistors M1r and M2r and a capacitor C1r for driving the organic EL element OLEDr. Similarly, the green subpixel 10g includes two transistors M1g and M2g and a capacitor C1g, and the blue subpixel 10b also includes two transistors M1b and M2b and a capacitor C1b. . Since the operations of these subpixels 10r, 10g, and 10b are all the same, one subpixel 10r will be described below as an example.

The driving transistor M1r is connected between the power supply voltage VDD and the anode of the organic EL element OLEDr to transfer a current for light emission to the organic EL element OLEDr, and the cathode of the organic EL element OECDr is the power supply voltage. It is connected to a voltage VSS lower than VDD. The amount of current in the driving transistor M1r is controlled by the data voltage applied through the switching transistor M2r. At this time, the capacitor C1r is connected between the source and the gate of the transistor M1r to maintain the applied voltage for a predetermined period. A scan line S1 for transmitting an on / off selection signal is connected to a gate of the transistor M2r, and a data line D1r for transmitting a data voltage corresponding to the red subpixel 10r is connected to a source side thereof. have.

Referring to the operation, when the switching transistor M2r is turned on in response to the selection signal applied to the gate, the data voltage V _DATA from the data line D1r is applied to the gate of the transistor M1r. Then, the current I _OLED flows through the transistor M1r in response to the voltage V _GS charged between the gate and the source by the capacitor C1r, and the organic EL element OLEDr corresponds to the current I _OLED . Emits light. At this time, the current I _OLED flowing through the organic EL device OLEDr is represented by Equation 1 below.

Here, V _TH represents a threshold voltage of the transistor M2r, and β represents a constant value.

As shown in Equation 1, in the pixel circuit shown in Fig. 1, a current corresponding to the data voltage is supplied to the organic EL element OLEDr, and the organic EL element OLEDr emits light at a luminance corresponding to the supplied current. do. In this case, the applied data voltage has a multi-level value in a predetermined range in order to express a predetermined gray level.

As described above, in the organic EL display device, one pixel 10 includes three subpixels 10r, 10g, and 10b, and a driving transistor, a switching transistor, and a capacitor for driving the organic EL element are formed for each subpixel. In addition, a data line for transmitting a data signal and a power supply line for transmitting a power supply voltage VDD are formed for each subpixel.

Therefore, there is a need for a large number of transistors, capacitors and voltages or wirings for transmitting signals or signals formed in one pixel, and it is difficult to arrange them all within the pixel, and also reduces the aperture ratio corresponding to the light emitting area of the pixel. There is this.

SUMMARY OF THE INVENTION An object of the present invention is to provide a light emitting display device having an efficient arrangement of pixel regions.

In order to achieve the above technical problem, a light emitting display device according to an aspect of the present invention includes a plurality of scan lines extending in a first direction and transmitting a selection signal, insulated from and intersecting the scan lines and extending in a second direction. A light emitting display device in which a plurality of data lines transferring a signal and a plurality of pixel circuits connected to the scan line and the data line, respectively, are arranged in an array form.

First, second and third light emitting devices each having a pixel electrode to which a current is applied and emitting light based on the current applied to the pixel area where the pixel circuit is disposed; The first semiconductor layer region contacting the pixel electrode of the first light emitting device through the first contact hole, the second semiconductor layer region contacting the pixel electrode of the second light emitting device through the second contact hole and the third light emitting device. A first semiconductor layer including a third semiconductor layer region in contact with the pixel electrode through a third contact hole; First and second conductive layers disposed substantially symmetrically with respect to the second semiconductor layer region; And third and fourth conductive layers insulated from and overlapping each of the first and second conductive layers and disposed substantially symmetrically with respect to the second semiconductor layer region.

At least a portion of the first, second and third semiconductor layer regions may be disposed in parallel with the data lines, respectively, or may be insulated from and intersect with at least a portion of the second semiconductor layer region in the pixel region to form the third portion. And a fifth conductive layer connecting the fourth conductive layer.

Each of the first and second conductive layers may be a semiconductor layer doped with a specific type of impurity.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification. When a part is connected to another part, this includes not only a directly connected part but also a case where another part is connected in between. Also, when a part of a layer, film, region, plate, etc. is over another part, this includes not only when the other part is "right over" but also another part in the middle.

On the other hand, when the term for the scan line is defined, the scan line to which the current selection signal is to be transmitted is referred to as the "current scan line", and the scan line to which the selection signal is transmitted before the current selection signal is transmitted is referred to as the "previous scan line".

Also, a pixel that emits light based on the selection signal of the current scan line is referred to as a "current pixel", and a pixel that emits light based on the selection signal of the previous scan line is "previous pixel" and a pixel that emits light based on the selection signal of the next scan line is " Next pixel ".

2 is a diagram schematically illustrating a configuration of an organic EL display device according to an exemplary embodiment of the present invention.

As shown in FIG. 2, an organic EL display device according to an exemplary embodiment of the present invention includes a display panel 100, a scan driver 200, a light emission controller 300, and a data driver 400. The display panel 100 includes a plurality of scan lines S0, S1, ..., Sk, ..., Sn, light emission control lines E1, ..., Ek, ..., En that extend in a row direction, and a plurality of scan lines that extend in a column direction. Data lines D1, ..., Dk, ..., Dm, a plurality of power lines VDD, and a plurality of pixels 110 are included. The pixel 110 is formed in a pixel region formed by any two neighboring scan lines Sk-1 and Sk and any two neighboring data lines Dk-1 and Dk, and each pixel 110 is currently present. It is driven by signals transmitted from the scan line Sk, the immediately preceding scan line Sk-1, the light emission control line Ek, and the data line Dk. Although not shown in Fig. 2, the light emission control lines E1 to En each consist of three light emission control lines E1r to Enr, E1g to Eng, and E1b to Enb.

The scan driver 200 sequentially transmits a selection signal for selecting the corresponding line to the scan lines S0 to Sn so that the data signal can be applied to the pixels of the corresponding line, and the emission controller 300 transmits the organic EL element OLEDr. The light emission control signals for controlling the light emission of the OLEDg and the OLEDb are sequentially transmitted to the light emission control lines E1 to En. Each time the selection signal is sequentially applied, the data driver 400 applies a data signal corresponding to the pixel of the line to which the selection signal is applied to the data lines D1 to Dm.

The scan driver, the light emission controllers 200 and 300, and the data driver 400 are electrically connected to the substrate on which the display panel 400 is formed. Alternatively, the scan driver 200, the emission controller 300, and / or the data driver 400 may be directly mounted on the glass substrate of the display panel 100, and the scan line and the data line may be mounted on the substrate of the display panel 100. And a driving circuit formed of the same layers as the transistor. Alternatively, a tape carrier package (TCP), a flexible printed circuit (FPC), or a TAB may be bonded to the scan driver 200, the light emission controller 300, and / or the data driver 400 to be electrically connected to a substrate of the display panel 100. tape automatic bonding) can be installed in the form of chips.

At this time, in the embodiment of the present invention, one field is divided into three subfields and driven. In each of the three subfields, red, green, and blue data are written to emit light. To this end, the scan driver 200 sequentially transmits a selection signal to the scan lines S0 to Sn for each subfield, and the emission controller 300 also emits light so that the organic EL elements of each color emit light in one subfield. The control signal is applied to the emission control lines E1 to En. The data driver 400 applies data signals corresponding to the red, green, and blue organic EL elements in the three subfields to the data lines D1 to Dm, respectively.

Next, a detailed operation of the organic EL display device according to the exemplary embodiment of the present invention will be described in detail with reference to FIG. 3.

3 is an equivalent circuit diagram of one pixel 110 in the organic EL display device of FIG. 2. In FIG. 3, for convenience, the pixel Pk connected to the scan line Sk of an arbitrary kth row and the data line Dk of the kth column is illustrated as an example, and all transistors are illustrated as p-channel transistors.

As shown in FIG. 3, a pixel circuit according to an exemplary embodiment of the present invention includes a driving transistor M1, a diode transistor M3, a capacitor transistor M4, a switching transistor M2, and three organic EL elements OLEDr and OLEDg. , OLEDb) and light emitting transistors M2r, M2g, and M2b for controlling light emission of the organic EL elements OLEDr, OLEDg, and OLEDb, respectively, and include two capacitors Cst and Cvth. One emission control line Ek includes three emission control lines Ekr, Ekg, and Ekb. The light emitting transistors M2r, M2g, and M2b receive current from the driving transistor M1 in response to the light emission control signals transmitted by the light emission control lines Ekr, Ekg, and Ekb, and the organic EL elements OLEDr, OLEDg, and OLEDb. Optionally pass in

Specifically, the transistor M5 has a data voltage applied from the data line Dk in response to a selection signal from the scan line Sk with a gate connected to the current scan line Sk and a source connected to the data line Dk. Is transferred to the node B of the capacitor Cvth. Transistor M4 directly connects node B of capacitor Cvth to power source VDD in response to a selection signal from immediately preceding scan line Sk-1. Transistor M3 diode-connects transistor M1 in response to a selection signal from immediately preceding scan line Sk-1. The driving transistor M1 is a driving transistor for driving the organic EL element OLED, the gate of which is connected to the node A of the capacitor Cvth, the source of which is connected to the power source VDD, and to a voltage applied to the gate. By controlling the current to be applied to the organic EL element (OLED).

In addition, the capacitor Cst has one electrode connected to the power supply VDD, the other electrode connected to the drain electrode (node B) of the transistor M4, and the capacitor Cvth has one electrode connected to the other electrode of the capacitor Cst. Two capacitors are connected in series, and the other electrode is connected to the gate (node A) of the driving transistor M1.

Sources of the light emitting transistors M2r, M2g, and M2b are connected to drains of the driving transistor M1, and light emission control lines Ekr, Ekg, and Ekb are connected to gates of the transistors M2r, M2g, and M2b, respectively. . The anodes of the organic EL elements OLEDr, OLEDg, and OLEDb are connected to the drains of the light emitting transistors M2r, M2g, and M2b, respectively. The cathode of the organic EL elements OLEDr, OLEDg, and OLEDb has a power supply lower than the power supply voltage VDD. The voltage VSS is applied. As the power supply voltage VSS, a negative voltage or a ground voltage may be used.

When a low level scan voltage is applied to the immediately preceding scan line Sk-1, the transistors M3 and M4 are turned on. Transistor M3 is turned on so that transistor M1 is in a diode-connected state. Therefore, the voltage difference between the gate and the source of the transistor M1 changes until the threshold voltage Vth of the transistor M1 becomes. At this time, since the source of the transistor M1 is connected to the power supply VDD, the voltage applied to the gate of the transistor M1, that is, the node A of the capacitor Cvth, is the power supply voltage VDD and the threshold voltage Vth. Is the sum of. In addition, since the transistor M4 is turned on and the power supply VDD is applied to the node B of the capacitor Cvth, the voltage V _Cvth charged in the capacitor _Cvth is expressed by Equation 2 below.

Here, V _Cvth is the voltage applied to the node (B) of the voltage applied to the node (A) of a voltage that is charged in the capacitor (Cvth), and, V _CvthA a capacitor (Cvth), V _CvthB a capacitor (Cvth) Means.

When the low level scan voltage is applied to the current scan line Sn, the transistor M5 is turned on to apply the data voltage Vdata to the node B. In addition, since the capacitor Cvth is charged with a voltage corresponding to the threshold voltage Vth of the transistor M1, the gate of the transistor M1 is charged with the data voltage Vdata and the threshold voltage Vth of the transistor M1. The voltage corresponding to the sum is applied. That is, the gate-source voltage Vgs of the transistor M1 is expressed by Equation 3 below. At this time, the low-level signal is applied to the emission control line Ek so that the transistor M2 is cut off.

Then, in response to the high level of the light emission control line Ek, the transistor M2 is turned on so that the current I _OLED corresponding to the gate-source voltage V _GS of the transistor M1 is the organic EL element OLED. Supplied to the OLED, the organic EL element OLED emits light. The current I _{OLED is} shown in Equation 4.

Where I _OLED is the current flowing through the organic EL element OLED, Vgs is the voltage between the source and gate of transistor M1, Vth is the threshold voltage of transistor M1, Vdata is the data voltage, and β is a constant value. .

When the data voltage Vdata is a red data signal, when the light emitting transistor M2r is turned on in response to a low level light emission control signal from the light emission control line Ekr, this current I _OLED is a red organic EL element. It is transmitted to the OLEDr to emit light.

Similarly, when the data voltage Vdata is a green data signal, when the light emitting transistor M2g is turned on in response to a low level light emission control signal from the light emission control line Ekg, the current I _OLED is a green organic EL. The light is transmitted to the device OLEDg. In addition, when the data voltage Vdata is a blue data signal, when the light emitting transistor M2b is turned on in response to a low level light emission control signal from the light emission control line Ekb, the current I _OLED becomes a blue organic EL. The light is transmitted to the device OLEDb. The three emission control signals respectively applied to the three emission control lines have low level periods that do not overlap for one field so that one pixel can display red, green, and blue colors.

Next, referring to FIGS. 4, 5, and 6, the arrangement structure of the pixel region in which one pixel circuit is arranged in the organic EL display device according to the exemplary embodiment of the present invention will be described in detail. In the following description, reference numerals are given to components of the current pixel Pk, and reference numerals of components of the immediately preceding pixel Pk-1 are denoted by the same reference numerals as those of the components of the current pixel Pk. ') Is further indicated to distinguish the components of the current pixel from those of the direct telephone.

4 is a plan view illustrating an example of an arrangement structure of a pixel region in which the pixel circuit illustrated in FIG. 3 is disposed, FIG. 5 is a cross-sectional view of a portion II ′ of FIG. 4, and FIG. 6 is a II-II of FIG. 4. It is a cross section of the part.

First, as shown in FIGS. 4, 5, and 6, a blocking layer 3 made of silicon oxide or the like is formed on the insulating substrate 1, and a polysilicon layer, which is a semiconductor layer, is formed on the blocking layer 3. (21, 22, 23, 24, 25, 26, 27, 28, 29) are formed.

The polysilicon layer 21 has a 'U' shape to form a semiconductor layer including a source region, a drain region, and a channel region of the transistor M5 of the current pixel Pk. Polycrystalline silicon layer 22 is approximately ' The semiconductor layer including the source region, the drain region, and the channel region of the transistor M2r of the current pixel Pk is formed in a 'shape. The polysilicon layer 23 extends in the column direction to form a semiconductor layer including a source region, a drain region, and a channel region of the transistor M2g of the current pixel Pk. Polycrystalline silicon layer 24 is approximately ' The semiconductor layer including the source region, the drain region, and the channel region of the transistor M2b of the current pixel Pk is formed in a 'shape. The polycrystalline silicon layers 22, 23, and 24 are integrally connected to form an 'm' shape, and the polycrystalline silicon layer 22 and the polycrystalline silicon layer 24 are approximately symmetrical with respect to the polycrystalline silicon layer 23. do.

The polycrystalline silicon layer 25 extends in the column direction at the center of the pixel region, and the bottom end touches the portion where the polycrystalline silicon layers 22, 23, and 24 are connected to one, and thus the polycrystalline silicon layer 22, 23, and 24. Is formed in connection with The left side polycrystalline silicon layer 26 and the right side polycrystalline silicon layer 27 are formed approximately symmetrically with respect to the polycrystalline silicon layer 25. The polycrystalline silicon layer 26 forms one electrode (node A) of the capacitor Cvth in a substantially square shape, and the polycrystalline silicon layer 27 forms one electrode of the capacitor Cst in an approximately rectangular shape. The polysilicon layer 28 is formed to have an approximately 'n' shape, and one end thereof is connected to the polycrystalline silicon layer 26 and the other end thereof is connected to the polycrystalline silicon layer 25 to form a source and a drain of the transistor M3. And a channel region. The polysilicon layer 29 is formed to have an approximately 'n' shape and extends at one end to contact the polysilicon layer 28 so that the channel region and the drain region of the transistor M1 and the source region and channel region of the transistor M4 are formed. And a drain region.

The gate insulating film 30 is formed on the polycrystalline silicon layers 21 to 29 formed as described above.

Gate electrodes 41, 42, 43, 44, 45, 46, and 47 are formed on the gate insulating layer 30. Specifically, since the gate electrode line 41 extends in the row direction and corresponds to the current scan line Sk of the current pixel Pk, the gate electrode line 41 is insulated from and crosses the polycrystalline silicon layer 21 to be insulated from the transistor M5 of the current pixel Pk. A gate electrode is formed. The gate electrode line 42 extends in the row direction and corresponds to the light emission signal line Ekb of the current pixel Pk, thereby forming the gate electrode of the transistor M2b. The gate electrode line 43 extends in the row direction and corresponds to the light emission signal line Ekg of the current pixel Pk, thereby forming the gate electrode of the transistor M2g. The gate electrode line 44 extends in the row direction and corresponds to the light emission signal line Ekr of the current pixel Pk, thereby forming the gate electrode of the transistor M2k. The gate electrode lines 45 cross each other insulated from the polysilicon layer 26 in a rectangular shape to form a gate electrode of the transistor M1. The gate electrode 46 is formed in a substantially square shape on the polycrystalline silicon layer 26 to form the other electrode (node B) of the capacitor Cvth. The gate electrode 47 is formed in connection with the gate electrode 46 and is formed in a substantially rectangular shape on the polycrystalline silicon layer 27 to form the other electrode (node B) of the capacitor Cst.

Since the gate electrode line 41 'extends in the row direction and corresponds to the immediately preceding scan line Sk-1 of the immediately preceding pixel Pk-1, the gate electrode line 41' is insulated from and crosses the polycrystalline silicon layer 21 'so that The gate electrode of the transistor M5 is formed. The gate electrode line 41 'is insulated from and intersected with the polycrystalline silicon layers 28 and 29 to form the gate electrodes of the transistors M3 and M4 of the current pixel Pk.

The interlayer insulating film 50 is formed on the gate electrodes 41, 42, 43, 44, 45, 46, and 47. The data line 61 and the power line 62 are disposed on the interlayer insulating layer 50 so as to contact the electrodes through the contact holes 51a, 51b, 53, 54a, 54b, 55, 56a, 56b, 57r, 57g and 57b. ) And electrodes 63, 64, 65, 66r, 66g, 66b are formed.

The data line 61 extends in the column direction between the pixel region and another pixel region and is connected to the polysilicon layer 21 through a contact hole 51a penetrating through the interlayer insulating film 50 and the gate insulating film 30. Is electrically connected to a source of transistor M4.

The power line 62 extends in the column direction and is connected to the polycrystalline silicon layer 27 and the polycrystalline silicon layer 29 through a contact hole 55 passing through the interlayer insulating film 50 and the gate insulating film 30. Power is supplied to the one electrode of Cst and the source of the transistor M1.

The electrode 63 is formed in parallel with the data line 61 and is formed in parallel with the contact hole 51b penetrating the interlayer insulating film 50 and the gate insulating film 30 and the contact hole 53 penetrating the interlayer insulating film 50. The drain region of the polysilicon layer 21 and the gate electrode 46 are electrically connected to each other to form a node B.

The electrode 64 extends in parallel with the gate electrode 41 ′, and contacts 54a penetrating the interlayer insulating film 50 and the gate insulating film 30 and contacts penetrating the interlayer insulating film 50 ( The drain region of the transistor M3 and the gate electrode 45 are electrically connected to each other in the polycrystalline silicon layer 28 through 54b to become the node A.

The electrode 65 is formed in a substantially rectangular shape adjacent to the gate electrode 41 ', and has a contact hole 56a penetrating through the interlayer insulating film 50 and the gate insulating film 30 and a contact hole penetrating through the interlayer insulating film 50. The drain region of the transistor M4 and the gate electrode 47 are electrically connected to each other in the polycrystalline silicon layer 29 through the 56b to form the node B.

The electrodes 66r, 66g and 66b are electrodes for connecting the pixel electrodes 81r, 81g and 81b of the light emitting elements and the drains of the transistors M2r, M2g and M2b, respectively. The electrodes 66r, 66g, 66b are formed in a substantially rectangular shape that is longer in the horizontal direction in which the gate electrodes 42 to 44 extend than in the vertical direction in which the data line 62 extends. The electrodes 66r, 66g, 66b are respectively in contact with the polysilicon layers 22, 23, 24 through the contact holes 57r, 57g, 57b passing through the gate insulating film 30 and the interlayer insulating film 50, respectively. It is formed to be electrically connected to the drain electrodes of the transistors M2r, M2g, and M2b, respectively.

The planarization layer 70 is formed on the electrodes 63, 64, 65, 66r, 66g, and 66b. The pixel electrodes 81r, 81g, and 81b are electrically connected to the electrodes 66r, 66g, and 66b through the contact holes 71r, 71g, and 71b passing through the planarization film 70, respectively. 5 and 6, red, green, and blue organic thin films 85r and 85g each having a multilayer structure including an emission layer EML, an electron transport layer ETL, and a hole transport layer HTL on the pixel electrodes 81r, 81g, and 81b. , 85b) are formed respectively.

As described above, the capacitor is formed in a substantially rectangular shape with the polycrystalline silicon layer 26 serving as one electrode of the capacitor Cvth in a substantially square shape, centering on the polycrystalline silicon layer 25 extending in the column direction in the central portion of the pixel region. The polycrystalline silicon layer 27 serving as one electrode of Cst) is formed substantially symmetrically with each other. The gate electrode 46 serving as the other electrode of the capacitor Cvth and the gate electrode 47 serving as the other electrode of the capacitor Cst are insulated and overlapped on the polycrystalline silicon layer 26 and the polycrystalline silicon layer 27. Capacitor Cvth and capacitor Cst are formed. By symmetrically arranging the two capacitors, the elements can be more efficiently arranged in the pixel area while ensuring sufficient capacity of the capacitors.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited to the same structure as the embodiments, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the claims are provided. It also belongs to the scope of the present invention.

According to the present invention, the capacitor Cvth and the capacitor Cst are formed substantially symmetrically with respect to the central portion of the pixel region, thereby sufficiently securing the capacitances of the capacitor Cvth and the capacitor Cst and at the same time. A sufficient area for arranging the elements within the device can be secured, thereby realizing a more efficient pixel area arrangement structure.

1 is a diagram illustrating a pixel circuit of a conventional light emitting display panel.

2 is a plan view schematically illustrating a configuration of an organic EL display device according to an exemplary embodiment of the present invention.

3 is an equivalent circuit diagram of one pixel circuit according to an exemplary embodiment of the present invention.

4 is a layout plan view illustrating an arrangement structure of a pixel circuit according to an exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view of the II ′ portion of FIG. 4.

FIG. 6 is a cross-sectional view of the II-II ′ portion of FIG. 4.

Claims (4)

A plurality of scan lines extending in a first direction and transmitting a selection signal, a plurality of data lines insulated from and intersecting the scan lines and extending in a second direction and connected to the scan lines and the data lines, respectively; In a light emitting display device in which a plurality of pixel circuits are arranged in an array form, In the pixel region where the pixel circuit is arranged, First, second and third light emitting devices each having a pixel electrode to which a current is applied, and emitting light based on the current applied thereto; The first semiconductor layer region contacting the pixel electrode of the first light emitting device through the first contact hole, the second semiconductor layer region contacting the pixel electrode of the second light emitting device through the second contact hole and the third light emitting device. A first semiconductor layer including a third semiconductor layer region in contact with the pixel electrode through a third contact hole; First and second conductive layers disposed substantially symmetrically with respect to the second semiconductor layer region; And Third and fourth conductive layers insulated from and overlapping each of the first and second conductive layers and disposed substantially symmetrically with respect to the second semiconductor layer region. The light emitting display device is disposed. The method of claim 1, At least some of the first, second and third semiconductor layer regions are disposed in parallel with the data lines. The method of claim 1, In the pixel area And a fifth conductive layer insulated from and intersecting at least a portion of the second semiconductor layer region to connect the third and fourth conductive layers. The method according to any one of claims 1 to 3, The first and second conductive layers are semiconductor layers doped with a specific type of impurity, respectively.