KR20050102779A - Design of nand flash memory file system - Google Patents

Abstract

The present invention relates to a design method for a NAND type flash memory dedicated file system suitable for a 2 Kbytes page size and a method of designing a NAND type flash memory access layer. The present invention provides a method that exhibits better performance than the conventional NAND-type flash memory usage scheme by the flash translation layer and minimizes the use of memory for address mapping. By designing an access layer that can take advantage of NAND-type flash memory special operations, it provides a way to increase the performance of the file system by utilizing it in the file system, and by using the multi-plane capability of NAND-type flash memory, Simple address translation shows that this is possible.

Description

Design Method of NAND Flash Memory File System {Design of NAND Flash Memory File System}

The present invention relates to an access layer for a NAND-type flash memory and a method of designing a file system dedicated to a NAND-type flash memory.

Flash memory is a nonvolatile memory capable of electrically erasing and writing data, and is widely used as a storage medium for portable information devices such as mobile phones, PDAs, and digital cameras because it is light and resistant to physical shocks and has low power consumption. However, in order to write data in flash memory, a kind of EEPROM, the erase operation must be preceded. Generally, the erase unit is larger than the write unit. This feature makes it difficult to use a file system for a general hard disk when using flash memory as an auxiliary storage device. Therefore, the flash translation layer, which is middleware between the file system and the flash memory, has been proposed and used to hide the limitations and use the flash memory as a block device such as a hard disk. The flash translation layer maintains mapping information between a logical location on a virtual block device and a physical location on a flash memory, and uses a mapping information when a write / read operation is requested for a predetermined logical location. It converts logical locations into physical locations. In particular, logic

When a write operation that changes data is requested for a logical location, the physical location corresponding to the logical location is electrically erased and then rewritten, or the logical location is re-imagined to another physical location.

Flash memory is mainly used in NAND type and NOR type. Recently, due to the large capacity of the storage medium of portable information devices, the high density and low cost, large capacity NAND flash memory is widely used as the basic storage medium. The flash memory file system, which has been proposed and used, is optimized for NOR flash memory and cannot be used to efficiently configure the page unit of NAND flash memory, perform fast block erase operations, and utilize redundant areas within the page. It does not actively utilize special operations such as copy-back provided by type flash memory. The copyback operation can be used to copy a valid page existing in a block to the allocating block before performing the block delete operation.

Currently used NAND flash memory is divided into a page size of 512 bytes and a page size of 2 Kbytes. NAND-type flash memory with a 512 bytes page size has a relatively small capacity. NAND flash memory with 2 Kbytes page size is large and will be used more aggressively. Therefore, the design of a file system dedicated to NAND-type flash memory is based on 2 Kbytes page size NAND-type flash memory. This design makes it difficult to use 512 bytes page size NAND-type flash memory, which utilizes the multi-plane capabilities of NAND-type flash memory at the access layer, so that the upper-tier file system can be as large as 2 Kbytes even with 512 bytes page size NAND-type flash memory. The problem is solved by recognizing a flash memory having a logical page.

The use of such a flash translation layer can not fully utilize the performance of the flash memory and uses a lot of main memory to maintain mapping information. Therefore, a file system dedicated to NAND flash memory considering the characteristics of NAND flash memory is required.

One object of the present invention to solve the above problems is to design a NAND flash memory file system optimized for 2 Kbytes page size, NAND flash memory is the optimal performance in the device that NAND flash memory is used as a storage medium To be able to exercise.

Another object of the present invention is to design an access layer that can utilize NAND-type flash memory special operations such as copyback, and to actively utilize it in the file system to improve the performance of the file system.

Another object of the present invention is to provide an access layer that enables the use of a file system designed for 2 Kbytes by utilizing the multi-plane function of NAND-type flash memory of 512 bytes page size.

Another object of the present invention is to minimize the use of main memory required when mapping the logical address of a file into a physical page address.

In order to achieve the above object, the present invention provides a basic operation of page read / write and block erase of a NAND type flash memory, provides special operations such as copyback, and has an access layer supporting logical pages using multi-planes. It is characterized by. It is also optimized for 2 Kbytes page size NAND-type flash memory and utilizes the special operation provided by the access layer to improve performance and minimizes the use of main memory required to map logical page addresses to physical page addresses. Characterized in having.

Hereinafter, a NAND type flash memory dedicated file system according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 illustrates the overall structure of the present invention. The file system is a basic operation (11) of page read / write and block deletion provided by an access layer. To manage (13). The access layer performs basic functions and special operations (12) as a file system and supports 2 Kbytes logical pages by utilizing the multi-plane function.

NAND-type flash memory is a type of EEPROM that must be preceded by a delete operation in order to write data, and only delete operations larger than a page, which is a write operation unit, are allowed. Because of this restriction, the data being updated is not written to the same place in flash memory, but to a different location. Thus, previous data is invalidated, and subsequent updates cause a particular block to have only invalidated data. In the case of a block having only invalidated data, when the space used in the flash memory is secured, the block is subjected to a delete operation, and after the delete operation is performed, the block is converted into a free block that can be used for data storage. However, due to the cost of wear-leveling of the flash memory and the cost of the erase operation for freeing up space, a block having valid data is also subject to the erase operation. In this case, valid data in the block must be copied to another block in the allocation of flash memory, which can degrade the performance of the flash memory storage technique. The copyback write operation allows you to copy data from one page to another without using external memory. This allows you to perform the copyback write operations provided by NAND-type flash memory at the flash memory access layer. By providing an interface, you can improve the performance of the upper layer file system. 2 illustrates the use of a copyback write operation in securing a used space of a NAND type flash memory according to an exemplary embodiment of the present invention.

Referring to FIG. 2, a copyback write operation is copied to a block 22 for newly allocating a valid page 24 in a block 21 that is a target of a delete operation when securing a used space. The copied page 25 will have the same data as the valid page. Since this process is fast without using external memory, performance can be increased when space is secured. The invalid page 23 is not copied and becomes a blank page by a delete operation to secure space used.

According to a feature of the invention, the data storage of the file system is based on a 2 Kbytes page size. However, the access layer is designed to support logical pages to use NAND type flash memory with 512 bytes page size. The access layer supports logical pages by taking advantage of the multi-plane special operations provided by NAND-type flash memory.

3 illustrates a general structure of a NAND flash memory having a multi-plane structure. 4,096 physical blocks are located on four planes, and each physical block shows an embodiment of a NAND flash memory including 32 physical pages. As shown in FIG. 3, physical blocks of the flash memory are evenly distributed on n memory planes, and each physical block includes a plurality of physical pages. Each plane is provided with a separate page register, which allows you to select one physical block or physical page from each plane to perform simultaneous delete and read / write operations on up to n physical blocks or physical pages. Can be. Hereinafter, the present invention will be described based on the embodiment shown in FIG. 3.

4 illustrates a page write operation according to a preferred embodiment of the present invention. As shown in FIG. 4, an access layer supporting logical pages does not perform 2 Kbytes write operations to four pages 42 in the same plane but to four pages 41 belonging to each plane. In order for a 512 bytes page size NAND-type flash memory with a multi-plane structure to appear as a 2 Kbytes page size NAND-type flash memory by a higher layer, four pages must be grouped into one logical page to perform an operation. Although four pages belonging to the same plane may be bundled to support logical pages, using the multi-plane function may simultaneously enable write operations to improve performance.

Given a page physical address arranged at 2 Kbytes page size and data to be used for write operations, the access layer divides the data into four 512 bytes. In order to perform a multi-plane write operation on divided pieces of data, a series of address translation processes are required, as shown in FIG. The physical address 51 of the NAND type flash memory may be divided into a column address 54 and a page address 55. For address translation, the page address 55 may be represented by subdividing 52 into a plane bit 56, a page address 57, and a block address 58. Substituting the plane bits and the page address among them converts this address into an address 53 that can be used for multi-plane write operations. As shown in the embodiment of FIG. 4, an address that has undergone an address translation process is converted into four page addresses that span the plane, rather than being contiguous with pages of the same plane.

6 illustrates a method for storing in-page data of a NAND flash memory file system according to an exemplary embodiment of the present invention. The pages in the NAND type flash memory are divided into size page space 61 and excess space. In the present invention, data of a file is stored in a page space, and metadata of data stored in the page space is stored in a surplus space. When the file is saved, the file information is stored in the page space. In this case, the file offset separator of the surplus space is set to zero. The file data is then identified by the incrementing file offset delimiter. Therefore, pages with the same file separator stored in the redundant space become pieces of data of the same file.

As shown in the embodiment of Fig. 6, data of the same file is displayed over several pages, and thus a work of mapping a physical page address to a logical offset of the file is required. In the present invention, this operation is performed using a data structure called a page node. Page nodes are dynamically allocated to the system's main memory and implemented to minimize memory usage. There are two page nodes, one of which is a middle layer node that manages end nodes as an inner node. A single inner node manages up to eight end nodes. The inner node moves the upper 3 bits of the file offset delimiter to the lower node by the index value. The end node is the node that holds the actual page address. One node has 16 16-bit page addresses. The page address written to the end node becomes the actual address of the page where the relevant file data is written on the flash memory. The least significant 4 bits of the file offset separator are used as an index value for selecting one of the 16 page addresses recorded at the end node.

As shown in Fig. 7, when one new file is generated, one terminal node 71 is assigned to the generated file by default. The gray nodes in FIG. 7 all represent newly added nodes. Since one end node can store 16 page addresses, a newly created file can store the associated page address in the assigned end node until the data occupies 16 pages. If file's data

 If the size grows to more than 16 pages, as shown in FIG. 8, the file system assigns one more new end node 82 to the file to store additionally generated page addresses. In addition, since one more end node has been added, two internal nodes 81 are allocated. Fig. 9 shows a case where the data size of the file continues to increase so that the required number of end nodes exceeds eight. Since one internal node can manage a maximum of eight end nodes, in this case, one additional end node 93 is added, and one more inner node 92 is needed to manage the added end node. In addition, a higher inner node 91 is required to manage two more inner nodes, and as a result, one end node and two inner nodes are added. In the present invention, through this process, the page node for page address translation is managed.

10 illustrates a process of finding a physical page address through a file offset separator using a page node. The upper three bits are read from the file offset separator and this value is used as an index to move from the upper internal node 101 to the lower internal nodes 102 and 103 in the page node tree. Moving to the end node 104 through this process leaves only the least significant 4 bits of the file offset delimiter. This 4-bit value is the index containing the page address of the offset separator of the file at the current end node, and the value recorded at the position corresponding to this index value at the end node is the page address. Looking at the embodiment of FIG. 10 in detail, assuming that the value of the file offset delimiter to find the page address is 0x753, it is represented as binary '000.001.110.101.0011'. Here, except that the value of the top 3 bits is 0, when reading the top 3 bits, the index to move from the internal node becomes 1 (105), 6 (106), 5 (107) in turn, and follows this index from the highest internal node. Moving to a child internal node finally leads to the end node. In the end node, the page address exists at the position of the file offset delimiter with the least significant 4-bit value, and the file offset delimiter has the least significant 4-bit value, so the physical page address can be found at the end node's fourth position (108). have.

As described above, the present invention is a design method for a NAND-type flash memory dedicated file system suitable for 2 Kbytes page size, and shows better performance than the conventional NAND-type flash memory using technique by the flash translation layer. It also provides a way to minimize use.

In addition, according to the present invention, by designing an access layer that can utilize NAND-type flash memory special operations such as copyback, and actively utilize it in the file system, the performance of the file system can be improved.

In addition, according to the present invention, the 2 Kbytes logical page can be implemented by simple address translation using the multi-plane function of the NAND type flash memory, and the design of the file system can be simplified by using the address conversion.

1 is a general configuration of the present invention.

2 is a diagram illustrating a valid page copying method according to an embodiment of the present invention.

3 is a diagram illustrating a configuration of a flash memory having a multi-plane structure.

4 illustrates a method of performing a multi-plane write operation, in accordance with an embodiment of the invention.

5 is a diagram illustrating an address translation method for supporting logical pages according to an embodiment of the present invention.

6 illustrates a data storage structure in accordance with an embodiment of the present invention.

FIG. 7 illustrates a structure in which a page first page node is allocated according to an embodiment of the present invention. FIG.

8 illustrates a structure in which a new internal page node is allocated according to an embodiment of the present invention.

9 illustrates a structure in which new upper inner page nodes and end page nodes are allocated according to an embodiment of the present invention.

FIG. 10 is a diagram illustrating a physical page search structure through a file offset separator according to an embodiment of the present invention. FIG.

Claims (3)

In the method of securing the used space in the flash memory, A method of providing copyback operations at the access layer and copying valid pages from the file system. In the logical page support method, Separating page addresses; And Performing address translation by replacing the divided addresses; And How to support logical pages using translated addresses. In the method of designing a NAND-type flash-only file system, Storing a physical page address at which data is stored when storing data of the file; And Use this method to retrieve the physical page address of file data.