JP2005092678A - Semiconductor memory card and method for deleting data in nonvolatile memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem with a semiconductor memory card wherein the time it takes to physically delete data in the card gets longer as the volume of the card increases. <P>SOLUTION: An address management table LPT and a physical block management table ET are held in a physical block different from data in a nonvolatile memory 20. When a delete command is received from an external host device, a corresponding logical address is registered as being yet to be allocated, and a physical block that has been allocated to the logical address of the physical block management table is registered as being yet to be used and is written back into the nonvolatile memory 20. This eliminates the need to delete data physically, enabling the data to be deleted at high speed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory card having a rewritable nonvolatile memory and an erasing method for erasing information in the nonvolatile memory.

  A semiconductor memory card having a rewritable nonvolatile memory accesses internal data by converting a logical address given to access the nonvolatile memory into a physical address. A conventional semiconductor memory card associates a physical address and a logical address of a nonvolatile memory by writing a logical address together with data in a redundant area of the physical block. Before an external access to internal data occurs, redundant areas of all physical blocks in the semiconductor memory card are searched, and an address management table for converting logical addresses to physical addresses is created in the internal volatile memory. It was.

  When erasing data in the semiconductor memory card, the physical block to which the corresponding logical address is assigned is searched based on the address management table and physically erased.

In addition, since it takes time to physically erase, for example, Patent Document 1 proposes a flash memory card in which a plurality of block erase operations are simultaneously performed to speed up the erase.
JP-A-8-263361

  However, in the above conventional semiconductor memory card, even when a plurality of blocks are erased simultaneously, when the number of physical blocks increases as the capacity increases, the entire area is physically erased at the time of initialization by FAT. In addition, the processing time may increase.

  An object of the present invention is to make it possible to greatly shorten the data erasing period in a nonvolatile memory.

  The invention of claim 1 of the present application includes a volatile memory, a nonvolatile memory, and a controller that writes data into the volatile memory and the nonvolatile memory and erases the data in response to an external signal. A semiconductor memory card, wherein the nonvolatile memory includes a plurality of address management tables for converting a logical address given from the outside to access the nonvolatile memory into a physical address, and physical block usage status of the nonvolatile memory And a plurality of address management table index information groups indicating positions of the plurality of address management tables and physical block management tables on a nonvolatile memory, and the control unit When erasing data based on the data erasure command from With the unused appropriate logical address of Buru, and writes in the non-volatile memory as unused the physical block management information.

  The invention of claim 2 of the present application includes a volatile memory, a nonvolatile memory, and a controller that writes data into the volatile memory and the nonvolatile memory and erases the data in accordance with an external signal. A data erasing method in a device, wherein the nonvolatile memory includes a plurality of address management tables for converting a logical address given from the outside to access the nonvolatile memory into a physical address, and a physical memory of the nonvolatile memory. A plurality of physical block management tables for managing block usage status, and an address conversion table index information group indicating positions on the nonvolatile memory of the plurality of address management tables and the physical block management tables are stored. When erasing data based on the data erasure command, the address management And unused appropriate logical address table, and writes in the non-volatile memory as unused the physical block management information.

  As described above, according to the present invention, data erasure of a nonvolatile memory such as a semiconductor memory card can be realized only by updating the address management table and the physical block management table to the nonvolatile memory. It is possible to reduce the physical block erase time that occupied Therefore, even when the number of physical blocks increases due to a future increase in the capacity of the semiconductor memory card, the erasing process can be realized without depending on the physical block erasing time. Even if the erasing process of all recorded data is executed at the time of initialization by FAT, the increase in the entire processing time can be minimized.

  FIG. 1 is a conceptual diagram showing a configuration of an address management table (LPT), a physical block management table (ET), and address translation table index information (ATI) in a semiconductor memory card and management information update method according to an embodiment of the present invention. It is. Here, LPT and ET are hereinafter referred to as AT as one pair. FIG. 2 is a conceptual diagram showing the configuration of the semiconductor memory card according to the present embodiment and the address map of the nonvolatile memory in the semiconductor memory card. FIG. 3 is a flowchart showing a data erasure processing method according to this embodiment.

  In FIG. 2, the semiconductor memory card includes a nonvolatile memory 20 such as a flash memory, a host interface circuit (host I / F) 21, a control unit 22, and a RAM (random access memory) 23. The host interface circuit 21 transmits and receives signals such as data and commands between the semiconductor memory card and the host device. The control block 21 includes a CPU (Central Processing Unit), and controls operations of the nonvolatile memory 20 and the semiconductor memory card by a command from a host device. The RAM 23 is a volatile memory that temporarily stores data, address management information, and the like.

  The nonvolatile memory 20 includes an ATI group area 4 and a data area 5. The ATI group area 4 is an area for storing ATI groups, and the data area 5 is an area for storing data. The data area 5 is composed of a plurality of areas (# 0 to # 3 in the figure), and the data entry 7 managed by the AT group 6 and the current AT exists in each area. The nonvolatile memory 20 described in the present embodiment has a 4-bank configuration (Bank 0 to Bank 3). One area of the data area 5 is 1024 blocks / bank. Each physical block is limited to a memory in which a page with a data capacity of 2 KB is composed of two pages.

  In FIG. 1, the ATI group 1 is fixedly held in the AT group area 4 of the nonvolatile memory 20. In FIG. 1, reference numerals 2 and 3 denote AT groups having LPT / ET as one pair (AT), and are referred to as AT group 2 and AT group 3 for convenience. There are AT groups other than those shown in the figure. Reference numeral 10 denotes a block (physical block), and the ATI group 1, AT group 2, AT group 3,... According to the present embodiment have a configuration of four blocks 10 in total, one block per bank.

  The ATI group area 4 is an area for storing ATI groups for managing the AT groups of the four data areas of the data area 5. The ATI has a physical block number of each AT group (the first physical block of each data area is set to 0 and managed for each bank, maximum 1023). In FIG. 1, in order to simplify the description, one AT group has a 4-block configuration and four data areas. However, when an AT group has a 32-block configuration (8 blocks / bank) and manages 8 data areas, 1 word (2B for determining 1024 physical blocks) × 32 (AT group) × 8 (number of data areas) = 512B. Accordingly, as shown in FIG. 1, eight ATIs can be recorded per block. For example, as shown in FIG. 2, the head ATI is stored in the head physical block of the non-volatile memory 20, and link information to one block per bank is written in the redundant area of the page where the head ATI is stored. Form a group. Therefore, a maximum of 32 ATIs can be stored. The update order of the ATI is determined in advance so that the ATI nonvolatile memory 20 is not written to the same block as the current ATI.

  The data area 5 stores data (so-called content information such as music data and image data) read / written from / to an external host device, and also stores an AT group. The data area 5 is divided into four areas (data area # 0 to data area # 3) every 1024 blocks / bank, and the AT group is stored in each data area in order to manage each data area. The

  The data entry 7 managed by the LPT in the AT is managed as one block / bank and a total of four blocks as one entry, and arranged in the order of logical addresses. In the redundant area of the lower page of the first block (for example, bank 0) of each entry managed by the LPT, link information to one block per bank is written. Therefore, it is sufficient to specify only the address of bank 0. In each data area, basically, in order to convert a logical address (0 to 1023 [block x block size x number of banks]) into a physical address (0 to 1023 [block x block size x number of banks]) Each logical block number (every word) corresponding to a logical address has a physical block number (for example, equivalent to 10 bits of the physical address of bank 0) and an allocation flag (1 bit). The allocation flag is a flag indicating whether or not the physical block is logically allocated. Therefore, the data capacity of one LPT is 1 word (physical block number + allocation flag) × 1024 (block) = 2048 B, and one LPT is held in one page.

  The ET in the AT is management information for identifying the usage status of the physical block number (physical address) of each bank. The entry flag for each block is 4 bits (used / unused / erased / unusable). Assign. Therefore, the data capacity of one ET is 4 (bits) × 1024 (block / bank) × 4 (bank) = 2048 B, and one ET is held in one page. LPT and ET are a set of LPT # i and ET # i that manage data in the data area. When data is updated, LPT # i and ET # i are simultaneously updated to become LPT # i + 1 and ET # i + 1, as shown in FIG. Move within the same AT group. Here, in the AT update, the order of writing is determined in advance so that writing to the non-volatile memory 20 of the next AT is not performed in the same block as the current AT. If the current AT group is the AT group 2 managed by ATI # 4 of the ATI group 1 in FIG. 1 and the AT group 2 cannot be updated due to the AT update, a new AT group is created in the same data area. (AT group 3 in FIG. 1) is secured (erase), the AT is updated at the head of the newly secured AT group 3, and a new ATI in which the AT group 3 is registered is created, and ATI # 5 of the ATI group is created. Write to.

  Next, the data erasing operation according to the present embodiment will be described with reference to FIGS. The process of detecting the latest ATI from the ATI group (step S1 in FIG. 3) is performed at the time of initialization, for example, and is not performed for each data write command from the outside (host) to the memory card. Moreover, a series of control shown in FIG. 3 is performed by the control part 22 shown in FIG.

  Data erasure processing within an AT group managed by one ATI will be described with reference to the flowchart of FIG. A data erasure destination area is determined according to a logical address given from the outside (host). For example, when the logical address 0 is designated from an external host device, the physical block number of the AT group corresponding to the data area # 0 in the nonvolatile memory 20 is obtained from the current ATI in step S1. When the current AT is detected, the AT group including the current AT is erased in advance, so that the normal AT is read according to the predetermined AT writing order (# 0 to # 3) shown in FIG. The issued last written AT is set as the current AT. The current effective LPT and ET are read from the nonvolatile memory 20 and transferred to the volatile memory (RAM 23) (step S2). Then, the erase data entry count BC used as a pointer is set to 0 (step S3). Next, the current LPT (for example, LPT # 1) is detected in the read current AT group, and the physical block number in one word corresponding to the logical block number is checked (step S4). If the physical block has not been allocated, the process proceeds to step S6. If the physical block has been allocated, block ring information is read in step S5. When the physical block number is registered in one word corresponding to the logical block number, the physical block number assigned to each bank is read from the redundant area of the registered physical block number (step S5). In step S6, the erase data entry count BC is incremented, and the data entry address LBA in the current data area is incremented. In step S7, the read block number is registered as unused on the ET in the volatile memory (RAM 23). Further, according to the logical address given from the external host, the block number corresponding to the block number of the LPT in the volatile memory (RAM 23) is deleted, or the allocation flag is registered as unallocated. In step S8, it is checked whether or not the specified amount of erasure processing from the post device has been completed. If not, the process returns to step S4. The processing from step S4 to S8 is performed in units of data entries. If the physical block number is not registered in one word corresponding to the logical block number of LPT in S03, the processes in steps S5 and S7 are omitted. When the processing of the data amount designated by the external host is completed, the LPT and ET in the volatile memory (RAM 23) are changed to predetermined write areas in the nonvolatile memory 20 (for example, LPT # 2, ET # 2). (Step S9).

  As described above, erasing of data in the semiconductor memory card can be realized only by updating the LPT and ET in the nonvolatile memory, so that it is possible to reduce the erasing time of the physical block which has occupied the majority of the conventional data erasing time. . Therefore, even when the number of physical blocks increases due to a future increase in the capacity of the semiconductor memory card, the erasing process can be realized without depending on the physical block erasing time. Therefore, even if the erasing process of all recorded data is executed at the initialization by the FAT, the increase in the entire processing time can be minimized.

  In this embodiment, the case where the memory card is configured by one nonvolatile memory has been described. However, even when the memory card is configured by a plurality of nonvolatile memories, one data entry is divided into 8 blocks (1 block / bank). If the configuration is such that two non-volatile memories are managed by one AT by changing the management of ET to 8 blocks, the same processing as in this embodiment is possible.

  In the present embodiment, the memory card has been described as an example as shown in FIG. 2. However, the present invention is not limited to the memory card. For example, the data erasing processing method of the present invention is applied to a device incorporating a nonvolatile memory. It may be used. In this case, the host I / F 21 and the control unit 22 may be configured using resources in a device having the same function.

  The present invention can speed up erasure of a nonvolatile memory such as a semiconductor memory card. Accordingly, such a storage medium can be used in a wide range of applications such as semiconductor memory cards whose capacity is increasing, such as audio video equipment, cameras, communication equipment including mobile phones, video equipment, and other equipment having nonvolatile memory. it can.

The conceptual diagram which shows the address management method by embodiment of this invention The figure which shows the structure and address map of a memory card by embodiment of this invention Flowchart for explaining the operation of the address management method according to the embodiment of the present invention

Explanation of symbols

1 ATI group 2, 3 AT group 4 ATI group area 5 Data area 6 AT area 7 1 Data entry range 20 Non-volatile memory 21 Host I / F
22 control unit 23 RAM

Claims (2)

A semiconductor memory card comprising: a volatile memory; a nonvolatile memory; and a controller that writes data to the volatile memory and the nonvolatile memory and erases the data in response to an external signal,
The nonvolatile memory is
A plurality of address management tables for converting a logical address given from the outside to access the nonvolatile memory into a physical address;
A plurality of physical block management tables for managing physical block usage status of the nonvolatile memory;
An address conversion table index information group indicating a position on the nonvolatile memory of the plurality of address management tables and the physical block management table;
The controller is
When erasing data based on an external data erasure command, the corresponding logical address in the address management table is unused and the physical block management information is written to the nonvolatile memory as unused. Semiconductor memory card. A data erasing processing method in a device comprising: a volatile memory; a nonvolatile memory; and a control unit that writes data to the volatile memory and the nonvolatile memory and erases data according to an external signal. And
The nonvolatile memory is
A plurality of address management tables for converting a logical address given from the outside to access the nonvolatile memory into a physical address;
A plurality of physical block management tables for managing physical block usage status of the nonvolatile memory;
An address conversion table index information group indicating a position on the nonvolatile memory of the plurality of address management tables and the physical block management table;
When erasing data based on an external data erasure command, the corresponding logical address in the address management table is unused,
A data erasure processing method, wherein the physical block management information is written in the nonvolatile memory as unused.

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