KR20050101840A - Serial communication circuit - Google Patents

Abstract

The present invention relates to a serial communication circuit capable of improving transmission speed by decoding a plurality of bit data and transmitting using a plurality of logic levels when transmitting and receiving data, and encoding the received logic level using a comparator. In a serial communication circuit that uses serial communication for data transmission between systems, and converts and transmits and receives parallel data in each system to serial data through a serial input output (SIO), the SIO transmits a plurality of parallel data. Parallel blocks are generated by decoding a plurality of bit data by using a logic level of the data and transmitting the data in serial, and encoding a plurality of bit data by comparing a logic level corresponding to the received serial data with a plurality of reference logic levels. It characterized in that it comprises a receiving block.

Description

Serial communication circuit

The present invention relates to a serial communication circuit, and more particularly, to decode and transmit a plurality of bit data using a plurality of logic levels, and to encode a received logic level using a comparator to improve transmission speed. It relates to a serial communication circuit that can be.

1 is a conceptual diagram illustrating an operation of performing serial communication between two systems according to the prior art.

Referring to FIG. 1, serial data D0 to D7 inside each system are converted into serial data through SIO (Serial Input Output) 1 using serial communication for data transmission between system A and system B. This is a general asynchronous serial communication method of transmitting and receiving each. Here, the SIO 1 includes a transmitter 2 for converting and converting parallel data into serial data and a receiver 3 for converting received serial data into parallel data.

FIG. 2 is a detailed circuit diagram showing the transmitter 2 of the SIO 1 shown in FIG.

The transmitter 2 of the SIO 1 includes a parallel data buffer 4, a 10 bit shift register 6, and an output data buffer 8.

The parallel data buffer 4 transfers the start bit, the 8 bit data D0 to D7, and the stop bit to the 10 bit shift register 6 in parallel by the write activation signal WE.

The 10-bit shift register 6 is activated by the transmit activation signal TxEN and sequentially outputs start bits, 8-bit data D0 to D7, and stop bits in synchronization with the clock CLK.

The output data buffer 8 serially transmits start bits, 8-bit data D0 to D7, and stop bits output from the 10-bit shift register 6 by the transmission activation signal TxEN.

FIG. 3 is a detailed circuit diagram showing the receiver 3 of the SIO 1 shown in FIG.

The receiving unit 3 of the SIO 1 includes a receiving data buffer 10, a 10 bit shift register 12, and a parallel data buffer 14.

The receive data buffer 10 is activated by the receive activation signal RxEN to receive start bits, 8-bit data D0 to D7, and stop bits in series.

The 10-bit shift register 12 is activated by the receive activation signal RxEN to sequentially shift start bits, 8-bit data D0 to D7, and stop bits in synchronization with the clock CLK. At this time, when all 10 bits are shifted, the reception data buffer 10 is inactivated.

The parallel data buffer 14 is activated by the read enable signal RE to send start bits, 8-bit data D0 to D7, and stop bits stored in the 10-bit shift register 12 in parallel within the system. do.

4 is a waveform diagram showing data transmission and reception operations of the SIO 1 shown in FIGS. 1, 2 and 3;

Referring to FIG. 4, the SIO 1 transmits and receives in the order of start bits, 8-bit data D0 to D7, and stop bits, where data of each bit is divided into two logic levels (low level). (0V), high level (VDD), "0" and "1" are recognized.

As described above, since the SIO 1 according to the related art requires 8 clocks to transmit 8-bit data by transmitting 1 bit through the transmission line, the clock needs to be set quickly in a system requiring high speed. However, setting the clock quickly has limitations that are dependent on the system itself.

An object of the present invention to solve the above problems is to improve the transmission rate by decoding a plurality of bits at a time using a plurality of logic levels to transmit, and to encode the received data using a comparator.

In order to achieve the above object, the serial communication circuit of the present invention uses serial communication for data transmission between a plurality of systems, and converts parallel data in each system into serial data through a serial input output (SIO), and A serial communication circuit for receiving, said SIO comprising: a transmission block for transmitting parallel data in series by decoding a plurality of bit data using a plurality of logic levels; And a receiving block for generating parallel data by encoding the logic level corresponding to the received serial data with a plurality of reference logic levels and encoding the plurality of bit data.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a conceptual diagram illustrating an operation of performing serial communication between two systems according to the present invention. Here, an example of setting two bit data to one voltage level will be described. In addition, a plurality of bit data can be set to one voltage level.

Referring to FIG. 5, the serial data D0 to D7 in each system are converted into two signals through a SIO (Serial Input Output) 15 using serial communication for data transmission between system A and system B. Decode and transmit Asynchronous serial communication method. Here, the SIO 15 includes a transmitter 16 for converting and converting parallel data into serial data, and a receiver 17 for converting the received serial data into parallel data.

FIG. 6 is a detailed circuit diagram showing the transmitter 16 of the SIO 15 shown in FIG.

Transmitter 16 of SIO 15 includes two parallel data buffers 18 and 20, two 6-bit shift registers 22 and 24, a 2X4 decoder 26, and multiple switches 28, 30, 32, 34).

The even parallel data buffer 18 sends the start bit, the 4-bit data D0, D2, D4, D6, and the stop bit in parallel to the 6-bit shift register 22 by the write enable signal WE. The odd parallel data buffer 20 transmits the start bit, the 4-bit data D1, D3, D5, D7, and the stop bit in parallel to the 6-bit shift register 24 by the write enable signal WE. do.

The even 6-bit shift register 22 is activated by the transmit enable signal TxEN to sequentially decode the start bit, the 4-bit data D0, D2, D4, D6, and the stop bit in synchronization with the clock CLK. 26, an odd 6-bit shift register 24 is activated by the transmit enable signal TxEN to transfer the start bits, 4-bit data D1, D3, D5, D7, and stop bits to the clock CLK. In synchronization, the data is transmitted to the decoder 26 sequentially.

The decoder 26 is activated by the transmit activation signal TxEN and decodes the data De and Do transmitted by the two 6-bit shift registers 22 and 24 to generate the switch control signals Q0, Q1, Q2 and Q3.

The first switch 28 selectively outputs the ground voltage level GND according to the first switch control signal Q0, and the second switch 30 outputs the second voltage level Vr2 (2VDD / 6) according to the second switch control signal Q1. Is selectively outputted, the third switch 32 selectively outputs the fourth voltage level Vr4 (4VDD / 6) according to the third switch control signal Q2, and the fourth switch 34 is the fourth switch control signal Q3. The output voltage level VDD is selectively output.

FIG. 7 is a detailed circuit diagram illustrating a reference voltage generator circuit for generating voltage levels Vr2 and Vr4 shown in FIG. 6.

The reference voltage generator circuit includes a voltage generator 36 including six resistors R connected in series and an activator 38 for selectively applying the supply voltage VDD to the voltage generator 36 by the transmit activation signal TxEN. .

The voltage generator 36 generates corresponding voltage levels Vr1, Vr2, Vr3, Vr4, and Vr5 at the common node of each resistor R. FIG.

The activation part 36 is comprised by the switch controlled by the transmission activation signal TxEN.

The truth table of the operation of the transmission portion of the SIO 15 according to the prior art is shown in [Table 1].

TABLE 1

Do De Q3 Q2 Q1 Q0 Output voltage level (V) 0 0 0 0 0 One GND 0 One 0 0 One 0 Vr2 (2VDD / 6) One 0 0 One 0 0 Vr4 (4VDD / 6) One One One 0 0 0 VDD

FIG. 8 is a waveform diagram showing the data transmission operation of the SIO 15 shown in FIGS. 5, 6 and 7. FIG.

Referring to Figure 8, the start bit, the signals D0, D1, (D2, D3), (D4, D5), (D6, D7), and two bits having arbitrary voltage levels, stop) is transmitted in bit order, where any voltage level has four potentials depending on the value of the two bits. That is, if the values of both bits are "1" (D4, D5), the supply voltage level is VDD, and if the values of both bits are "0" (D6, D7), the ground voltage GND is even. When the bit is "1" and the odd bit is "0" (D0, D1), the fourth voltage level Vr4 (4VDD / 6) becomes, the even bit is "0", and the odd bit is "1" ( D2, D3) becomes the second voltage level Vr2 (2VDD / 6).

FIG. 9 is a detailed circuit diagram of the receiver 17 of the SIO 15 shown in FIG.

The receiver 17 of the SIO 15 includes a comparator 40, an encoder 42, two six-bit shift registers 46 and 48, and two parallel data buffers 50 and 52.

The comparator 40 includes three comparators 41, and each comparator 41 compares the voltage level received by the reception activation signal RxEN with the reference voltages Vr1, Vr3, and Vr5, respectively.

The encoder 42 includes two AND gates 43 and 45 and an exclusive NOR gate 44, and encodes even signals by encoding signals m0, m2 and m3 output from the comparator 40. Output De and odd data Do.

The even 6-bit shift register 46 sequentially stores the even data De output from the encoding section 42 by the receive activation signal RxEN in synchronization with the clock CLK, and the odd 6-bit shift register 48 stores the receive activation signal RxEN. The odd data Do output from the encoding section 42 is sequentially stored in synchronization with the clock CLK.

The even parallel data buffer 50 transmits in parallel the start bits, 4-bit data D0, D2, D4, D6, and stop bits stored in the even shift register 46 by the read enable signal RE. The odd parallel data buffer 52 transmits in parallel the start bits, 4-bit data D1, D3, D5, D7, and stop bits stored in the odd shift register 48 by the read enable signal RE. do.

FIG. 10 is a detailed circuit diagram illustrating a reference voltage generator circuit for generating the reference voltages Vr1, Vr3, and Vr5 shown in FIG. 9.

The reference voltage generator circuit includes a voltage generator 54 including six resistors R connected in series and an activation unit 56 for selectively applying a supply voltage VDD to the voltage generator 54 by the reception activation signal RxEN. .

The voltage generator 54 generates corresponding voltage levels Vr1, Vr2, Vr3, Vr4, and Vr5 at the common node of each resistor R. FIG.

The activation unit 56 is composed of a switch controlled by the reception activation signal RxEN.

FIG. 11 is a waveform diagram illustrating a data receiving operation of the SIO 15 shown in FIGS. 5, 9, and 10.

Referring to FIG. 11, two data values De and Do are determined according to the voltage level of the received data.

First, in the step T1 at which the voltage level GND corresponding to the start bit is received, the values of the signals m0, m1, and m2 output from the comparators 41 of the comparator 40 are all “0”. The even data De and the odd data Do output from the encoding section 42 both become " 0 " and are stored in the two 6-bit shift registers 50 and 52.

When the voltage level Vr4 (4VDD / 6) corresponding to the first two bits of data D0 and D1 is received, step T2 is performed by the signals m0, m1 and m2 output from the comparators 41 of the comparator 40. The values are " 1 ", " 1 " and " 0 ", respectively, the even data De output from the encoding section 42 becomes " 0 ", and the odd data Do becomes " 1 " Stored at (50, 52). At this time, the start bits stored in the two 6-bit shift registers 50 and 52 are shifted by the clock CLK.

In step T3, when the voltage level Vr2 (2VDD / 6) corresponding to the second two bits of data D2 and D3 is received, the signals m0, m1, and m2 output from the comparators 41 of the comparator 40 are received. The values of are " 1 ", " 0 " and " 0 ", respectively, the even data De output from the encoding section 42 becomes " 1 ", and the odd data Do becomes " 0 " Are stored in registers 50 and 52. At this time, the start bits and the data D0 and D1 stored in the two 6-bit shift registers 50 and 52 are shifted by the clock CLK.

In step T4, when the voltage level VDD corresponding to the third two bits of data D4 and D5 is received, the values of the signals m0, m1, and m2 output from the comparators 41 of the comparator 40 are all ". 1 ", the even data De output from the encoding section 42 becomes" 1 ", and the odd data Do becomes" 1 "and stored in the two 6-bit shift registers 50 and 52. At this time, the start bits and the data D0, D2 and D1, D3 stored in the two 6-bit shift registers 50, 52 are shifted by the clock CLK.

In step T5, when the voltage level GND corresponding to the fourth two bits of data D6 and D7 is received, the values of the signals m0, m1 and m2 output from the comparators 41 of the comparator 40 are all ". 0 ", the even data De output from the encoding section 42 becomes" 0 ", and the odd data Do becomes" 0 "and stored in the two 6-bit shift registers 50 and 52. At this time, the start bits and the data D0, D2, D4 and D1, D3, D5 stored in the two 6-bit shift registers 50, 52 are shifted by the clock CLK.

In step T6, in which the voltage level VDD corresponding to the stop bit is applied, the values of the signals m0, m1, and m2 output from the comparators 41 of the comparator 40 are all “1”, and the encoding is performed. The even data De and the odd data Do output from the section 42 both become " 1 " and are stored in the two 6-bit shift registers 50 and 52. At this time, the start bits and the data D0, D2, D4, D6 and D1, D3, D5, D7 stored in the two 6-bit shift registers 50, 52 are shifted by the clock CLK.

The relationship between the signals m0, m1, m2 and even data De and odd data Do output from each comparator 41 for each step T1, T2, T3, T4, T5, and T6 of the waveform diagram shown in FIG. When organized into a table, it can be expressed as shown in [Table 2].

TABLE 2

T1 T2 T3 T4 T5 T6 m2 0 0 0 One 0 One m1 0 One 0 One 0 One m0 0 One One One 0 One De 0 0 One One 0 One Do 0 One 0 One 0 One

Since each reference voltage generation circuit applied to the transmitter 16 and the receiver 17 of the SIO 15 shown in FIGS. 7 and 10 is the same circuit, one reference voltage generation circuit is actually used for the SIO 15. Therefore, the present invention can be commonly applied to the transmitter 16 and the receiver 17 of the SIO 15. At this time, the switch of the activator 38 or 56 is designed to be controlled by a logical combination of the transmit activation signal TxEN and the receive activation signal RxEN.

As described above, the serial communication circuit according to the present invention has the effect of improving the transmission speed by decoding a plurality of bits at a time by using a plurality of logic levels and transmitting the received data by using a comparator. have.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1 is a conceptual diagram illustrating an operation of performing serial communication between two systems according to the prior art.

FIG. 2 is a detailed circuit diagram illustrating a transmitter of the SIO illustrated in FIG. 1.

3 is a detailed circuit diagram illustrating a receiver of the SIO illustrated in FIG. 1.

4 is a waveform diagram showing data transmission and reception operations of the SIO shown in FIGS. 1, 2, and 3;

5 is a conceptual diagram illustrating an operation of performing serial communication between two systems according to the present invention.

FIG. 6 is a detailed circuit diagram illustrating a transmitter of SIO2 shown in FIG. 5.

FIG. 7 is a detailed circuit diagram illustrating a reference voltage generation circuit for generating voltage levels Vr2 and Vr4 shown in FIG. 6.

Fig. 8 is a waveform diagram showing a data transmission operation of the SIO shown in Figs. 5, 6 and 7;

9 is a detailed circuit diagram illustrating a receiver of the SIO illustrated in FIG. 5.

FIG. 10 is a detailed circuit diagram illustrating a reference voltage generator circuit for generating the reference voltages Vr1, Vr3, and Vr5 shown in FIG.

FIG. 11 is a waveform diagram showing a data receiving operation of the SIO shown in FIGS. 5, 9 and 10;

Claims (11)

In the serial communication circuit for transmitting and receiving the parallel data in each system to serial data through the serial input output (SIO) using serial communication for data transmission between multiple systems, The SIO A transmission block for transmitting the serial data in serial by decoding a plurality of bit data using a plurality of logic levels; And And a receiving block which compares the logic level corresponding to the received serial data with a plurality of reference logic levels and encodes the plurality of bit data to generate parallel data. The method of claim 1, wherein the transmission block A plurality of shift registers for sequentially outputting parallel data; A decoder for decoding data sequentially transmitted by the plurality of shift registers; And And an output block for outputting the logic level corresponding to the signal output from the decoder. The method of claim 2, And said shift register performs a shift operation in synchronization with an arbitrary clock. The method of claim 2, wherein the output block is A voltage generation block generating said logic level; And And a plurality of switches each controlled by a signal output from the decoder to selectively output the plurality of logic levels. The method of claim 4, wherein the voltage generation block And a plurality of resistors connected in series between a supply voltage and a ground voltage, wherein the plurality of logic levels are output at a node to which the plurality of resistors are commonly connected. The method of claim 1, wherein the receiving block A plurality of comparing means for comparing the logic level with a plurality of reference logic levels; An encoder for encoding data corresponding to the logic level by using signals output from the plurality of comparing means; And And a plurality of shift registers for sequentially storing data output from the encoder and outputting parallel data. The method of claim 6, And said shift register performs a shift operation in synchronization with an arbitrary clock. The method of claim 6, And a voltage generating block for generating said reference logic level. The method of claim 8, wherein the voltage generation block And a plurality of resistors connected in series between a supply voltage and a ground voltage, wherein said plurality of reference logic levels are output at a node to which said plurality of resistors are commonly connected. The method of claim 1, And a voltage generating block for generating said logic level and said reference logic level. The method of claim 10, The voltage generation block includes a plurality of resistors connected in series between a supply voltage and a ground voltage, wherein the plurality of logic levels and the plurality of reference logic levels are alternately output at a node to which the plurality of resistors are commonly connected. Serial communication circuit, characterized in that.