JP5106757B2 - Voltage level coding system and method - Google Patents

Description

  The present invention relates to coding systems and methods, and more particularly, to voltage level coding systems and methods.

  FIG. 1 is a block diagram of a typical data transmission system including a transmission unit 102 and a reception unit 104. The transmitting unit 102 receives the digital signal DATA_IN, and converts the digital signal DATA_IN into an analog signal DATA that can be transmitted using a digital / analog converter (DAC) 106. The transmission unit 102 transmits the analog signal DATA to an analog / digital conversion unit (ADC: Analog Digital Converter) 108 in the reception unit 104. The ADC 108 converts the analog data DATA into a digital signal DATA_OUT.

  The transmitter 102, and in particular the ADC 106, can encode the digital signal DATA_IN before transmitting the digital signal DATA_IN as an analog signal DATA to the receiver 104. The transmitter 102 can encode the digital signal DATA_IN using various transmission codes of 8B / 10B coding.

  Since 8B / 10B coding is a direct current (DC) balanced code, it is very suitable for high-speed local area necklines and computer links, and is widely used. The DC balanced transmission code is DC free and has a constant DC level regardless of the data pattern. The DC balanced transmission code has received much attention because it can simplify the transmission system. Such simplification of the system ultimately reduces system cost and improves reliability.

  8B / 10B coding examines each data octet and assigns a 10-bit code. One method includes dividing 8-bit wide data into two packets or nibbles. The first nibble includes 5 LSB (Least Significant Bits), and the second nibble includes 3 MSB (Most Significant Bits). Five nibbles are encoded into a 6-bit code, and three nibbles are encoded into a 4-bit code. The two encoded nibbles form a 10-bit code packet, and the 10-bit code packet is transmitted from the transmission unit 102 in series and transmitted to the reception unit 104. The 8B / 10B coding table is well known, and is disclosed, for example, in US Pat.

  A 10-bit code packet may contain 5 1's and 5 0's, 4 1's and 6 0's, or 6 1's and 4 0's. . This ensures that too many consecutive ones or zeros do not occur during the code packet. In order to maintain DC balance, a calculation called running disparity is used to maintain the number of transmitted 1s equal to the number of transmitted 0s.

  8B / 10B coding is disadvantageous for various reasons. For one, 8B / 10B coding uses 10 bits for each 8-bit data to reduce the data rate rate relative to the line rate. For example, to obtain a data rate of 1 Gbps, the line speed must be 10/8 * 1 = 1.25 Gbp.

  Another disadvantageous reason is that transmission between the highest level and the lowest level degrades the transmission frequency characteristics. FIG. 2 is a voltage amplitude diagram over time for 8B / 10B code data with various transitions between other levels superimposed on each other. FIG. 3 is a state transition diagram of 8B / 10B coding. 2 and 3, it is assumed that a voltage level of 1.2V indicates a 00 logic state and a 1.8V voltage level indicates a 10 logic state. Referring to FIGS. 2 and 3, the diagram may vary depending on a transition from one state to another, for example, a transition to 10-11-10 or a transition to 11-00-11, and other transitions. 8B / 10B code packet response. As shown in FIG. 3, the longest transition occurs at the transition between the 00 state and the 10 state or vice versa. These long state transitions have a wide-angle effect that adversely affects the transmission of high-frequency data because the larger the voltage transition, the longer it takes for the signal to reach the proper voltage level, i.e., the proper code state. Create an opening.

Accordingly, there is a need for improved coding systems and methods.
US Pat. No. 5,387,911

  The problem to be solved by the present invention is to provide a voltage level coding system and method capable of realizing high speed operation by minimizing data skew in a short transition time.

To achieve the above object, a voltage level coding system and method according to a preferred embodiment of the present invention includes an input for receiving a data segment coded using a first code, and at least 2 ^N And a level encoder having an output for supplying a second data code indicating one of the voltage levels obtained by adding one additional voltage level. The conversion unit converts the second data code into each voltage level. The output of the control unit then supplies a voltage level.

  The level encoder can receive the data segment in the first code and can supply the data segment in the second code.

  The first code may include 1 and 0, and the second code may include 1, 0, and S.

  The level encoder may include a serial / parallel converter that converts serial data segments in the first code into parallel data segments in the first code. The input latch latches the parallel data segments in the first code. The coding block codes parallel data segments in the first code into parallel data segments in the second code. The output latch latches the parallel data segment in the second code. Then, the parallel / serial converter converts the parallel data segment in the second code into a serial data segment in the second code.

  The conversion unit may include a pre-driver that receives a data segment in the second code and a multi-level driver that generates a voltage level corresponding to the pre-driver.

  The system includes a level decoder having a second converter for converting a voltage level to a second data code, an input for receiving the second data code, and an output for providing a data segment in the second data code. Can be included.

  A method for coding digital data for transmission to an analog channel includes determining a first data transition and a code including at least one additional level to minimize data skew in the first data transition. Generating and coding the first data transition to an additional level in the code.

  The step of determining the first data transition may be a step of determining a data transition from low to high.

  The step of determining may be a step of determining a transition from the lowest level to the highest level.

  The step of determining may be a step of determining a transition between 00 and 10.

  Generating the code may be generating a code having an additional SS level.

  The step of generating a code at an additional SS level may be a step of generating an SS level closer to 00 level than 10 level.

  The data coding method may include coding digital data from a first code to a second code including at least one level.

The step of coding the digital data includes applying the coded digital data to the input of the N-bit digital / analog conversion unit and generating a level obtained by adding at least one additional level to 2 ^N for the output of the conversion unit. Stages.

The memory system includes a control unit and a memory device. The control unit supplies a data code indicating one voltage level assigned to each data segment among an input for receiving the data segment and a voltage level obtained by adding at least one additional voltage level to ^2N. And a level encoder having: The first conversion unit converts the data code into each voltage level, and the control unit outputs the voltage level to supply the voltage level. The memory device includes an input for receiving a voltage level from the control unit, a second conversion unit for converting the voltage level into a data code, an input for receiving the data code, and an output for supplying the data code. A decoder.

  The memory device may include an analog channel connected to the controller and a memory to which a voltage level is applied.

  The level encoder can assign at least one additional voltage level to the low-to-high transition.

  The level encoder can assign at least one additional voltage level to the transition from the lowest level to the highest level.

  At least one additional voltage level is closer to 00 level than 10 level.

The first converter is an N-bit digital / analog converter, and can generate a voltage level obtained by adding at least one additional voltage level to 2 ^N as an output of the first converter.

The second conversion unit is an N-bit digital / analog conversion unit, and can generate a voltage level obtained by adding at least one additional voltage level to 2 ^N as an output of the second conversion unit.

  The present invention can realize high-speed operation of a data transmission system by minimizing data skew with a short transition time.

  For a full understanding of the invention and the operational advantages thereof and the objects achieved by the practice of the invention, reference should be made to the accompanying drawings illustrating the preferred embodiments of the invention and the contents described in the accompanying drawings. I have to do it.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numbers provided in each drawing represent similar components.

  FIG. 4 is a coding transmission diagram according to a preferred embodiment of the present invention. Referring to FIG. 4, the coding system of the present embodiment includes an additional SS code representing an additional voltage level for an existing coding system, for example, 8B / 10B coding. The SS code can represent a predetermined voltage level substantially closer to the voltage level representing the 00 code than the 10 code. For example, when the 00 code represents 1.2V and the 10 code represents 1.8V, the SS code can be represented by the same voltage level as 1.0V.

  The coding system of the present embodiment can replace a data pattern representing an undesired high frequency operation, for example, a 00-10-00 pattern, with a pattern representing a more desirable high frequency operation, for example, a 00-SS-00 pattern. In other words, the coding system according to the preferred embodiment of the present invention can replace the longest voltage transition between 00 and 10 with a shorter 00-SS transition, where SS code is The voltage level is closer to the 00 code voltage level than the 10 code voltage level. As a result, the reduced transition time minimizes data skew and improves high frequency operation.

  FIG. 5 is a block diagram of a data transmission system 200 according to a preferred embodiment of the present invention. Referring to FIG. 5, the transmission system 200 includes a transmission unit 202 that receives a digital signal DATA_IN and converts it into a transmittable analog signal DATA using a level encoder 205 and a DAC 206. The transmission unit 202 transmits the analog signal DATA to the ADC 208 and the level decoder 209 of the reception unit 204. The receiving unit 204 receives the analog signal DATA and decodes it to provide a digital signal DATA_OUT.

  FIG. 6 is a block diagram of the embodiment of the level encoder 205 shown in FIG. Referring to FIG. 6, the level encoder 205 receives data segments, eg, AB, CD, and EF data segments, from the digital signal DATA_IN, and each data segment represents at least one additional voltage level representing at least one voltage level. Encode with UV, WX and YZ codes including SS code. In other words, the input digital signal DATA_IN includes data segments coded with 1 and 0, and the coded data signal TA_IN includes data segments coded with 1, 0, and S.

  As described above, the SS code can represent a voltage level that can minimize data skew by shortening the transition time of the data segment. For example, if the 00 code represents 1.2V and the 10 code represents 1.8V, the SS code can be set at 1.0V. A coding system according to a preferred embodiment of the present invention provides a data transition requiring a voltage swing from 1.2V to 1.8V between 00 code and 10 code from 1.2V to 1.0V. A voltage swing can be substituted. Referring to FIG. 6, each of the three data segments is represented by 2 bits (eg, AB, CD, EF). However, those skilled in the art will appreciate that, according to the preferred embodiment of the present invention, each data segment can be broadly extended to multiple data segments having multiple bits.

  FIG. 7 is a specific block diagram of the embodiment of the level encoder 205 shown in FIGS. Referring to FIG. 7, the level encoder 205 converts serial data segments AB, CD, EF from the digital signal DATA-IN into parallel segments 704 (eg, A, B, C, D, E, and F). / A parallel conversion unit 702 is included. The parallel segment 704 can be coded with various transmission codes, eg, transmission codes based on 1 and 0 with 8B / 10B coding. The function mapping block or circuit 706 is a code according to a preferred embodiment of the present invention in which the parallel data segment 704 is added to N bits with one additional code (eg, SS code) representing an additional voltage level. Align or code to parallel segment 708. That is, the function mapping block 706 encodes the parallel data segment 704 in the first code based on 1 and 0 into the parallel data code 708 in the second code based on 1, 0, and S.

  Table 1 shows a 6-bit data segment that can be changed to the four possible levels 00, 01, 11, 10 shown in FIG. 3 and the five possible levels SS, 00, 01, 11, 10 is an exemplary table for mapping to a 6-bit data segment that can be changed to 10. This is a mapping performed by the encoder 205. Of the four levels, all possible combinations of transitions are listed in the non-coded column, and of the five levels, all possible combinations of transitions are listed in the coded column. ing. The shaded area of the non-coded column represents the worst case transition in the 4-level code, i.e. the combination of adjacent transitions crossing 4 levels. In other words, the shaded area is a combination where adjacent transitions have between 00 and 10 or vice versa. Each possible combination of transitions is numbered 1-64 in the left column.

The shaded part in the coded column represents the worst case transition in the 5 level code, ie all combinations of transitions where adjacent transitions cross 4 or 5 levels. In other words, these shaded areas are adjacent transitions that move between SS and 11, between SS and 10, and between 00 and 10. The numbers in the first column of the coded column correspond to the same number of non-coded columns. That is, each numbered combination in a non-coded column is mapped to that number of combinations in the column coded by encoder 205. The 75 possible combinations include adjacent transitions across 3 levels or less. Only 64 levels are required. Thus, a 5 level code maps all combinations to combinations that transition between at most 3 levels. On the other hand, the 4-level code required some transition between the 4 levels in the shaded part in the non-coded column. Table 1 is understood to be exemplary to those skilled in the art and can be easily extended to large and small data segments with more or less levels.
Parallel / serial converter 710 converts coded parallel data segments 708 (eg, U, V, W, X, Y, and Z) into coded serial data segments (eg, UV, WX, and YZ). To do.

  FIG. 8 is a block diagram showing an embodiment of the level encoder 205 and the DAC 206 shown in FIG. The parallel / serial converter 710 outputs the data segment to the pre-driver 902 in the ADC 208 in series. In an embodiment, the parallel / serial converter 710 puts a pair of data segments in series with four lines assigned to two lines for each digit place. One line represents 1 or 0, and the other line represents S. If the S line is low, its value is 1 or 0 regardless of what the remaining lines are. If the S line is high, the value is S. The parallel / serial converter 710 outputs the value to the pre-driver 902 in series as in the clock timing diagram shown inside the pre-driver 902. For example, the parallel / serial converter 710 outputs a UV data segment with a first clock pulse, a WX data segment with a second clock pulse, and a YZ data segment with a third clock pulse.

  FIG. 9 is a block diagram illustrating an embodiment of the DAC 206 shown in FIG. FIG. 10 shows how each of the SS-10 levels provides a voltage to one of the transistors MN1 or S1-S4, so that five of the analog signals sent from the transmitter 202 to the receiver 204 are shown. 6 is a coding table 1000 for explaining whether one of other voltage levels is generated. Referring to FIGS. 9 and 10, the coding table 1000 may include coded data segments, eg, UV, WX, and YZ data segments having 10, 11, 01, 00 and SS codes, as pre-drivers 902 values V1-V5. , And analog voltage levels (1.8V, 1.6V, 1.4V, 1.2V and 1.0V). For example, pre-driver 902 outputs a V1 value of 0 for the input data segment coded at 10, requesting that multi-level driver 904 output the same analog voltage as 1.8V. As another example, pre-driver 902 outputs a V1 and V2 value of 1 for the data segment coded at 11, requesting that multi-level driver 904 output the same analog voltage as 1.6V. Similarly, the pre-driver 904 outputs a V1 and V5 value of 1 for the SS coded data segment, requesting the multi-level driver 904 to output the same analog voltage as 1.0V. The DAC 206 can have an additional level capacity of N bits. One skilled in the art will appreciate that other types and sizes of DACs may be used within the scope of the present invention.

  FIG. 11 is a block diagram showing an embodiment of the ADC shown in FIG. Referring to FIG. 11, the ADC 208 includes a plurality of series-connected reference resistors R2-R6 that generate a plurality of reference voltages VREF1-VREF4. Reference resistors R2-R6 are connected in series between power supply voltage VDD and ground voltage VSS. The reference resistors R2-R6 provide the corresponding reference voltages VREF1-VREF4 to the comparator 1104. Comparator 1104 generates VD1-VD4 voltages in response to a comparison between analog signal DATA and reference voltages VREF1-VREF4 provided by reference resistors R2-R6. Encoder 1106 is a UV, WX and YZ data segment encoded with a code according to a preferred embodiment of the present invention based on 1, 0 and S representing VD1-VD4 voltages in coding table 1200 (FIG. 2). Encode with. For example, if the VD1-VD4 voltages are all 1, the encoder 1106 outputs a UV data segment coded at 10. As another example, if both the VD1-VD4 voltages are 0, the encoder 1106 outputs a WX data segment coded with SS.

The ADC 208 may have an additional level capacity of ^2N . One skilled in the art will appreciate that other types and sizes of ADCs may be used within the scope of the present invention.

  FIG. 13 is a block diagram showing an embodiment of the level decoder 209 shown in FIG. Referring to FIG. 13, the level decoder 209 decodes UV, WX and YZ data segments from a coded DATA_OUT signal including at least one additional SS code representing at least one voltage level. Decode to AB, CD and EF. In other words, the level decoder 209 decodes the input data segment having 1, 0 and S into the data segment having 1 and 0.

  As described above, the SS code can represent a voltage level that minimizes data skew by shortening the data transition time. For example, when the 00 code represents 1.2V and the 10 code represents 1.8V, the SS code can be set at 1.0V. The coding system according to the preferred embodiment of the present invention can perform data transition between 00 code and 10 code, which requires a voltage swing from 1.2V to 1.8V, for example, 1.2V and 1. A voltage swing between 0V can be substituted. Although FIG. 13 shows three data segments having 2 bits (UV, WX, and YZ), those skilled in the art will appreciate that the scope of the present invention is various with various numbers of bits associated with each data segment. It will be appreciated that it can be extended to any number of data segments.

  FIG. 14 is a specific block diagram showing an embodiment of the level decoder 209 shown in FIGS. 5 and 13. Referring to FIG. 14, the level decoder 209 converts a serial data segment (UV, WX, and YZ) from a coded DATA_OUT signal into a parallel segment 1404 (U, V, W, X, Y, and Z). A parallel conversion unit 1402 is included. The parallel data segment 1404 can be coded with a transmission code according to a preferred embodiment of the present invention based on 1, 0 and S as described above. The function block or circuit 1406 maps or decodes the parallel data segment 1404 to the parallel segment 1408 based on one additional code that represents an additional voltage level in N bits. Mapping block 1406 can use the values in Table 1 to map or decode data segment 1404 to data segment 1408. The parallel / serial converter 1410 converts the decoded parallel data segments 1408 (A, B, C, D, E, and F) into decoded serial data segments (AB, CD, and EF).

  FIG. 15 is an 8B / 10B (3-bit) coding state transition diagram. Referring to FIG. 15, the coding state transition diagram is 8B / 10B coded with various transitions such as 111-100-111 and 100-010-100 when transitioning from one state to another state. Represents a packet response. As shown in FIG. 15, the longest transition occurs when the coded packet transitions between 000-111-000. These longest transitions create a wide eye opening that adversely affects high-speed data transmission. This is because the longer the voltage transition, the longer the signal is to reach the proper voltage signal and consequently the proper code state.

  FIG. 16 is a (3-bit) coding transition diagram according to a preferred embodiment of the present invention. Referring to FIG. 16, a coding system according to a preferred embodiment of the present invention represents one or more additional voltage levels compared to an existing coding system, eg, 8B / 10B coding. One or more additional codes can be included, eg, SSS and TTT. The SSS code can represent a predetermined voltage level that is substantially closer to the voltage level represented by the 000 code than the voltage level represented by the 111 code. For example, when a 000 code represents 1.2V and a 111 code represents 1.8V, the SSS code can represent a voltage level of 1.0V. Similarly, the TTT code can represent a predetermined voltage level that is substantially closer to the voltage level represented by the 000 code than the 111 code. For example, when the 000 code represents 1.2V and the 111 code represents 1.8V, the TTT code can represent 0.9V.

  A coding system according to a preferred embodiment of the present invention provides a data pattern representing an undesirable high frequency operation, such as 000-111-000 data pattern, a data pattern representing a desired high frequency operation, eg, 000-TTT-000 data. It can be replaced by a pattern. In other words, the coding system according to the preferred embodiment of the present invention replaces the longest voltage transition between 000-111 with a shorter voltage transition of 000-TTT. At this time, the TTT code represents a voltage level closer to the voltage level appearing by 000 than the voltage level represented by 111. As a result, short transition times minimize data skew and improve high frequency operation.

  FIG. 17 is a circuit diagram of a data transmission system 300 according to a preferred embodiment of the present invention. Referring to FIG. 17, the data transmission system 300 receives the digital signal DATA_IN and uses the encoder 304 and the transmission unit 306 that converts each encoded digital value into an analog value applied to the channel. A memory system 200 that converts the analog signal DATA into a transmittable analog signal DATA.

  The control unit 312 receives a channel signal from the transmission unit 306 through an analog data channel. The control unit 312 includes a receiving unit 314 that converts an analog signal into an encoded digital value, and a level decoder 316 that decodes the digital value.

  The illustrated data can be encoded into an analog signal and converted by the encoder 320 and the transmission unit 318 for transmission from the control unit 312 to the memory 302. The receiving unit 310 and the decoder 308 both receive an analog signal, convert it into an encoded digital value, and decode the digital value in order to provide decoded digital information.

  Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and various modifications and equivalent other embodiments may be made by those skilled in the art. You will understand. Therefore, the technical scope of the present invention must be determined based on the description of the scope of claims.

  The present invention can be applied to a data transmission system that realizes high-speed operation by minimizing data skew with a short transition time.

1 is a block diagram of an exemplary data transmission system 100. FIG. FIG. 6 is a voltage amplitude diagram over time for 8B / 10B coded data. It is an 8B / 10B coding state transition diagram. 2 is a coding state transition diagram according to a preferred embodiment of the present invention. 2 is a block diagram of a data transmission system 200 according to a preferred embodiment of the present invention. 6 is a block diagram showing an embodiment of the level decoder 206 shown in FIG. FIG. 7 is a block diagram showing an embodiment of the level encoder 205 shown in FIGS. 5 and 6. FIG. 6 is a block diagram according to an embodiment of the level encoder 205 and the DAC 206 shown in FIG. 6 is a block diagram according to the embodiment of DAC 206 shown in FIG. 4 is a coding table associated with a transmission unit 202 according to an exemplary embodiment of the present invention. 6 is a block diagram according to an embodiment of ADC 208 shown in FIG. 4 is a coding table associated with a receiving unit 204 according to a preferred embodiment of the present invention. 6 is a block diagram according to an embodiment of the level decoder 209 shown in FIG. 6 is a specific block diagram according to an embodiment of the level decoder 209 shown in FIG. It is an 8B / 10B coding state transition diagram. 3 is a coding transition diagram according to a preferred embodiment of the present invention. 3 is a block diagram of a data transmission system 300 according to another preferred embodiment of the present invention.

Explanation of symbols

200 Data Transmission System 202 Transmission Unit 204 Reception Unit 205 Level Encoder 206 DAC
208 ADC
209 Level decoder DATA_IN, DATA_OUT Digital signal DATA Analog signal

Claims (26)

In a method of coding digital data for transmission to an analog channel,
Determining a first data transition;
Generating a code including at least one additional level to minimize data skew in the first data transition;
Coding the first data transition at an additional level in the code. The step of determining the first data transition includes:
The data coding method according to claim 1, further comprising the step of determining a data transition from low to high. The step of determining includes
3. The data coding method according to claim 2, further comprising the step of determining a transition from the lowest level to the highest level. The step of determining includes
The method of claim 2, comprising determining a transition between 00 and 10. The step of generating the code comprises:
The method of claim 2, comprising generating a code having an additional SS level. Generating the code at the additional SS level comprises:
6. The data coding method according to claim 5, further comprising the step of generating the SS level which is closer to 00 level than 10 level. The data coding method includes:
The method of claim 2, further comprising: coding the digital data from a first code to a second code including at least one level. Coding the digital data comprises:
Applying the coded digital data to an input of an N-bit digital / analog converter;
The output of the conversion unit, the data according to claim 7, characterized in that it comprises the steps of generating a level obtained by adding at least one level which is different from the 2 ^N pieces of level to the the 2 ^N levels Coding method. An input for receiving a data segment coded using a first code and the 2 ^N voltage levels to determine a data segment transition and to minimize data skew within the data segment transition 2 a level having an output for providing a second data code, adding a code comprising at least one voltage level different from the ^N voltage levels and coding the data segment transition at an additional level in the code An encoder,
A converter for converting the second data code into a voltage level;
And a control unit that outputs to supply the voltage level.   The system of claim 9, wherein the level encoder receives a data segment in a first code and provides a data segment in the second code. The first code includes 1 and 0,
The system of claim 10, wherein the second code includes 1, 0 and S. The level encoder is
A serial / parallel converter for converting serial data segments in the first code into parallel data segments in the first code;
An input latch for latching the parallel data segments in the first code;
A coding block for coding the parallel data segment in the first code with the parallel data segment in the second code;
An output latch for latching the parallel data segments in the second code;
The system according to claim 9, further comprising: a parallel / serial converter configured to convert the parallel data segment in the second code into a serial data segment in the second code. The converter is
A pre-driver for receiving a data segment in the second code;
The system according to claim 9, further comprising a multi-level driver that generates a voltage level corresponding to the pre-driver. The system
A second converter for converting the voltage level into a second data code;
The system of claim 9, further comprising a level decoder having an input for receiving the second data code and an output for providing a data segment in the second data code. . In the memory system,
A control unit;
A memory device,
The controller is
An input for receiving a data segment, the 2 ^N-number of voltage levels, to determine the data segment transitions, different from the for minimizing data skew of the data segment in the transition, the 2 ^N pieces of voltage levels An output for providing a data code coding the data segment transition at an additional level in the code, indicating one voltage level assigned to each data segment among the voltage levels to which at least one voltage level has been added; A level encoder having
A first converter for converting the data code into each voltage level;
A controller for outputting to supply the voltage level,
The memory device includes:
An input for receiving the voltage level from the controller;
A second converter for converting the voltage level into a data code;
A memory system comprising: a level decoder having an input for receiving the data code and an output for supplying the data code. The memory device includes:
An analog channel connected to the control unit;
The memory system according to claim 15, further comprising a memory to which the voltage level is applied. The level encoder is
16. The memory system of claim 15, wherein the at least one additional voltage level is assigned to a low to high transition. The level encoder is
The memory system of claim 17, wherein the at least one additional voltage level is assigned to a transition from a lowest level to a highest level. The at least one additional voltage level is
18. The memory system of claim 17, wherein the memory system is closer to 00 level than 10 level. The first converter is
N-bit digital / analog converter,
The memory of claim 15 in which the voltage level obtained by adding a different at least one voltage level and the 2 ^N pieces of level the the 2 ^N levels, characterized by generating as an output of the first converter system. The second converter is
N-bit digital / analog converter,
A voltage level obtained by adding a different at least one voltage level and the 2 ^N-number of voltage levels the 2 ^N pieces of voltage levels, according to claim 15, characterized in that to generate as an output of the second converter Memory system. In systems that transmit digital data segments to analog channels,
Wherein each data segment, 2 ^N-number of voltage levels (N is the number of bits in each data segment), the determining data segment transitions, to minimize data skew of the data segment in the transition, the 2 ^N A level encoder for assigning a code corresponding to one of the voltage levels to which at least one voltage level different from the voltage level is added
And a digital / analog converter for converting the code into each voltage level. The system
An analog / digital converter that receives the voltage level after transmission through the analog channel and converts it into a corresponding code;
The system of claim 22, further comprising a level decoder that converts the code back into a corresponding data segment.   The system of claim 23, wherein the code minimizes data skew. The level encoder is
A serial / parallel converter for converting serial data segments into parallel data segments;
An input latch for latching the parallel data segments;
A coding block for coding the parallel data segments with the code;
An output latch for latching the coded parallel data segments;
23. The system of claim 22, further comprising: a parallel / serial converter that converts the coded parallel data segment into a coded serial data segment. The digital / analog converter is
A pre-driver for receiving the coded serial data segment;
23. The system of claim 22, including a multi-level driver that generates a voltage level corresponding to the pre-driver.