KR20050098625A - Driving method of plasma display panel and plasma display device - Google Patents

Abstract

A driving method of the plasma display panel of the present invention. Scan pulses Y are applied to the scan electrodes Y for applying scan pulses, and the scan pulses are simultaneously applied. At this time, the voltage biased to the sustain electrode is adjusted so that addressing occurs only for the discharge cells formed on one of the two scan electrodes. The scan pulse is simultaneously applied to the scan electrode Y once more, and at this time, the voltage biased to the sustain electrode is adjusted to address the discharge cells formed on the scan electrodes not previously selected to the simultaneously bundled scan electrodes. This can be applied to the structure of not only three electrodes but also four electrodes. Through this, the number of scan ICs applying the scan pulse can be reduced.

Description

Plasma display panel driving method and plasma display device {DRIVING METHOD OF PLASMA DISPLAY PANEL AND PLASMA DISPLAY DEVICE}

The present invention relates to a method of driving a plasma display panel (PDP).

Recently, flat panel display devices such as liquid crystal displays (LCDs), field emission displays (FEDs), and plasma displays have been actively developed. Among these flat panel display devices, the plasma display device has advantages of higher luminance and luminous efficiency and a wider viewing angle than other flat panel display devices. Therefore, the plasma display device is in the spotlight as a display device to replace the conventional cathode ray tube (CRT) in a large display device of 40 inches or more.

Plasma display devices are flat display devices that display characters or images using plasma generated by gas discharge, and dozens to millions or more of pixels are arranged in a matrix form according to their size. The plasma display device is classified into a direct current type (DC type) and an alternating current type (AC type) according to the shape of a driving voltage waveform to be applied and the structure of a discharge cell.

In the DC plasma display device, since the electrode is exposed to the discharge space as it is, the current flows in the discharge space while the voltage is applied, and there is a disadvantage in that a resistance for current limitation must be made for this purpose. On the other hand, in the AC plasma display device, since the electrode covers the dielectric layer, the current is limited by the formation of a natural capacitance component, and thus the electrode is protected from the impact of ions during discharge.

1 is a partial perspective view of a conventional AC plasma display panel, and FIG. 2 is a cross-sectional view of the plasma display panel shown in FIG. 1.

1 and 2, the X electrode 3 and the Y electrode 4 covered with the dielectric layer 14 and the passivation layer 15 are arranged in parallel on the first glass substrate 11. At this time, the X electrode and the Y electrode is made of a transparent conductive material. Bus electrodes 6 made of metal materials are formed on the surfaces of the X and Y electrodes 3 and 4, respectively.

A plurality of address electrodes 5 are provided on the second glass substrate 12, and the address electrodes 5 are covered by the dielectric layer 14 '. A partition 17 is formed on the dielectric layer 14 ′ between the address electrodes 5 in parallel with the address electrode 5. In addition, phosphors 18 are formed on the surface of the dielectric layer 14 'and on both sides of the partition wall 17. The first glass substrate 11 and the second glass substrate 12 have a discharge space 19 therebetween so that the Y electrode 4 and the address electrode 5 and the X electrode 3 and the address electrode 5 are orthogonal to each other. Are placed opposite to each other. The discharge space at the intersection of the address electrode 5 and the paired Y electrode 4 and the X electrode 3 forms a discharge cell 19.

3 shows an electrode arrangement diagram of a conventional plasma display device.

As shown in FIG. 3, the conventional plasma display electrode has a matrix configuration of m> n. The address electrodes A ₁ to _Am are arranged in the column direction, and the n electrodes Y ₁ to Y _n and the X electrodes X ₁ to X _n are arranged in a zigzag pattern in the row direction. The discharge cell 20 shown in FIG. 3 corresponds to the discharge cell 19 shown in FIG.

4 is a driving waveform diagram of a conventional plasma display panel.

According to the driving method of the plasma display panel shown in Fig. 4, each subfield is composed of a reset period, an address period, and a sustain period.

The reset period serves to erase the state of the wall charge of the previous sustain discharge and to set up the wall charge in order to stably perform the next address discharge.

The address period is a period in which wall charges are accumulated in cells to be turned on (addressed cells) by selecting cells to be turned on and cells not to be turned on.

The sustain period is a period in which a sustain discharge voltage is alternately applied to the X electrode and the Y electrode to perform a discharge to actually display an image in a cell to be addressed in the address period.

Hereinafter, the operation of the address period of the conventional plasma display panel driving method will be described in detail.

Address period, and applies a sequential scan electrode (Y _j) an address electrode (A _i) address voltage (Va) of the cells to be displayed from time to apply the scan voltage (0V), the scan electrode (Y _j) a. At this time, the address electrode (A _i) the scan electrode (Y _j) a discharge is caused to sound to the address electrode (A _i) in-turn by being the wall of the charge, the positive wall charges are formed on scan electrodes (Y _j) () The cell to be selected is selected. This operation is sequentially performed on all scan electrodes Y _j to select cells to be displayed on the entire screen. Here, in order to apply a scan voltage (0V) in order to all the scanning electrodes (Y _j) should be present in each of the scan IC for each scanning electrode (Y _j). Therefore, a large number of scan ICs are required, and more scan ICs are required to drive a large screen, thereby increasing the cost burden.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the above problems of the related art, and to provide a method of driving a plasma display panel which reduces a scan IC.

A driving method of a plasma display panel according to a feature of the present invention for achieving the above object is

A driving method of a plasma display panel comprising a plurality of first electrodes and a second electrode, wherein a discharge cell is formed by the first electrode and the second electrode.

In the address period,

(a) simultaneously applying a scan pulse voltage to any two first-first and one-second electrodes of the plurality of first electrodes;

(b) applying a first voltage to a second electrode corresponding to the first-first electrode while the scan pulse voltage is applied; And

(c) applying a second voltage lower than the first voltage to a second electrode corresponding to the first-second electrode while the scan pulse voltage is applied.

The driving method of the plasma display panel according to another aspect of the present invention

A driving method of a plasma display panel comprising a plurality of first electrodes and a second electrode, wherein a discharge cell is formed by the first electrode and the second electrode.

In the address period,

(a) applying a scan pulse voltage to any one-first electrode of the plurality of first electrodes during a first period;

(b) applying a scan pulse voltage to the first-first electrode again during the second period;

(c) applying a first voltage to a second electrode corresponding to the first-first electrode while the scan pulse voltage is applied in step (a); And

(d) applying a second voltage lower than the first voltage to the second electrode corresponding to the first-first electrode while the scan pulse voltage is applied in the step (b).

A driving method of a plasma display panel according to another aspect of the present invention is

A method of driving a plasma display panel comprising a plurality of first electrodes and a second electrode to which a sustain discharge pulse is applied, and a plurality of third electrodes formed between the first electrode and the second electrode, respectively.

In the address period,

(a) simultaneously applying a scan pulse voltage to any two 3-1 and 3-2 electrodes of the plurality of third electrodes:

(b) applying a first voltage to a first electrode corresponding to the third-1 electrode while the scan pulse voltage is applied; And

(c) applying a second voltage higher than the first voltage to the first electrode corresponding to the third-2 electrode while the scan pulse voltage is applied.

A driving method of a plasma display panel according to another aspect of the present invention is

 A method of driving a plasma display panel comprising a plurality of first electrodes and a second electrode to which a sustain discharge pulse is applied, and a plurality of third electrodes formed between the first electrode and the second electrode, respectively.

In the address period,

(a) applying a scan pulse voltage to any 3-1 electrode of the plurality of third electrodes during a first period;

(b) applying a scan pulse voltage to the 3-1 electrode again during the second period;

(c) applying a first voltage to a first electrode corresponding to the third-1 electrode while a scan pulse voltage is applied in step (a); And

(d) applying a second voltage higher than the first voltage to the first electrode corresponding to the third-1 electrode while the scan pulse voltage is applied in the step (b).

Plasma display device according to another aspect of the present invention

First substrate,

A plurality of first electrodes and second electrodes formed on the first substrate, respectively;

A second substrate facing away from the first substrate,

A plurality of third electrodes formed on the second substrate in a direction crossing the first and second electrodes, and

A driving circuit for supplying a driving voltage to the first electrode, the second electrode, and the third electrode to discharge the discharge cells formed by the adjacent first, second, and third electrodes;

The driving circuit may be configured to bias a first voltage to one first electrode of any two first electrodes and a second voltage lower than the first voltage to the other first electrode in an address period. The scan pulse voltage is simultaneously applied to the two arbitrary first electrodes and the corresponding second electrode.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

First, a driving method of the plasma display panel according to the first embodiment of the present invention will be described in detail with reference to FIG. 5. In the following description, reference numerals denoted by the address electrodes A ₁ -A _m , the scan electrodes Y ₁ -Y _n , and the sustain electrodes X ₁ -X _n denote the address electrodes, the scan electrodes, and the sustain electrodes. The same voltage is applied, and the display of the address electrode A _i and the scan electrode Y _j indicates that only a portion of the address electrode and the scan electrode are applied.

5 is a driving waveform diagram of a plasma display panel according to a first embodiment of the present invention.

As shown in Fig. 5, the drive waveform according to the first embodiment of the present invention includes a reset period, an address period, and a sustain period. In the plasma display panel, a scan / hold driving circuit (not shown) and an address electrode A ₁ -which apply driving voltages to the scan electrodes Y ₁ -Y _n and the sustain electrodes X ₁ -X _n in each period. An address driving circuit (not shown) for applying a driving voltage is connected to A _n ). The driving circuit and the plasma display panel are connected to form one plasma display device.

The reset period is a period for removing wall charges formed in the sustain period, and the address period is a period for selecting a cell to be displayed from the discharge cells. The sustain period is a period for discharging the cell selected in the address period.

As shown in FIG. 5, the driving waveform diagram according to the first exemplary embodiment of the present invention maintains the voltages applied to the sustain electrodes X _1- X _n in the address period to hold the sustain electrodes X _odd of the odd lines and the even lines. Each of the electrodes X _even is applied at a different voltage. That is, the maintenance of the odd lines in the address period, the electrodes (X _odd) is the cell voltage and then primarily addressing the cells of the odd lines by applying varying the contact pressure applied to the sustain electrode (X _even) of the even lines the even-numbered line to the Perform addressing. In addition, the period in which the scan voltage (0V) is applied to the scan electrodes (Y ₁ -Y _n ) in the address period is divided into two sections (I, II), and in the first period (I), the scan electrodes (Y ₁ -Y _n). ) and applies a scan voltage (0V) is applied to all the scanning electrodes (Y ₁ -Y _n) the second section (ⅱ) again to all the scanning electrodes (Y ₁ -Y _n) to then be applied to the.

Hereinafter, a waveform applied to each period (reset period, address period, sustain period) of an arbitrary subfield in the plasma display panel driving method according to the first embodiment of the present invention will be described in more detail.

In the reset period, the sustain discharge voltage Vs is applied to the scan electrodes Y ₁ -Y _n in a state in which a constant potential Ve is biased to both the sustain electrode X _odd of the odd line and the sustain electrode X _even of the even line. ), A ramp that slowly drops to ground potential (0V) is applied to remove wall charges formed in the previous holding period. Next, the sustain electrodes X _odd of the odd lines and the sustain electrodes X _even and the address electrodes A ₁ -A _m of the even lines are kept at 0 V and gently risen to the scan electrodes Y1-Yn. Apply lamp voltage. While this ramp voltage is rising, fine reset discharges occur from the scan electrodes Y ₁ -Y _n to the address electrodes A ₁ -A _m and the sustain electrodes X _odd and X _even , respectively, in all the discharge cells. As a result, negative wall charges are accumulated on the scan electrodes Y ₁ -Y _n , and at the same time, positive wall charges are stored on the address electrodes A ₁ -A _m and the sustain electrodes X _odd and X _even . Wall charges accumulate. Subsequently, during the second half of the reset period, the ramp ramps slowly from the scan electrodes Y ₁ -Y _n voltage Vs to the ground voltage (0 V) while the sustain electrode (including both X _odd and X _even ) is biased. Apply voltage. While this ramp voltage is falling, again, a weak reset discharge is generated in all the discharge cells, resulting in an addressable wall charge state.

Next, in the address period, the driving waveform is applied differently by dividing into two sections I and II, which will be described in detail below.

(1) First section (Ⅰ)

In the first section I, the scan electrodes Y ₁ -Y are biased with the constant voltage Ve biased to the sustain electrode X _{odd of} the odd line and the ground voltage 0V biased to the sustain electrode X _even of the odd line. _n is sequentially applied to the scan voltage (0V). At this time, Y ₁ , Y ₂ , Y ₃ , Y _4, and the like are respectively connected to the scan ICs in the scan electrodes Y ₁ -Y _n , so that a scan pulse voltage (0 V) is simultaneously applied. That is, the scan electrodes Y ₁ and Y _2, for example, Y ₁ and Y ₂ is applied is connected to one scan IC scan pulse voltage (0V) at the same time. Here, the data voltage Va for the odd line is applied to the address electrode A _i while the scan pulse voltage 0 V is sequentially applied to the scan electrodes Y _1- Y _n . That is, a data voltage Va for addressing a cell to be selected among the cells of the odd lines is applied to the first period I.

As described above, while the constant voltage Ve is biased to the sustain electrode X _{odd of} the odd line and the ground voltage is biased to the sustain electrode X _even of the even line, the scan pulse voltage and the scan electrodes Y1 to Yn are sequentially address electrode address voltage (Va) to (a _i) (This data voltage being on the odd-numbered line) discharges only in cells of the hole number of lines by applying (i.e., the discharge to the scan electrodes (Y _j) at the address electrode (a _i) Is generated and a discharge is generated from the sustain electrode X _odd to the scan electrode Y _j ) to perform addressing. Here, even if the scan pulse voltage (0V) is applied to the even-numbered cells, since the voltage of 0V is biased to the sustain electrode (X _even ) of the even-numbered lines, addressing does not occur effectively. For example, even if the scan electrodes Y ₁ and Y ₂ are connected to one scan IC and the scan pulse voltage (0 V) is applied at the same time, a voltage of 0 V is biased to the even electrode sustain electrode (X _even ). The addressing operation is not performed in the cells of the even line.

In other words, by applying the ground voltage (0V) to the sustain electrode (X _even ) of the even lines in the first period (I) of the address period, addressing operation does not occur in the cells of the even lines, but only the cells of the odd lines The action occurs.

(2) Second section (Ⅱ)

In the second period (II) of the address period, the Ve voltage is biased to the sustain electrode (X _even ) of the even line and the ground voltage (0V) is biased to the sustain electrode (X _odd ) of the odd line as opposed to the first period (I). In one state, scan pulse voltages 0V are sequentially applied to scan electrodes Y1-Yn. In this case, while the scan pulse voltage 0V is sequentially scanned in the second section II, the data voltage Va for the odd line is applied to the address electrode A _i . As described above, in the second period (II), the scan pulse voltage (0V) is applied to the scan electrodes (Y ₁ -Y _n ) while the Ve voltage is biased only to the sustain electrodes (X _even ) of the even lines. A valid address discharge is generated to perform the addressing operation.

In this way, addressing is performed for all the discharge cells in two sections I and II of the address period.

Next, in the sustain period, sustain discharge is performed to discharge the addressed cells in the address period by applying sustain voltage Vs to the sustain electrodes X _odd and X _even and the scan electrodes Y ₁ -Y _n alternately. . At this time, the waveforms applied to the sustain electrodes (X _odd and X _even ) and the scan electrodes (Y ₁ -Y _n ) in the sustain discharge period are preferably a symmetrical waveform.

In order to perform the addressing discharge of the appropriate address period by applying the driving waveform of the first embodiment of the present invention as shown in FIG. 5, the scan electrodes Y ₁ -Y _n must be connected to one scan IC every two lines. The sustain electrode driver should be divided into two sustain electrode drivers.

FIG. 6 is a diagram illustrating a configuration of a scan IC and a structure of a sustain electrode driver required to apply the driving waveform shown in FIG. 5.

FIG scan electrode as shown in _{6 (Y 1 -Y n) Y} 1 and Y ₂ at the same time is connected to the SCAN IC 1, Y ₃ and Y ₄ are connected to the SCAN IC 2 ... and Y _n-1 Y _n is connected to SCAN IC n / 2. In this way, two scan electrode lines are simultaneously connected to the scan IC so that a scan pulse voltage (0V) is simultaneously applied in the address period. In addition, since the voltages applied to the sustain electrodes X _odd of the odd lines and the sustain electrodes X _even of the even lines are different in the address period as described with reference to FIG. 5, the sustain electrode driving unit has an X _odd electrode as shown in FIG. 6. and a driver and _even X electrode driver, the sustain electrodes X of the _odd electrode drive has odd lines _{(X 1, X 3, X} 5 ... X n-1) this connection is maintained _even in the even-numbered line X electrodes, the driving electrodes (X ₂ , X ₄ ... X _n ) are connected.

In this way, two sustain electrodes (Y ₁ -Y ₂ , Y ₃ -Y ₄ , ... Y _n-1 -Y _n ) are connected to one scan IC, and the voltage applied to the sustain electrodes in the address period is an odd line. By differentiating the sustain electrode X _odd and the even electrode sustain electrode X _even , the number of scan ICs can be reduced to 1/2 of the conventional one. In the address period, the scan is performed twice for each line, but since the two sustain electrodes are applied with the scan voltage by one scan IC, the address period is the same as the previous period.

At this time, in the driving method of the plasma display panel according to the first embodiment of the present invention, the sustain electrode (X ₁ -X _n ), the scan electrode (Y ₁ -Y _n ) and the address electrode (A ₁ -A _m ) Although the present invention was applied to the plasma display panel of the electrode, the same method can be applied to the case of four electrodes having an M electrode which is an intermediate electrode between the X electrode and the Y electrode.

7 is a diagram illustrating an arrangement of four electrodes of a plasma display panel according to an exemplary embodiment of the present invention.

7, the plasma display according to an embodiment of the present invention includes an address electrode in the column direction (A ₁ ~ A _m) are arranged parallel to and, n / 2 + Y electrodes of the first line (Y _1, Y _{n / 2 + 1} ), X electrodes (X ₁ to X _{n / 2 + 1} ), and an intermediate electrode (hereinafter 'M electrode') in n rows are arranged. That is, according to the embodiment of the present invention, the M electrode is arranged in the middle of the Y electrode and the X electrode, and the Y electrode, the X electrode, the M electrode, and the address electrode have a four-electrode structure in which one discharge cell 30 is formed. .

At this time, according to the embodiment of the present invention, the X electrode and the Y electrode mainly serve as an electrode for applying a sustain discharge voltage waveform, and the M electrode mainly serves for applying a reset waveform and a scan pulse voltage.

8 illustrates a driving waveform diagram of a plasma display panel according to a second exemplary embodiment of the present invention.

According to the driving waveform according to the second embodiment of the present invention shown in Fig. 8, each subfield is composed of a reset period, an address period, and a sustain period. At this time, unlike the first embodiment, the reset waveform and the scan pulse voltage are applied to the M electrode instead of the Y electrode.

In the reset period, the period of erasing the wall charges formed in the sustain period (this is performed by applying a gently falling voltage to the M electrode), and a period of applying a gently rising waveform and a gently falling waveform to the M electrode is reset. Perform the action. At this time, the ground voltage (0V) is applied to the X electrode (including both X _odd and X _even ), and the ground voltage (0V) is applied to the Y electrode, and the voltage is gently lowered in the section in which the slowly rising voltage is applied to the M electrode. In the period of applying, reset discharge is performed by biasing the Vxe voltage to the X electrode (including both X _odd and X _even ) and the Vyc voltage to the Y electrode.

Next, the address period includes two sections I-1 and II-1 similarly to the first embodiment of the present invention.

In the first section (I-1), the grounding voltage (0V) is applied to the X electrode (X _odd ) of the _odd line, and the Vxe voltage is applied to the X electrode (X _even ) of the even line, so that the addressing operation is performed only for the cells of the odd line. Bias. At this time, the V electrode is biased with a Vyc voltage (that is, a voltage higher than the voltage applied to the X _odd electrode). Here, the voltage Vyc applied to the Y electrode is higher than the ground voltage (0 V) between the X electrodes (X _odd ) of the odd lines, so that appropriate addressing occurs only for the cells of the _odd lines. In addition, since the Vxe voltage is biased to the X electrode X _even of the even line, proper addressing does not occur in the cells of the even line.

In addition, in the second section II-1, the voltage applied to the X electrode X _odd of the odd lines and the X of the even lines is performed so that the addressing operation is performed only on the cells of the even lines as opposed to the first section I-1. The voltage applied to the electrode X _even is opposite to the first period I-1.

Here, the scan pulse voltage is sequentially applied to the M electrodes M ₁ -M ₂ , M ₃ -M ₄ ... in the first section I-1, and then sequentially in the second section II-1. The scan pulse voltage is applied to the M electrodes (M ₁ -M ₂ , M ₃ -M ₄ ..). In addition, adjacent M electrodes (eg, M ₁ -M ₂ ) are connected to one scan IC so that a scan pulse voltage is applied at the same time.

In this manner, by properly combining the voltages applied to the X _odd electrode and the X _even electrode in the address period, _{even if the} scan pulse voltage is simultaneously applied to two adjacent M electrodes M ₁ -M ₂ , only the cells of odd or even lines are used. The addressing operation is performed. This allows the scan IC to be reduced to half the conventional size. That is, although not shown in the drawing, in the second embodiment of the present invention, two ICs are connected to one IC, and the driving unit of the X electrode also includes two driving units (X _odd electrode driving unit and X _even electrode driving unit). .

In the sustain period, the sustain cell is discharged by selecting the sustain voltage Vs alternately between the X electrode and the Y electrode.

At this time, when driving the plasma display panel with four electrodes as in the second embodiment of the present invention, since the X electrode and the Y electrode are symmetrical with each other, when the ground voltage (0 V) is applied to the Y electrode in the address period, the X electrode It can be seen that the voltage applied to the reverse to FIG. In this case, however, the sustain discharge voltage Vs must be applied to the Y electrode first.

In the first and second embodiments of the present invention, one scan of two adjacent scanning electrodes (Y1-Y2, Y3-Y4, etc.) or two M electrodes (M ₁ -M ₂ , M ₃ -M _4, etc.) The scan pulse voltage is applied simultaneously with the IC, but any two electrodes may be bundled and connected to the scan IC to apply the scan pulse voltage in the same manner as the present invention. In this case, however, the X electrodes are also bundled differently from each other and connected to the two X electrode driving units, and the address data applied in the address period should be appropriately adjusted accordingly. Detailed description thereof will be appreciated by those skilled in the art and will be omitted below.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, the number of scan ICs applying the scan voltage can be reduced by appropriately applying the voltage applied to the X electrode in the address period.

1 is a perspective view of a conventional plasma display panel.

FIG. 2 is a cross-sectional view of the plasma display panel shown in FIG. 1.

3 is an electrode array diagram of a conventional plasma display device.

4 is a driving waveform diagram of a conventional plasma display panel.

5 is a driving waveform diagram of a plasma display panel according to a first embodiment of the present invention.

FIG. 6 is a diagram illustrating a configuration of a scan IC and a structure of a sustain electrode driver required to apply the driving waveform shown in FIG. 5.

7 is a diagram illustrating an arrangement of four electrodes of a plasma display panel according to an exemplary embodiment of the present invention.

8 is a driving waveform diagram of a plasma display panel according to a second embodiment of the present invention.

Claims (18)

A driving method of a plasma display panel comprising a plurality of first electrodes and a second electrode, wherein a discharge cell is formed by the first electrode and the second electrode. In the address period, (a) simultaneously applying a scan pulse voltage to any two first-first and one-second electrodes of the plurality of first electrodes; (b) applying a first voltage to a second electrode corresponding to the first-first electrode while the scan pulse voltage is applied; And and (c) applying a second voltage lower than the first voltage to a second electrode corresponding to the first-second electrode while the scan pulse voltage is applied. The method of claim 1, The plasma display panel further includes a plurality of third electrodes crossing the first and second electrodes. And applying a third voltage higher than the scan pulse voltage to the third electrode of a discharge cell to be selected from among the discharge cells formed by the first-first electrode while the scan pulse voltage is applied. How to drive the display panel. The method of claim 1, And the first-first electrode and the first-second electrode are adjacent electrodes. The method according to claim 1 or 3 And the first-first electrode and the first-second electrode are connected to one scan IC. The method according to claim 1 or 3, The second electrode corresponding to the first-first electrode is adjacent to the first-first electrode and formed side by side, and the second electrode corresponding to the first-second electrode is adjacent to the first-second electrode and side by side And a plasma display panel driving method. A driving method of a plasma display panel comprising a plurality of first electrodes and a second electrode, wherein a discharge cell is formed by the first electrode and the second electrode. In the address period, (a) applying a scan pulse voltage to any one-first electrode of the plurality of first electrodes during a first period; (b) applying a scan pulse voltage to the first-first electrode again during the second period; (c) applying a first voltage to a second electrode corresponding to the first-first electrode while the scan pulse voltage is applied in step (a); And (d) driving a plasma display panel including applying a second voltage lower than the first voltage to a second electrode corresponding to the first-first electrode while the scan pulse voltage is applied in step (b). Way. The method of claim 6, In the step (a), the discharge cell formed by the first-first electrode is selected while the scan pulse voltage is applied, and in the step (b), the discharge cell is selected. And the discharge cells formed are not selected. The method of claim 6, The scan pulse voltage applied in the step (a) is simultaneously applied to the 1-2 electrodes adjacent to the 1-1st electrode, and is applied to the second electrode corresponding to the 1-2 electrodes during the first period. And applying a third voltage lower than the first voltage.  The method of claim 8, The scan pulse voltage applied in step (b) is simultaneously applied to the 1-2 electrodes, and a fourth voltage higher than the second voltage is applied to a second electrode corresponding to the 1-2 electrodes during the second period. And driving the plasma display panel. The method of claim 9, And the first voltage and the fourth voltage have the same voltage level. A method of driving a plasma display panel comprising a plurality of first electrodes and a second electrode to which a sustain discharge pulse is applied, and a plurality of third electrodes formed between the first electrode and the second electrode, respectively. In the address period, (a) simultaneously applying a scan pulse voltage to any two 3-1 and 3-2 electrodes of the plurality of third electrodes: (b) applying a first voltage to a first electrode corresponding to the third-1 electrode while the scan pulse voltage is applied; And and (c) applying a second voltage higher than the first voltage to a first electrode corresponding to the third-2 electrode while the scan pulse voltage is applied.  The method of claim 11, And applying a third voltage higher than the first voltage to the plurality of second electrodes. The method according to claim 11 or 12, wherein And the 3-1 electrode and the 3-2 electrode are adjacent electrodes.  A method of driving a plasma display panel comprising a plurality of first electrodes and a second electrode to which a sustain discharge pulse is applied, and a plurality of third electrodes formed between the first electrode and the second electrode, respectively. In the address period, (a) applying a scan pulse voltage to any 3-1 electrode of the plurality of third electrodes during a first period; (b) applying a scan pulse voltage to the 3-1 electrode again during the second period; (c) applying a first voltage to a first electrode corresponding to the third-1 electrode while a scan pulse voltage is applied in step (a); And (d) applying a second voltage higher than a first voltage to a first electrode corresponding to the third-1 electrode while the scan pulse voltage is applied in step (b). . The method of claim 14, And applying a third voltage higher than the first voltage to the second electrode. The method according to claim 14 or 15, The plasma display panel further includes a fourth electrode formed to cross the first electrode and the second electrode. Applying a fourth voltage higher than the scan pulse voltage to the fourth electrode such that the discharge cells formed on the first-first electrode are selected while the scan pulse voltage is applied in the step (a); And applying the fourth voltage to the fourth electrode such that the discharge cells formed on the 1-2 electrodes are selected while the scan pulse voltage is applied in the step (b). . First substrate, A plurality of first electrodes and second electrodes formed on the first substrate, respectively; A second substrate facing away from the first substrate, A plurality of third electrodes formed on the second substrate in a direction crossing the first and second electrodes, and A driving circuit for supplying a driving voltage to the first electrode, the second electrode, and the third electrode to discharge the discharge cells formed by the adjacent first, second, and third electrodes; The driving circuit may be configured to bias a first voltage to one first electrode of any two first electrodes and a second voltage lower than the first voltage to the other first electrode in an address period. And simultaneously applying scan pulse voltages to the two arbitrary first electrodes and the second electrodes corresponding to the first and second electrodes. The method of claim 17, The driving circuit may be configured to bias a third voltage lower than the second voltage to the one first electrode and bias a fourth voltage higher than the third voltage to the other first electrode in an address period. And applying a scan pulse voltage to the second two electrodes corresponding to the two arbitrary first electrodes simultaneously.