KR20050098512A - Driving chip and display device having the same - Google Patents

Abstract

Disclosed are a driving chip and a display device having the same for reducing manufacturing costs and improving display characteristics. The first display panel displays the first image in response to the first driving signal, the second display panel displays the second image in response to the second driving signal, and the flexible film includes the first display panel and the second display panel. The driving chip is formed on the flexible film between the first display panel and the second display panel to output the first and second driving signals to the first and second display panels, respectively. Therefore, a driving chip is formed in the form of a COF between the main display panel and the sub display panel, and the main display panel and the sub display panel are driven by different driving methods, thereby reducing the manufacturing process and manufacturing cost. At the same time, the display characteristics of the sub-display panel can be improved.

Description

DRIVING CHIP AND DISPLAY DEVICE HAVING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving chip and a display device having the same, and more particularly, to a driving chip and a display device having the same to reduce manufacturing costs and to improve display characteristics.

Cellular phones have a flip type in which a liquid crystal display panel for displaying an image is exposed to the outside, and a folding type in which a liquid crystal display panel and a key input unit are opposed to each other by a hinge connected to the liquid crystal display panel and a key input unit for operating the cellular phone. .

The folding type is classified into a general folding type and a dual folding type according to the number of liquid crystal display panels. The dual clamshell type has a main liquid crystal display panel displaying a main image and a sub liquid crystal display panel displaying a standby image (e.g., time, date, reception sensitivity, etc.).

1 is a view schematically showing a general dual clamshell liquid crystal display device.

As shown in FIG. 1, a driving chip 120 for driving the main liquid crystal display panel 100 and the sub liquid crystal display panel 110 is integrally formed in one peripheral area of the main liquid crystal display panel 100.

In addition, a flexible printed circuit (FPC) 130 for electrically connecting the main liquid crystal display panel 100 and the sub liquid crystal display panel 110 is formed in the other peripheral area of the main liquid crystal display panel 100. In this case, the FPC 130 is formed such that one end thereof overlaps with the main liquid crystal display panel 100 by about 2 μm, and the other end thereof overlaps with the sub liquid crystal display panel 110 by about 2 μm.

The FPC 130 outputs the sub image signal applied through the main liquid crystal display panel 100 to the sub liquid crystal display panel 110 after being output from the driving chip 120. Accordingly, since the sub image signal is transmitted to the sub liquid crystal display panel 110 via the main liquid crystal display panel 100, a problem such as delay of the sub image signal occurs.

In addition, since the FPC requires an overlap area for connection between the main liquid crystal display panel and the sub liquid crystal display panel at one end and the other end, the size of the liquid crystal display device is also increased.

Accordingly, an object of the present invention is to solve the above problems, an object of the present invention to provide a driving chip for improving the display characteristics of the sub-display panel while reducing the manufacturing cost.

Another object of the present invention is to provide a display device having the driving chip.

The control unit of the present invention for achieving the above object outputs the first image signal and the first gate control signal in response to the raw image signal and the original control signal provided from the outside, or the second image signal and the second gate control signal The first driver outputs a first gate signal and a first data signal to the first display panel according to the first gate control signal and the first image signal, and the second driver outputs the second gate control signal and the second gate signal. The second gate signal and the second data signal are output to the second display panel according to the image signal.

In accordance with another aspect of the present invention, a first display panel of the present invention displays a first image in response to a first driving signal, and a second display panel displays a second image in response to a second driving signal. The flexible film connects the first display panel and the second display panel, and the driving chip is formed on the flexible film between the first display panel and the second display panel to display the first and second driving signals. Print each one to the panel.

According to such a driving chip and a display device having the same, a driving chip is formed in the form of a COF between the main display panel and the sub-display panel, and the main display panel and the sub-display panel are driven by different driving methods. Therefore, it is possible to reduce the manufacturing process and manufacturing cost and to improve the display characteristics of the sub-display panel.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram schematically illustrating a dual liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the dual liquid crystal display according to the exemplary embodiment of the present invention includes a main display panel 200 displaying main information, a sub-display panel 300 displaying atmospheric information, and the main display. And a driving chip 400 for driving the display panel 200 and the sub-display panel 300.

The driving chip 400 receives the raw image signal O-DATA and the raw control signal OCS from the CPU 500 which is an external device.

The driving chip 400 may drive various signals for driving the main display panel 200 and the sub display panel 300 in response to the raw image signal O-DATA and the raw control signal OCS. Output The signals output from the driving chip 400 may include a main image signal M-DATA, a sub image signal S-DATA, a main gate signal M-GS, and a sub gate signal S-GS.

The main display panel 200 receives a main image signal M-DATA and a main gate signal M-GS from the driving chip 400 to display a main image. The sub-display panel 300 receives a sub image signal S-DATA and a sub gate signal S-GS from the driving chip 400 to display a sub image.

3 is a plan view illustrating in detail the structure of the dual LCD shown in FIG. 2.

As illustrated in FIG. 3, the main display panel 200 includes a first display area DA1 displaying a main image and a first peripheral area PA1 adjacent to the first display area DA1. In the first display area DA1, a first gate line group GL1-1 to GL1-m including m gate lines and a first data line group including n data lines orthogonal to the m gate lines ( DL1-1 to DL1-n) are provided.

The sub-display panel 300 includes a second display area DA2 for displaying a sub image and a second peripheral area PA2 adjacent to the second display area DA2. In the second display area DA2, a second gate line group GL2-1 to GL2-k including k gate lines and a second data line group including j data lines orthogonal to the k gate lines ( DL2-1 to DL2-j) are provided. Where k and m are two or more natural numbers and k is a number less than or equal to m. J and n are two or more natural numbers, and j is a number less than or equal to n.

The size of the main display panel 200 is larger than that of the sub-display panel 300, and therefore, the size of the first display area DA1 is also larger than the size of the second display area DA2. In addition, the resolution of the first display area DA1 is higher than that of the second display area DA2.

The main display panel 200 includes a first lower substrate 210, a first upper substrate 220 facing the first lower substrate 210, and a first lower substrate 210 and a first upper substrate ( And a first liquid crystal layer (not shown) interposed therebetween. The sub-display panel 300 includes a second lower substrate 310, a second upper substrate 320 facing the second lower substrate 310, and a second lower substrate 310 and a second upper substrate ( And a second liquid crystal layer (not shown) interposed therebetween.

Here, the first peripheral area PA1 of the main display panel 200 includes the coupling area EA. The coupling area EA is an area in which the first lower substrate 210 extends longer than the first upper substrate 220.

The sub-display panel 300 is formed on the flexible film 600. That is, the flexible film 600 has an opening (not shown) formed at the center thereof to correspond to the second display area DA2 of the sub-display panel 300. Accordingly, the sub-display panel 300 is formed on the flexible film 600 so that the second display area DA2 is exposed by the opening. In this case, one end of the flexible film 600 is attached to the bonding area EA.

In addition, a driving chip 400 for driving the main display panel 200 and the sub-display panel 300 is formed in an area adjacent to one end of the flexible film 600. Here, the driving chip 400 is formed between the main display panel 200 and the sub-display panel 300, and is electrically connected to the main display panel 200 and simultaneously with the sub-display panel 300. Electrically connected. The driving chip 400 is formed on the flexible film 600 by a low temperature poly silicon (LTPS) process.

In the region of the flexible film 600 between the main display panel 200 and the driving chip 400, the main image signal M-DATA output from the driving chip 400 is included in the first data line group DL1 -DL. The first connection line group CL1-1, ..., CL1-n and the main gate signal M-GS provided to 1, ..., DL1-n are connected to the first gate line group GL1-1. 2nd connection line group CL1-1, ..., CL1-m provided to GL1-m is provided.

In addition, a sub image signal S-DATA output from the driving chip 400 may be included in a region of the flexible film 600 between the sub-display panel 300 and the driving chip 400. The third connection line group CL2-1, ..., CL2-j and the sub gate signal S-GS provided to the DL2-1, ..., DL2-j are supplied to the second gate line group GL2. Fourth connection line group CL2-1, ..., CL2-k provided to -1, ..., GL2-k) is provided.

Thus, the main image signal M-DATA output from the driving chip 400 passes through the first connection line group CL1-1,..., CL1-n, and then the main display panel 200. Are transmitted to the first data line group DL1-1, ..., DL1-n. The main gate signal M-GS output from the driving chip 400 passes through the second connection line group CL1-1,..., CL1-m, and then the first gate of the main display panel 200. It is transmitted to the gate line groups GL1-1, ..., GL1-m.

Meanwhile, the sub image signal S-DATA output from the driving chip 400 passes through the third connection line group CL2-1,..., CL2-j and then the sub-display panel 300. Are transmitted to the second data line group DL2-1,..., DL2-j, and the sub-gate signal S-GS output from the driving chip 400 is the fourth connection line group CL2-1. After passing through ..., CL2-k, the second gate line group GL2-1, ..., GL2-k of the sub-display panel 300 is transferred.

As such, since the driving chip 400 is formed on the flexible film 600 between the main display panel 200 and the sub-display panel 300, the sub image signal output from the driving chip 400 ( S-DATA and the sub-gate signal S-GS are provided directly to the sub-display panel 300 without passing through the main display panel 200, so that the path is not long, thereby reducing signal delay due to line resistance. You can prevent it.

In addition, the driving chip 400 displays the main image on the main display panel 200 by a 1: G demux method, and the sub-display panel 300 by a point addressing method. The sub image is displayed on the screen. Here, G is a number of data lines grouped into a plurality of groups, and represents the number of data lines grouped in the one group.

4 is a block diagram illustrating an internal configuration of a driving chip illustrated in FIG. 3.

As shown in FIG. 4, the driving chip 400 includes a controller 410, a memory 420, a main driver 430, and a sub driver 440.

The controller 410 receives the raw image signal O-DATA and the raw control signal OCS from the CPU 500 of FIG. 1. The controller 410 stores the received raw image signal O-DATA in the memory unit 420 (WRITE-DATA). Thereafter, the controller 410 reads an image signal from the memory unit 420 in units of lines at an appropriate time in response to the original control signal OCS (READ-DATA).

The memory unit 420 includes a main storage area and a sub storage area. The memory unit 420 selectively stores the raw image signal O-DATA provided from the controller 410 in the main storage area or the sub storage area. Here, the memory unit 420 may not only be formed inside the driving chip 400 but may be formed outside the driving chip.

The controller 410 reads the main image signal M-DATA stored in the main storage area of the memory unit 420, and supplies the main image signal M-DATA and the first gate control signal GCS1 to the main driver. Provided at 430.

The main driver 430 receives the first gate control signal GCS1 and receives the main gate signal M as the first gate line group GL1-1,..., GL1-m of the main display panel 200. -GS) and outputs the main video signal M-DATA to the first data line group DL1-1, ..., DL1-n. In this case, the main driving unit 430 sets the main image signal M-DATA to the first data line group DL1-1,..., DL1-n of the main display panel 200 by using a 1: G demux method. )

That is, the main driver 430 divides the first data line groups DL1-1,..., And DL1-n by G, and the first connection line groups CL1-1,..., CL1-n. The main video signal is output to G data lines simultaneously.

For example, if there are 300 data lines, the 300 data lines are divided into first, second, and third groups so that 100 data lines form one group, and the gate driving time is first and second. And the third section. The main video signal is simultaneously output to 100 data lines of the first group during the first period, and the main video signal is simultaneously output to 100 data lines of the second group during the second period. Subsequently, the main video signal is simultaneously output to 100 data lines of the third group during the third period.

Therefore, the number of output terminals of the driving chip can be reduced in proportion to the number of groups grouping the data lines. That is, in the case of the QVGA display device, there are 246 × 3 data lines. When the display device is driven by a 1: 3 demux method by grouping the data lines driving the R, G, and B pixels, The output terminals are reduced to 246.

In addition, the controller 410 reads the sub image signal S-DATA stored in the sub storage area of the memory unit 420, and sub-displays the sub image signal S-DATA and the second gate control signal GCS2. The driving unit 440 is provided.

The sub driver 440 receives the second gate control signal GCS2 and receives the sub gate signal S as the second gate line group GL2-1,..., GL2-k of the sub-display panel 300. -GS), and outputs the sub video signal S-DATA to the second data line group DL2-1, ..., DL2-j. In this case, the sub driver 440 provides the sub image signal S-DATA to the second data line group DL2-1,..., DL2-j of the sub-display panel 300 by the point addressing method. do.

That is, the sub driver 440 sequentially sub-sequences the second image signal S-DATA to the second data line group DL2 during the gate driving time through the third connection line groups CL2-1,..., CL2-j. -1, ..., DL2-j).

For example, when 100 data lines exist, the gate driving time is divided into 100, and the sub image signals are sequentially provided to 100 data lines during the divided gate driving times. Here, the point addressing method divides the gate driving time into a plurality of driving the plurality of data lines, so that the operating frequency is increased, but since the sub-display panel 300 has a lower resolution than the main display panel 200, Point addressing drive is possible.

As such, the main display panel 200 displays the main image by the 1: G demux method, and the sub display panel 300 displays the sub image by the point addressing method. The number of output terminals of the driving chip 400 for outputting the sub image signal and the sub gate signal is smaller than that of the output terminal for outputting the main image signal and the main gate signal to the main display panel 200.

Therefore, even if the main display panel and the sub-display panel are driven by one driving chip, the main display panel and the sub-display panel can be driven simultaneously without significantly increasing the number of output terminals of the driving chip. Can be.

In the above, the present invention has been described taking the case where the sub-display panel 300 is formed on the flexible film 600 as an example. Meanwhile, in the present invention, the flexible film 600 is formed between the main display panel 200 and the sub-display panel 300, and the driving chip 400 may be formed on the flexible film 600. have.

As described above, the present invention connects the main display panel and the sub-display panel to each other by a flexible film, and forms a driving chip for driving the main display panel and the sub-display panel on the flexible film. do. Therefore, since a drive signal for driving the sub-display panel is directly applied to the sub-display panel without passing through the main display panel, signal distortion due to signal delay of the drive signal can be prevented, thereby improving display characteristics. Can be.

In addition, since the conventional FPC is unnecessary, the overlap area for forming the FPC is unnecessary, and the process for forming the FPC is unnecessary, which reduces the size of the display panel and reduces the manufacturing process and manufacturing cost. You can.

In addition, the present invention drives the main display panel by the 1: G demux method and the sub-display panel by the point address method, thereby efficiently reducing the number of output terminals of the driving chip.

While the invention has been described with reference to the examples, those skilled in the art may variously modify and change the invention without departing from the spirit and scope of the invention as set forth in the claims below. You will understand.

1 is a view schematically showing a general dual clamshell liquid crystal display device.

2 is a block diagram schematically illustrating a dual liquid crystal display according to an exemplary embodiment of the present invention.

3 is a plan view illustrating in detail the structure of the dual LCD shown in FIG. 2.

4 is a block diagram illustrating an internal configuration of a driving chip illustrated in FIG. 3.

* Description of the symbols for the main parts of the drawings *

200: main display panel 300: sub-display panel

400: driving chip 410: control unit

420: memory unit 430: main drive unit

440: sub-drive unit 500: CPU

600: flexible film

Claims (9)

In the driving chip formed between the first display panel and the second display panel to output different driving signals to the first and second display panel, A controller for outputting a first image signal and a first gate control signal or outputting a second image signal and a second gate control signal in response to an original image signal and a source control signal provided from the outside; A first driver configured to output a first gate signal and a first data signal to the first display panel according to the first gate control signal and the first image signal; And And a second driver configured to output a second gate signal and a second data signal to the second display panel according to the second gate control signal and the second image signal. The driving chip of claim 1, wherein the first driving unit outputs the first data signal to the first display panel by using a 1: G demux method. The driving chip of claim 1, wherein the second driver outputs the second data signal to the second display panel by a point addressing method. The method of claim 1, And a storage unit having a first storage region for temporarily storing the first image signal input from the controller and a second storage region for temporarily storing the second image signal. A first display panel configured to display a first image in response to the first driving signal; A second display panel displaying a second image in response to a second driving signal; A flexible film connecting the first display panel and the second display panel; And And a driving chip formed on the flexible film between the first display panel and the second display panel to output the first and second driving signals to the first and second display panels, respectively. The display device of claim 5, wherein the first display panel includes first to nth data lines and first to mth gates orthogonal to the first to nth data lines, wherein m is a number equal to or less than n. 7. and, The second display panel may include first to jth data (j is a number less than or equal to n) and first to kth data k orthogonal to the first to jth data lines (k is less than or equal to m). And a gate line. The method of claim 6, wherein the driving chip A controller for outputting a first image signal and a first gate control signal or outputting a second image signal and a second gate control signal in response to an original image signal and a source control signal provided from the outside; A first driver to output a first data signal to the first to nth data lines and a first gate signal to the first to mth gate lines according to the first gate control signal and the first image signal ; And A second data signal output to the first to jth data lines and a second gate signal output to the first to kth gate lines according to the second gate control signal and the second image signal; Display device including a drive unit. 8. The first driving unit of claim 7, wherein the first driving unit is arranged in a group in which the first to n-th data lines are grouped by N while the first gate signal is applied to one of the first to m-th gate lines. And simultaneously outputting the first data signal to N data lines. The method of claim 7, wherein the second driver sequentially processes the second data signal to the first to jth data lines while the second gate signal is applied to one of the first to kth gate lines. Display device, characterized in that for outputting.