KR20050097146A - Method of manufacturing image sensor - Google Patents

Method of manufacturing image sensor Download PDF

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Publication number
KR20050097146A
KR20050097146A KR1020040022240A KR20040022240A KR20050097146A KR 20050097146 A KR20050097146 A KR 20050097146A KR 1020040022240 A KR1020040022240 A KR 1020040022240A KR 20040022240 A KR20040022240 A KR 20040022240A KR 20050097146 A KR20050097146 A KR 20050097146A
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scribe line
film
forming
image sensor
microlens
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KR1020040022240A
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Korean (ko)
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조동헌
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매그나칩 반도체 유한회사
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Publication of KR20050097146A publication Critical patent/KR20050097146A/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14618Containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/1462Coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14625Optical elements or arrangements associated with the device
    • H01L27/14627Microlenses
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1876Particular processes or apparatus for batch treatment of the devices

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

본 발명은 스크라이브 라인 절단 또는 패키지 공정 시 LTO막의 깨짐 및 들뜸을 방지하여 칩 특성 및 패키지 공정의 안정성을 향상시킬 수 있는 이미지센서의 제조방법을 제공한다.The present invention provides a method of manufacturing an image sensor that can improve chip characteristics and stability of the packaging process by preventing cracking and lifting of the LTO film during scribe line cutting or packaging process.

본 발명은 화소가 형성된 칩영역과 스크라이브 라인 영역이 구비되고, 상부에는 소정의 표면 단차를 가지는 배선이 형성된 반도체 기판을 준비하는 단계; 배선을 덮도록 기판 상에 패시배이션막을 형성하는 단계; 스크라이브 라인 영역의 패시배이션막 상부에 평탄화 패턴을 형성하여 단차를 제거하는 단계; 및 기판 전면 상에 LTO막을 형성하는 단계를 포함하는 이미지센서의 제조방법에 의해 달성될 수 있다. 바람직하게, 평탄화 패턴은 화소의 마이크로렌즈 형성 시 상기 마이크로렌즈 물질과 동일한 물질로 동시에 형성하고, 마이크로렌즈 물질은 포토레지스트막으로 이루어진다. 또한, 평탄화 패턴은 OCL로 형성할 수도 있다. According to an embodiment of the present invention, there is provided a semiconductor substrate including a chip region and a scribe line region on which pixels are formed, and wirings having predetermined surface steps thereon; Forming a passivation film on the substrate so as to cover the wirings; Forming a planarization pattern on the passivation layer of the scribe line region to remove the step; And forming an LTO film on the front surface of the substrate. Preferably, the planarization pattern is simultaneously formed of the same material as the microlens material when the microlens of the pixel is formed, and the microlens material is formed of a photoresist film. In addition, the planarization pattern may be formed of OCL.

Description

이미지센서의 제조방법{METHOD OF MANUFACTURING IMAGE SENSOR} Manufacturing Method of Image Sensor {METHOD OF MANUFACTURING IMAGE SENSOR}

본 발명은 이미지센서의 제조방법에 관한 것으로, 특히 LTO막을 적용한 이미지센서의 제조방법에 관한 것이다.The present invention relates to a manufacturing method of an image sensor, and more particularly, to a manufacturing method of an image sensor to which an LTO film is applied.

일반적으로, 이미지센서는 광학영상(optical image)을 전기적 신호로 변환시키는 반도체 소자로서, 빛을 감지하는 광감지 부분과 감지된 빛을 전기적 신호로 처리하여 데이터화하는 로직회로 부분으로 구성되어 있으며, CMOS(Complementary Metal Oxide Semiconductor) 이미지센서의 경우에는 CMOS 기술을 이용하여 화소 수만큼 MOS 트랜지스터를 만들고 이것을 이용하여 차례차례 출력을 검출하는 스위칭 방식을 채용한다. 또한, 광감지 부분 상부에는 칼라 이미지 구현을 위해 칼러필터 어레이(Color Filter Array; CFA)가 배치될 뿐만 아니라, 광감도 향상을 위해 광감지 부분 이외의 영역으로 입사하는 빛의 경로를 변경하여 광감지 부분으로 모아주도록 마이크로렌즈(Micro Lens; ML)가 배치된다.In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal. The image sensor is composed of an optical sensing part that senses light and a logic circuit part that processes the sensed light into an electrical signal to make data. (Complementary Metal Oxide Semiconductor) In the case of image sensor, CMOS technology is used to make MOS transistors by the number of pixels, and the switching method is used to detect the output sequentially. In addition, a color filter array (CFA) is disposed above the light sensing portion to realize a color image, and the light sensing portion is changed by changing a path of light incident to an area other than the light sensing portion to improve light sensitivity. Micro lenses (ML) are arranged to collect.

여기서, 칼라필터와 마이크로렌즈는 포토레지스트로 이루어지기 때문에 외부의 파티클 흡착이 용이하므로, 오염 방지를 위해 칼라필터와 마이크로렌즈 형성 후 저온산화(Low Temperature Oxide; LTO)막을 적용한다.Here, since the color filter and the microlens are made of photoresist, external particles are easily adsorbed, and thus, a low temperature oxide (LTO) film is applied after forming the color filter and the microlens to prevent contamination.

그러나, LTO막이 스트레스에 약한 단점을 가지기 때문에, 예컨대 화학기계연마(Chemical Mechanical Polishing; CMP) 공정을 수행하지 않는 0.35㎛급 CMOS 이미지센서 기술에서는, 도 1과 같이 비아홀(12)에 의해 배선(13)의 평탄도 저하가 발생되어 패시배이션 질화막(14)과 LTO막(15) 형성 후 큰 단차("A" 부분)가 야기됨으로써, 스크라이브 라인(scribe line) 절단(sawing) 또는 패키지 등의 후속 공정시, 도 2의 "B"와 같이 LTO막이 깨지거나 들뜨는 현상을 유발하여, 칩(chip) 특성에 악영향을 미칠 뿐만 아니라 파티클을 발생하여 WBP 패일(fail) 등을 야기시킨다. However, since the LTO film has a weak disadvantage in stress, for example, in the 0.35 占 퐉 CMOS image sensor technology that does not perform a chemical mechanical polishing (CMP) process, the wiring 13 is connected by the via hole 12 as shown in FIG. Flatness decreases and causes a large step ("A" portion) after formation of the passivation nitride film 14 and the LTO film 15, thereby resulting in subsequent scribe line sawing or packaging, etc. In the process, as shown in FIG. 2B, the LTO film is broken or lifted, which not only adversely affects chip characteristics, but also generates particles to cause WBP failure.

본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 스크라이브 라인 절단 또는 패키지 공정 시 LTO막의 깨짐 및 들뜸을 방지하여 칩 특성 및 패키지 공정의 안정성을 향상시킬 수 있는 이미지센서의 제조방법을 제공하는데 그 목적이 있다. The present invention has been proposed to solve the above problems of the prior art, a method of manufacturing an image sensor that can improve chip characteristics and stability of the packaging process by preventing cracking and lifting of the LTO film during scribe line cutting or packaging process. The purpose is to provide.

상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 상기의 본 발명의 목적은 화소가 형성된 칩영역과 스크라이브 라인 영역이 구비되고, 상부에는 소정의 표면 단차를 가지는 배선이 형성된 반도체 기판을 준비하는 단계; 배선을 덮도록 기판 상에 패시배이션막을 형성하는 단계; 스크라이브 라인 영역의 패시배이션막 상부에 평탄화 패턴을 형성하여 단차를 제거하는 단계; 및 기판 전면 상에 LTO막을 형성하는 단계를 포함하는 이미지센서의 제조방법에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, an object of the present invention is to provide a semiconductor substrate having a chip region and a scribe line region in which the pixel is formed, the wiring having a predetermined surface step on the top Preparing; Forming a passivation film on the substrate so as to cover the wirings; Forming a planarization pattern on the passivation layer of the scribe line region to remove the step; And forming an LTO film on the front surface of the substrate.

바람직하게, 평탄화 패턴은 화소의 마이크로렌즈 형성 시 상기 마이크로렌즈 물질과 동일한 물질로 동시에 형성하고, 마이크로렌즈 물질은 포토레지스트막으로 이루어진다.Preferably, the planarization pattern is simultaneously formed of the same material as the microlens material when the microlens of the pixel is formed, and the microlens material is formed of a photoresist film.

또한, 평탄화 패턴은 OCL로 형성할 수도 있다.In addition, the planarization pattern may be formed of OCL.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

도 3을 참조하여 본 발명의 실시예에 따른 이미지센서의 제조방법을 설명한다.Referring to Figure 3 will be described a method of manufacturing an image sensor according to an embodiment of the present invention.

도 3을 참조하면, 화소가 형성된 칩영역과 스크라이브 라인 영역이 구비되고, 상부에는 비아홀(32)이 구비된 층간절연막(31)과 비아홀(32)에 의해 표면 단차를 가지는 배선(33)이 형성된 반도체 기판(30) 상에 배선(33)을 덮도록 패시배이션 질화막(34)을 증착한다. Referring to FIG. 3, a chip region and a scribe line region in which pixels are formed are provided, and an interlayer insulating layer 31 having a via hole 32 and a wiring 33 having surface steps are formed by the via hole 32. The passivation nitride film 34 is deposited on the semiconductor substrate 30 so as to cover the wiring 33.

그 다음, 패시배이션 질화막(34) 상부에 마이크로렌즈용 포토레지스트막을 도포하고, 노광 및 현상하여 화소 상부에 마이크로렌즈(미도시)를 형성함과 동시에 스크라이브 라인 영역 상부에 평탄화 패턴(35)을 형성하여 단차를 제거하여 스크라이브 라인 영역의 표면 평탄도를 개선한다. 즉, 포토레지스트막에 의해 패시배이션 질화막(34)의 상대적으로 낮은 부분의 표면이 채워지게 되어 단차가 제거되므로 표면 평탄도가 우수해진다. 그 후, 기판 전면 상에 LTO막(36)을 증착한다. Next, a microlens photoresist film is applied on the passivation nitride film 34, and exposed and developed to form a microlens (not shown) on the pixel, and the planarization pattern 35 is formed on the scribe line region. It is formed to improve the surface flatness of the scribe line area by removing the step. That is, the surface of the relatively low portion of the passivation nitride film 34 is filled by the photoresist film so that the step is eliminated, so that the surface flatness is excellent. Thereafter, an LTO film 36 is deposited on the entire surface of the substrate.

상기 실시예에 의하면, 마이크로렌즈용 포토레지스트막을 이용하여 스크라이브 라인 영역의 표면 평탄도를 개선함으로써, 스크라이브 라인 절단 또는 패키지 등의 후속 공정 시 LTO막의 깨짐 및 들뜸을 방지할 수 있으므로, 칩 특성 및 패키지 공정의 안정성을 향상시킬 수 있다.According to the above embodiment, the surface flatness of the scribe line region is improved by using the photoresist film for microlenses, thereby preventing the cracking and lifting of the LTO film during the subsequent processing of the scribe line cutting or the package, and thus the chip characteristics and package. The stability of the process can be improved.

한편, 상기 실시예에서는 마이크로렌즈용 포토레지스트막을 적용하여 스크라이브 라인 영역의 표면 평탄도를 개선하였지만, 오버코팅층(Over Coating Lyer; OCL)을 적용하여도 동일한 작용 및 효과를 얻을 수 있다. Meanwhile, in the above embodiment, the surface flatness of the scribe line region is improved by applying a photoresist film for microlenses, but the same effect and effect can be obtained even by applying an over coating layer (OCL).

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다. The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

전술한 본 발명은 스크라이브 라인 절단 또는 패키지 공정 시 LTO막의 깨짐 및 들뜸을 방지할 수 있으므로, 칩 특성 및 패키지 공정의 안정성을 향상시킬 수 있다. Since the present invention described above can prevent cracking and lifting of the LTO film during scribe line cutting or package process, it is possible to improve chip characteristics and stability of the package process.

도 1 및 도 2는 종래 이미지센서의 LTO막에서 발생되는 문제를 나타낸 도면.1 and 2 are views showing a problem occurring in the LTO film of the conventional image sensor.

도 3은 본 발명의 실시예에 따른 이미지센서의 제조방법을 설명하기 위한 단면도.3 is a cross-sectional view illustrating a method of manufacturing an image sensor according to an embodiment of the present invention.

※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing

30 : 반도체 기판 31 : 층간절연막30 semiconductor substrate 31 interlayer insulating film

32 : 비아홀 33 : 배선32: via hole 33: wiring

34 : 패시배이션 질화막 35 : 평탄화 패턴34 passivation nitride film 35 planarization pattern

36 : LTO막 36: LTO membrane

Claims (4)

화소가 형성된 칩영역과 스크라이브 라인 영역이 구비되고, 상부에는 소정의 표면 단차를 가지는 배선이 형성된 반도체 기판을 준비하는 단계;Preparing a semiconductor substrate having a chip region and a scribe line region on which pixels are formed, and a wiring having a predetermined surface level formed thereon; 상기 배선을 덮도록 기판 상에 패시배이션막을 형성하는 단계;Forming a passivation film on the substrate so as to cover the wiring; 상기 스크라이브 라인 영역의 패시배이션막 상부에 평탄화 패턴을 형성하여 상기 단차를 제거하는 단계; 및 Forming a planarization pattern on the passivation layer of the scribe line region to remove the step; And 상기 기판 전면 상에 LTO막을 형성하는 단계를 포함하는 이미지센서의 제조방법.Forming an LTO film on the front surface of the substrate. 제 1 항에 있어서, The method of claim 1, 상기 평탄화 패턴은 상기 화소의 마이크로렌즈 형성 시 상기 마이크로렌즈 물질과 동일한 물질로 동시에 형성하는 것을 특징으로 하는 이미지센서의 제조방법.And the planarization pattern is formed simultaneously with the same material as the microlens material when the microlens of the pixel is formed. 제 2 항에 있어서, The method of claim 2, 상기 마이크로렌즈 물질은 포토레지스트막으로 이루어진 것을 특징으로 하는 이미지센서의 제조방법.And the microlens material is made of a photoresist film. 제 1 항에 있어서, The method of claim 1, 상기 평탄화 패턴은 OCL로 형성하는 것을 특징으로 하는 이미지센서의 제조방법.The flattening pattern is a manufacturing method of the image sensor, characterized in that formed by OCL.
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