KR100720463B1 - Method for fabricating cmos image sensor - Google Patents

Abstract

Fabrication of a CMOS image sensor according to an exemplary embodiment of the present invention, in which the surface of the planarization layer is shallow etched using oxygen to change the characteristics of the surface of the planarization layer, thereby reducing the change in the line width of the microlens. The method includes forming a color filter array implemented with a plurality of color filters on a semiconductor substrate on which a substructure including a plurality of light sensing elements is formed; Forming a first planarization layer on the color filter array; Etching only the surface of the first planarization layer thinly using oxygen; And forming a micro lens on the etched first planarization layer.

Microlens, Linewidth, Oxygen, Etch, Shallow

Description

Method of manufacturing CMOS image sensor {Method for Fabricating CMOS Image Sensor}

1 is a cross-sectional view of a CMOS image sensor according to the prior art.

2A to 2C are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to an embodiment of the present invention.

Figure 3 is a view showing a comparison of the line width related capability index according to the prior art and the present invention.

<Description of the symbols for the main parts of the drawings>

20: semiconductor substrate 22: device isolation film

24: photodiode 26: interlayer insulating film

28: metal wiring 30: passivation film

32: first planarization layer 34: color filter array

36: second planarization layer 38: microlens

The present invention relates to a method for manufacturing a CMOS image sensor, and more particularly, to a method of stabilizing a line width of a micro lens used in a CMOS image sensor.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal. Among them, a charge coupled device (CCD) includes individual metal-oxide-silicon (MOS) capacitors. A device in which charge carriers are stored and transported in a capacitor while being very close to each other, and a complementary MOS image sensor uses a CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits. A device employing a switching scheme that creates MOS transistors as many as pixels and sequentially detects outputs using the MOS transistors.

CCD has many disadvantages such as complicated driving method, high power consumption, high number of mask process steps, complicated process, and difficult to implement signal processing circuit in CCD chip. In order to overcome such drawbacks, the development of a CMOS image sensor using a sub-micron CMOS manufacturing technology has been studied a lot. The CMOS image sensor forms an image by forming a photodiode and a MOS transistor in a unit pixel and sequentially detects signals in a switching method.As a CMOS manufacturing technology, the CMOS image sensor consumes less power and has 20 to 30 masks. Compared to CCD process that requires two masks, the process is very simple, and it is possible to make various signal processing circuits and one chip, which is attracting attention as the next generation image sensor.

The CMOS image sensor has a color filter arrayed on the upper part of the light sensing portion that receives and receives light from the outside to generate and accumulate photocharges to implement a color image. The color filter array (CFA) consists of three colors: red, green, and blue, or three colors: yellow, magenta, and cyan. It is made of collar.

In addition, the image sensor is composed of a light sensing portion for detecting light and a logic circuit portion for processing the detected light as an electrical signal to make data. The ratio of the area of the light sensing portion in the entire image sensor element is increased to increase the light sensitivity. Efforts have been made to increase the fill factor, but these efforts are limited in a limited area because the logic circuit part cannot be removed.

Therefore, a condensing technology has emerged to change the path of light incident to an area other than the light sensing portion to raise the light sensitivity, and to collect the light sensing portion. For this purpose, the image sensor uses a microlens on the Cali filter. The method of forming is used.

1 is a cross-sectional view of an image sensor including a micro filter and a color filter array formed according to this prior art. As shown in the drawing, an image sensor including a color filter and a microlens includes a semiconductor substrate 10 having a device isolation layer forming process and a passivation process, a first planarization layer 12 formed on the semiconductor substrate 10, and a first planarization layer. Color filter array (CFA) 14 formed on (12), second planarization layer 14 formed on color filter array 14, and microlens (ML) 18 formed thereon It includes.

However, in the image sensor as described above, the surface of the second planarization layer 14 and the microlens 18 interact with each other according to the process progression condition during the baker process for forming the microlens 18. Therefore, there is a problem that a change in the line width (CD) of the microlens occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and by changing the characteristics of the surface of the second planarization layer by shallow etching the surface of the second planarization layer using oxygen to reduce the change in the line width of the microlenses. It is a technical object of the present invention to provide a method for manufacturing a CMOS image sensor.

Method of manufacturing a CMOS image sensor according to an embodiment of the present invention for achieving the above object is to form a color filter array implemented with a plurality of color filters on a semiconductor substrate formed with a lower structure including a plurality of light sensing elements step; Forming a first planarization layer on the color filter array; Etching only the surface of the first planarization layer thinly using oxygen; And forming a micro lens on the etched first planarization layer.

At this time, in the first planarization layer etching step, the first planarization layer is characterized in that only the surface of the first planarization layer is thinly etched.

More specifically, in the etching step of the first planarization layer, the etching target of the first planarization layer is characterized in that more than the top surface of the color filter array.

The method for manufacturing the CMOS image sensor may further include forming a passivation film on the semiconductor substrate before the color filter array forming step.

In addition, the method of manufacturing the CMOS image sensor, before the color filter array forming step. And forming a second planarization layer on the semiconductor substrate.

In addition, the first and second planarization layers may be formed of a photosensitive film series material.

 Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2A to 2C are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to an exemplary embodiment of the present invention.

First, as shown in FIG. 2A, first, an isolation layer 22 defining an active region and a field region and a photodiode 24 that generate photocharges are formed on the semiconductor substrate 20 by receiving light. After forming the device isolation film 22 and related elements including the photodiode 24, the interlayer insulating film 26 is formed on the semiconductor substrate 20, and the metal wiring 28 is formed on the interlayer insulating film 26. Form. Although only one metal wire 28 is shown in FIG. 2A, more metal wires may be used, and at this time, the metal wire formed at the top is referred to as the final metal wire 28. The metal wires 28 are preferably intentionally laid out so as not to block the light incident on the photodiode 13.

After the final metal wiring 28 is formed in this manner, the passivation film 30 is formed on the final metal wiring 28 to protect the device from moisture, scratches, and the like. Next, the first planarization layer 32 is formed on the passivation film 30 to remove the step difference between the final metal wiring 28 and the passivation film 30, which is a color filter to be subsequently formed. 34) is formed on the flattened surface. The first planarization layer 32 may be formed of a photosensitive film series material.

Next, a color filter array 34 for color image realization is formed on the first planarization layer 32. The color filter array is implemented with a plurality of color filters. One color filter is formed for each unit pixel to separate colors from incident light. Conventional color filters are composed of three types of filters: blue, red, and green. All three types of filters are formed using photoresist, and neighboring color filters are formed to overlap each other slightly.

Next, the second planarization layer 36 is formed on the color filter 34 to compensate for the step caused by the overlap of the adjacent color filters. The microlens for collecting light should be formed on the flattened surface. For this purpose, the step due to the color filter should be eliminated, and the second planarization layer 36 serves to remove the step. In this case, the second planarization layer 36 is also formed of the same photoresist film as the first planarization layer 32.

Next, as illustrated in FIG. 2B, the surface of the second planarization layer 36 is etched by etching the surface of the second planarization layer 36 with oxygen (O ₂ ) to form a microlens (not shown). In order to prevent the interaction between the second planarization layer 36 and the microlens generated by the Baker process, which is a subsequent process, to prevent the microlens. This prevents a change in the critical dimension (CD) of the microlens.

In this case, the etching target of the second planarization layer 36 is set to a depth such that an influence due to etching does not occur on the color filter array 34 formed under the second planarization layer 36. That is, the etching target is preferably set to the uppermost surface of the color filter array 34 or more.

Next, as shown in FIG. 2C, the microlens 38 is formed on the second planarization layer 36a having a thinly etched surface. A method of forming the microlens 38 will be described below.

First, a photosensitive photoresist of a silicon oxide film series having high light transmittance is applied by using a spin-on-coater. Next, a patterning process using an appropriate mask is performed to form an angular microlens corresponding to each unit pixel. Next, by applying a thermal process to flow the angular microlens, a dome-shaped microlens as shown in FIG. 1A can be obtained.

3 is a graph showing a line width related process capability index (Cpk) of the CMOS image sensor according to the related art and a line width related process capability index (Cpk) of the CMOS image sensor according to the present invention. As shown, it can be seen that the Cpk in the case of oxygen treatment of the second planarization layer 36 is 0.74, which is improved from 0.31, which is the Cpk in the absence of oxygen treatment.

Those skilled in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive.

The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

As described above, according to the present invention, the line width of the microlenses generated by the interaction between the microlens and the second planarization layer by changing the properties of the second planarization layer by etching the surface of the second planarization layer with oxygen. The change can be prevented, which can improve the line width related capability index.

Claims (6)

Forming a color filter array implemented with a plurality of color filters on a semiconductor substrate having a lower structure including a plurality of light sensing elements; Forming a first planarization layer on the color filter array; Etching only the surface of the first planarization layer thinly using oxygen; And Forming a micro lens on the etched first planarization layer; Method of manufacturing a CMOS image sensor comprising a. delete The method of claim 1, wherein the etching target of the first planarization layer is set to a depth such that an effect of etching does not occur on the color filter array. The method of claim 1, further comprising forming a passivation film on the semiconductor substrate before the color filter array forming step. The method of claim 1, further comprising forming a second planarization layer on the semiconductor substrate before the color filter array forming step. The method of claim 5, wherein the first and second planarization layers are formed of a photosensitive film series material.

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