KR20050096668A - Method and apparatus for driving data of liquid crystal display appratus - Google Patents

Abstract

The present invention provides a data driving method and apparatus for a liquid crystal display device which can reduce electromagnetic interference (EMI) and power consumption by reducing the number of data transitions.

To this end, the data driving method of the present invention comprises the steps of: arranging pixel data and alternately supplying pixel data for the left side of the panel with pixel data for the right side; Converting the binary code of the supplied pixel data into a gray code; Converting the pixel data converted into the gray code into modulated data indicating whether the pixel data converted into the gray code is identical to the gray data converted two gray cycles before; And alternately transmitting the converted modulated data to a left data driver integrated circuit and a right data driver integrated circuit through a transmission line.

Description

TECHNICAL AND APPARATUS FOR DRIVING DATA OF LIQUID CRYSTAL DISPLAY APPRATUS

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a method and an apparatus for driving data of a liquid crystal display which can reduce power consumption while minimizing electromagnetic interference (EMI).

In recent years, video data transmitted through a transmission medium has been increased in order to satisfy a user's desire for high quality images, and is being transmitted at a high speed so that the user can use it at an appropriate time. Accordingly, the transmission frequency of the video data is increased and the number of transmission lines for transmitting the video data is inevitably increased. In this case, as the video data having high frequency is transmitted synchronously through the increased data transmission lines, electromagnetic interference (hereinafter referred to as “EMI”) is severely displayed.

In order to reduce EMI, a liquid crystal display adopts a method of reducing the number of transitions of data by a data modulation method or a method of reducing a transmission frequency by using a six bus, that is, a two-port method.

1 illustrates a conventional liquid crystal display device for transmitting video data in a six-bus system.

The liquid crystal display shown in FIG. 1 includes a liquid crystal panel 10, a data driving IC 12 for driving data lines of the liquid crystal panel 10, and a gate driving for driving gate lines of the liquid crystal panel 10. An IC 14 and a timing controller 16 for controlling the data driver IC 12 and the gate driver IC 14 are provided.

The liquid crystal panel 10 includes a pixel matrix composed of sub pixels formed at respective regions defined by intersections of gate lines and data lines. One pixel is realized by a combination of R, G, and B sub pixels, and each of the sub pixels includes a liquid crystal cell for adjusting light transmittance according to a data signal, and a thin film transistor for driving the liquid crystal cell. The thin film transistor is turned on in a period where a scan pulse is supplied to a corresponding gate line to supply a video data signal on the data line to the liquid crystal cell, and is turned off until a scan pulse is supplied in the next frame to charge the liquid crystal cell. Data signal is maintained. According to the video data signal charged through the thin film transistor, the liquid crystal cell changes the arrangement state of the liquid crystal having the dielectric anisotropy, thereby realizing the gray scale by adjusting the light transmittance.

The plurality of gate driver ICs 14 separately drive the gate lines of the liquid crystal panel 10. The plurality of gate driving ICs 14 sequentially drive the gate lines by sequentially supplying scan pulses to the gate lines.

The plurality of data driver ICs 12 separately drive the data lines of the liquid crystal panel 10. Each of the plurality of data driving ICs 12 converts the digital video data signals R, G, and B supplied from the timing controller 16 into analog video data signals, so that each time the scan pulse is supplied to each of the data lines. Will be supplied.

The timing controller 16 generates a gate control signal for controlling the gate driving IC 14 and supplies it to the gate driving IC 14. The timing controller 16 also generates a data control signal for controlling the data driver IC 12 and supplies it to the data driver IC 12. In this case, the timing controller 16 may include a data enable signal DE, a horizontal sync signal Hsync, a vertical sync signal Vsync, and video data RGB indicating a valid data section input from a computer system (not shown). Gate control signals and data control signals are generated using a dot clock DCLK that determines a transmission frequency of the signal.

In addition, the timing controller 16 aligns the video data signals R, G, and B input from a computer system (not shown) to the data driver IC 12 in a manner suitable for a two-port transfer method. For example, the timing controller 16 separates the video data R, G, and B into the odd pixel data RO, GO, and BO, and even pixel data RE, GE, and BE, and thus, the two ports PT1 and PT2. ) To the data driver IC 12. Here, when it is assumed that each of the pixel data R, G, and B is composed of 6 bit data to represent 63 grays, the even and odd pixel data RE, GE, BE, RO, GO, and BO are transmitted in parallel. It can be seen that the two ports PT1 and PT2 consist of a total of 36 data transmission lines. In this way, the timing controller 16 reduces the EMI by reducing the transmission frequency of the video data by adopting the two-port (PT1, PT2) transmission scheme.

However, due to the large number of transitions of bit data in each of the plurality of data transmission lines constituting the two ports PT1 and PT2, problems such as EMI and power consumption increase still occur.

In detail, there is generally little gray level change due to similarity between adjacent pixel data in an image to be displayed on the liquid crystal panel. However, a change of one gray in a binary code corresponding to video data does not necessarily mean a transition of one bit data. For example, when the first port P1 transmits "0001111" corresponding to seven grays as the i-th red pixel data, and then transmits "000100" corresponding to eight grays as the i + 2th red pixel data. Although only one gray is changed between the i-th and i + 2th red pixel data, it can be seen that a relatively large amount of four bit data is transitioned. Therefore, even though the data transmission lines of two ports PT1 and PT2 continuously transmit adjacent pixel data with almost no gray change, many data bit transitions occur on each data transmission line, thereby increasing EMI and power consumption. Done.

Meanwhile, in order to further reduce the data transmission frequency, the four-port transmission method in which the timing controller transmits the first odd and first even pixel data and the second odd and second even pixel data in parallel to the data driver IC using four ports. Was proposed. However, the four-port transmission method doubles the number of data transmission lines compared to the two-port transmission method, and as described above, the number of transitions of data bits, which are binary codes, causes a problem of EMI and power consumption.

Accordingly, it is an object of the present invention to provide a data driving method and apparatus for a liquid crystal display device which can reduce electromagnetic interference (EMI) and power consumption by reducing the number of data transitions.

In order to achieve the above object, a data driving method of a liquid crystal display according to an exemplary embodiment of the present invention comprises the steps of: arranging pixel data and alternately supplying pixel data for the left side of the panel with pixel data for the right side; Converting the binary code of the supplied pixel data into a gray code; Converting the pixel data converted into the gray code into modulated data indicating whether the pixel data converted into the gray code is identical to the gray data converted two gray cycles before; And alternately transmitting the converted modulated data to a left data driver integrated circuit and a right data driver integrated circuit through a transmission line.

In addition, the present invention determines whether the current modulation data transmitted from each of the left and right data driving integrated circuits is identical to the restored previous pixel data, and selectively inverts the previous pixel data according to whether the same. And restoring to data.

In addition, the present invention includes the steps of converting the gray code of the reconstructed pixel data into a binary code; Sequentially latching pixel data converted into the binary code; Converting the latched pixel data to an analog signal and supplying the latched pixel data to a data line.

Alternatively, the present invention includes the steps of sequentially latching the restored pixel data; And converting the gray code of the latched pixel data into an analog signal and supplying the same to a data line.

The data driving device of the liquid crystal display according to the present invention includes a data alignment unit for arranging pixel data and alternately supplying left pixel data to be supplied to the left side of the panel with right pixel data to be supplied to the right; A binary-gray encoder for converting pixel data from a data alignment unit to pixel data of gray code, and indicating whether the pixel data converted to gray code is identical to the pixel data converted to gray code before two clock cycles. And a data controller for converting the modulated data to the left data driver integrated circuit and the right data driver integrated circuit through the transmission line.

Each of the left and right data driving integrated circuits determines whether the transmitted current modulated data is identical to the restored previous pixel data, and selectively inverts the previous pixel data to restore the current pixel data according to the same. A reconstruction unit and a gray-binary decoder for converting the gray code of the reconstructed pixel data into a binary code; After latching the pixel data converted to the binary code, and further comprising a data driver for converting the latched pixel data to an analog signal to supply to the data line.

In contrast, each of the left and right data driving integrated circuits determines whether the transmitted current modulated data is identical to the reconstructed previous pixel data, and selectively inverts the previous pixel data according to the identicalness to the current pixel data. A data latching unit for restoring and restoring the restored pixel data sequentially; And a gray digital-analog converter for converting the gray code of the pixel data supplied from the data latch unit into an analog signal and supplying the gray signal to the data line.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Prior to the description of the preferred embodiments of the present invention, one more detailed description of the source technology used to derive the present invention will be described.

2 illustrates a data driving device of a liquid crystal display device driven by a new four-port transmission method of alternately transmitting left and right data of a panel.

The data driver shown in FIG. 2 includes a plurality of left and right data driver ICs 22L and 22R for separately driving data lines of a liquid crystal panel (not shown), and left and right data driver ICs by arranging video data. A timing controller 26 is alternately supplied to the 22L and 22R.

The left data driver IC 22L divides and drives the left data lines on the liquid crystal panel (not shown), and the right data driver IC 22R drives the right data lines.

The timing controller 26 alternately supplies pixel data to the left and right data driving ICs 22L and 22R using two ports PT1 and PT2. In other words, the timing controller 26 rearranges the video data signals R, G, and B input from the computer system (not shown) and left-hands the left data driving IC 22L through the two ports PT1 and PT2. After supplying the odd pixel data (LOR, LOG, LOB) and the left even pixel data (LER, LEG, LEB), the right odd pixel data (ROR, ROG, ROB) and the right data driver IC 22R are supplied. Right even pixel data RER, REG, and REB are supplied. Accordingly, there is an advantage that the number of data transmission lines can be reduced by half compared to the existing four-port method.

However, the timing controller 26 alternates the left pixel data (LOR, LOG, LOB, LER, LEG, LEB) and the right pixel data (ROR, ROG, ROB, RER, REG, REB) whose grays are not similar. In this case, a data transition is more likely to occur than conventional two-port and four-port schemes in which gray transmits adjacent pixel data similar to each other.

In addition, when the new 4-port data transmission apparatus shown in FIG. 2 uses a method of converting and transmitting data such that data transition is reduced by comparing previous data with current data, the left pixel data having gray similarities ( Since the current data) is compared with the right pixel data (previous data), there is still a high possibility of a data transition occurring.

Accordingly, the data driving apparatus according to the present invention uses a method of modulating data by comparing similar data, ie, two previous data and current data, in order to reduce the possibility of data transition with the new four-port method described above. do. Further, the data transmission apparatus according to the present invention further reduces the possibility of data transition by further using a method of converting a binary code into a gray code in which one gray change means one bit change.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 6.

3 is a block diagram illustrating a data driving device of a liquid crystal display according to an exemplary embodiment of the present invention.

The data driving apparatus shown in FIG. 3 includes a timing controller 70 and a timing controller 70 for transmitting data using a method of encoding a binary code into a gray code and a method of modulating data with the same identity between gray similar data. And data driving ICs 90L and 90R for demodulating data of equality or not received from the < RTI ID = 0.0 >

The timing controller 70 includes a data alignment unit 72, a binary-gray encoder 70, and a data modulator 76.

The data aligning unit 72 inputs the video data signals R, G, and B from an external computer system (not shown), and stores the left and right pixel data of the liquid crystal panel separately. The data alignment unit 72 alternately outputs left pixel data to be supplied to the left data driver IC 90L and right pixel data to be supplied to the right data driver IC 90R. At this time, the left pixel data and the left pixel data (LDR, LOG, LOB, LER, LEG, LEB) as the left pixel data, and the right pixel data (ROR, ROG, ROB, RER, REG, REB) for the right pixel data ) Is included and output.

The binary-gray encoder 74 encodes the pixel data supplied from the data aligning unit 72, that is, the left or right pixel data in gray code and outputs the gray code. Specifically, the binary-gray encoder 74 outputs the MSB as it is from the binary code data as shown in FIG. 5, and each of the remaining bits is equal to "0" if the same is higher by the EOR operation with adjacent higher bits, and "1" if different. By outputting the binary code is converted to gray code and output.

 The gray code refers to data coded such that only one bit of data is transitioned in a change of one gray unit. Comparing these gray codes with binary codes is shown in Table 1 below.

Referring to Table 1 above, in the case where data is changed in units of 1 gray from 0 gray to 63 gray, a total of 120 data transitions occur in the binary code, whereas 63 transitions occur in the gray code. . Accordingly, when data having a small gray change between adjacent data such as a graphic image is transmitted in a gray code, the data transition can be reduced by half.

The data modulator 76 converts the left (or right) pixel data, which is converted into a gray code through the binary-gray encoder 74, to pixel data similar to gray, that is, left (or right) pixel data supplied before two clock cycles. Compares bit by bit and converts into modulated data indicating the identity and outputs the same.

Specifically, the data modulator 76 includes a plurality of D flip-flop pairs 78 for delaying the currently inputted left (or right) pixel data for two clock cycles, and the currently inputted left (or right) pixel data. And a plurality of EOR gates 80 which output modulation data indicating whether they are the same as compared to the left (or right) pixel data prior to two clock cycles supplied through the plurality of D flip-flop pairs 78.

Each of the plurality of D flip-flop pairs 78 delays each bit of currently input left (or right) pixel data for two clock periods. Accordingly, the plurality of EOR gates 80 compares currently supplied left (or right) pixel data with adjacent left (or right) pixel data to determine whether they are identical. Specifically, each of the plurality of EOR gates 80 compares the corresponding bit of the left (or right) pixel data that is currently supplied with the corresponding bit of the left (or right) pixel data two clocks ago, so that both bits are equal to " 0 " ", Otherwise" 1 "will be printed. In this case, the pixel data compared by the plurality of EOR gates 80 are similar to each other as they are supplied to adjacent pixels in the panel. As a result, many of the EOR gates 80 outputs "0", so the data transition is significantly reduced.

The left modulated data output from the data modulator 76 is supplied to the left data driver IC 90L through the output ports PT1 and PT2, and the right modulated data alternately outputted with the left modulated data is output port. It supplies to the right data driving IC 90R via (PT1, PT2).

Each of the left and right data driving ICs 90L and 90R includes a data recovery unit 92 for restoring input pixel data, and a gray-binary decoder for converting pixel data from the data restoration unit 92 back to gray code ( 98 and a data driver 100 for converting pixel data from the gray-binary decoder 98 into an analog data signal and supplying the same to a liquid crystal panel.

The data reconstructor 92 restores current modulated data input from the timing controller 70 by comparing the reconstructed previous pixel data. The data recovery unit 92 selectively inverts each bit of the restored previous pixel data according to each bit of the modulation data to restore each bit of the current pixel data. Specifically, when the corresponding bit of the modulated data is "0", the data recovery unit 92 supplies the corresponding bit of the restored previous pixel data to the corresponding bit of the current pixel data. On the other hand, when the corresponding bit of the modulation data is "1", the corresponding bit of the restored previous pixel data is inverted and supplied to the corresponding bit of the current pixel data.

To this end, the data recovery unit 92 outputs a plurality of EOR gates 94 for inputting modulated data and an output of the EOR gate 94 by one clock delay, and outputs the outputs to the inputs of the EOR gate 94. Nominal D flip-flop 96 is provided.

EOR gate 94 performs an EOR operation on the corresponding bit of modulation data and previous pixel data returned from D flip-flop 96 and supplies the result to D flip-flop 96. Specifically, when the corresponding bit of the modulation data is "0", the EOR gate 94 supplies the corresponding bit of the previous pixel data returned from the D flip-flop 96 to the D flip-flop 96 as it is. On the other hand, when the corresponding bit of the modulation data is "1", the corresponding bit of the previous pixel data returned from the D flip-flop 96 is inverted and supplied to the D flip-flop 96. The D flip-flop 96 outputs a clock delayed bit recovered through the EOR gate 94.

The gray-binary decoder 98 decodes the pixel data supplied from the data recovery unit 92 into a binary code and outputs it. Specifically, the gray-binary decoder 98 outputs the MSB in the gray code data as it is, as shown in FIG. 6, and each of the remaining bits is equal to "0" if different from the higher bits of the gray code by "OR". By outputting 1 ", gray code is converted into binary code and output.

The data driver 100 sequentially latches pixel data of the binary code supplied from the gray-binary decoder 98, and simultaneously converts the latched pixel data into an analog pixel signal and supplies the same to the corresponding data line. To this end, the data driver 100 includes a shift register for generating a sampling signal and a latch unit for sequentially latching input pixel data in response to the sampling signal; And a digital-to-analog converter (DAC) for converting the latched pixel data into an analog pixel signal using a gamma voltage, and an output buffer unit for buffering and outputting the analog pixel signal.

7 illustrates a data driving device of a liquid crystal display according to another exemplary embodiment of the present invention.

The data driver ICs 110L and 110R illustrated in FIG. 7 may have the data latch unit 112 instead of the gray-binary decoder 98 and the data driver 100 as compared to the data driver ICs 90L and 90R illustrated in FIG. 3. And the same components except having a gray code DAC 114. Therefore, description of overlapping components will be omitted.

The data latch unit 112 sequentially latches pixel data of the binary code supplied from the gray-binary decoder 98, and simultaneously supplies the latched pixel data to the gray code DAC 114. To this end, the data latch unit 112 includes a shift register for generating a sampling signal, and a latch unit for sequentially latching inputted pixel data in response to the sampling signal and then simultaneously outputting the same.

The gray code DAC 114 converts the pixel data of the gray code output from the data latch unit 112 into an analog pixel signal using the corresponding gamma voltage without decoding the binary code. In this case, the gamma voltage set corresponding to the pixel data of the gray code is used as the gamma voltage. The gray code DAC 114 supplies the converted analog pixel signal to a corresponding data line through an output buffer.

As described above, in the data driving method and apparatus of the liquid crystal display according to the present invention, when the left pixel data and the right pixel data of the panel are alternately supplied by the timing controller, the current pixel data is a pixel before two clock cycles of similar data. Compared to the data, the data transition can be reduced by modulating and transmitting the data indicating the identity.

In addition, the data driving method and apparatus of the liquid crystal display according to the present invention can significantly reduce the data transition by converting the pixel data into a gray code having a small data change rate between adjacent grays before data modulation.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a block diagram illustrating a general liquid crystal display.

2 is a block diagram showing a data driving device of a liquid crystal display device according to the present invention;

3 is a block diagram illustrating a data driving device of a liquid crystal display according to a first exemplary embodiment of the present invention.

4 is a diagram for explaining a coding concept of gray code.

5 is a detailed circuit diagram of the binary-gray encoder shown in FIG.

FIG. 6 is a detailed circuit diagram of the grey-binary decoder shown in FIG.

7 is a block diagram illustrating a data driving device of a liquid crystal display according to a second exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

10 liquid crystal panel 12 data driving IC

14: gate drive IC 16, 26, 70: timing controller

22L, 90L, 110L: Left Data Driver IC

22R, 90R, 110R: Right Data Drive IC

72: data alignment unit 74: binary-gray decoder

76: data modulation section 78: D flop-flop pair

80, 94: EOR gate 92: data recovery unit

96: D flip-flop 98: Grey-binary decoder

100: data driver 112: data latch unit

114: Gray Code DAC

Claims (7)

Aligning the pixel data to alternately supply the left pixel data of the panel with the right pixel data; Converting the binary code of the supplied pixel data into a gray code; Converting the pixel data converted into the gray code into modulated data indicating whether the pixel data converted into the gray code is identical to the gray data converted two gray cycles before; And alternately transmitting the converted modulated data to a left data driver integrated circuit and a right data driver integrated circuit through a transmission line. The method of claim 1, Determining whether the current modulated data transmitted from each of the left and right data driving integrated circuits is identical to the restored previous pixel data, and selectively inverting the previous pixel data to restore the current pixel data according to the same. The data driving method of the liquid crystal display device further comprises. The method of claim 2, Converting the gray code of the reconstructed pixel data into a binary code; Sequentially latching pixel data converted into the binary code; Converting the latched pixel data into an analog signal and supplying the latched pixel data to a data line. The method of claim 2, Sequentially latching the restored pixel data; And converting the gray code of the latched pixel data into an analog signal and supplying the gray code of the latched pixel data to a data line. A data alignment unit for arranging pixel data and alternately supplying left pixel data to be supplied to the left side of the panel with right pixel data to be supplied to the right; A binary-gray encoder for converting pixel data from the data alignment unit into pixel data of gray code; A data modulator for converting the pixel data converted into the gray code into modulated data indicating whether the pixel data converted into the gray code is equal to the gray data converted two gray cycles ago; And a timing controller for alternately transferring the converted modulated data to a left data driver integrated circuit and a right data driver integrated circuit through a transmission line. The method of claim 5, Each of the left and right data driver integrated circuits A data restoring unit for determining whether the transmitted current modulated data is identical to the restored previous pixel data, and selectively inverting the previous pixel data to restore the current pixel data according to the same identity; A gray-binary decoder for converting gray codes of the reconstructed pixel data into binary codes; And a data driver for latching the pixel data converted into the binary code and converting the latched pixel data into an analog signal and supplying the converted pixel data to a data line. The method of claim 5, Each of the left and right data driver integrated circuits A data restoring unit for determining whether the transmitted current modulated data is identical to the restored previous pixel data, and selectively inverting the previous pixel data to restore the current pixel data according to the same identity; A data latch unit for sequentially latching and restoring the restored pixel data; And a gray digital-analog converter for converting a gray code of the pixel data supplied from the data latch unit into an analog signal and supplying the gray signal to a data line.