KR20050096006A - Method for improving efficiency of test system using jtag and system for performing the same - Google Patents

Abstract

Disclosed are a method for improving the performance of a test system using a JTAG to improve the performance of a JTAG-based test system by removing unnecessary clock consumption during a JTAG-based test process, and a system for performing the same. The present invention provides a control method of a JTAG-based test system formed by including a command processing module in front of a TAP controller, wherein the command processing module receives an input of a TMS pin as an internal enable pin to input an input of a TMS pin. Recognizing that a signal input through the TDI pin is a command when it is in a '1' state and storing the same in a command register; And a step of ignoring when the input of the TMS pin is '0' before the TAP controller generates the control signal.

Description

Method for improving efficiency of test system using JTAG and system for performing the same}

The present invention relates to a method for improving the performance of a test system using the JTAG and a system for performing the same, in particular to improve the performance of the JTAG-based test system by removing unnecessary clock consumption during the instruction storage process during the JTAG-based test process The present invention relates to a method for improving performance of a test system using JTAG and a system for performing the same.

In general, a method for testing complex integrated circuits implemented in integrated circuit (IC) chips is the IEEE 1149.1 boundary-scan standard created by the recently widely used Joint Test Action Group (JTAG). -scannedstandard).

The general concept of serial testing using JTAG is to shift serial data into multiple integrated circuit devices to generate certain output signals from circuitry embedded within the integrated circuit device. Then, data generated by the integrated circuit elements or received by the input pins of the integrated circuit element is shifted from the integrated circuit element to the JTAG master test circuit.

If the data stream returned to the JTAG master test circuit differs from what is expected, malfunctions in the circuit are detected by the test circuit, so carefully analyzing the deviations present in the data stream under software control is present in the circuit. It can isolate any malfunction.

1 is a block diagram illustrating an instruction storage circuit in a test system using a conventional JTAG, and FIG. 2 is a flowchart illustrating an operation of a TAP controller in the instruction storage circuit illustrated in FIG.

As shown in FIG. 1, the conventional test system using the JTAG receives a TCK, which is a clock signal of the JTAG circuit, through the TCK pin, and controls the state of the TAP controller 110 through the TMS pin. The TAP controller 110 receiving the determined TMS (test mode select) signal outputs a control signal for a test to the command register scan chain 120. The command register scan chain 120 is composed of four scan cells, and the command register scan chain 120 is composed of four bits according to the control signal of the TAP controller 110. Save the command in).

In addition, when a command for determining data or data to be input to a target circuit such as a semiconductor for testing is input to the command register scan chain 120 through the TDI pin, the command register scan chain 120 The test is performed according to the control signal input from the TAP controller 110 and the signal input through the TDI pin.

 In detail, as shown in FIG. 2, the TAP controller 110 initializes all contents in the test logic reset state 210 and maintains the state while the TMS signal is 1. If the TMS signal is 0, the TMS signal is in the run test / idle state 211 for entering the JTAG into an operating state. When the TMS signal is high and the rising edge is applied to the TCK signal, the TAP controller 110 moves to a data register select scan state 212 where all the dead data registers selected by the current instruction maintain their full state. If the TMS signal remains low while the rising edge is applied to the TCK signal, the TAP controller 110 transitions to the data register capture state 213, where the TMS signal remains high and the rising edge is applied to the TCK signal. In this case, the TAP controller 110 transitions to the command register selection scan state 219.

When the TAP controller 110 transitions to the data register capture state 212, the data register capture state 212 selects whether to control the boundary scan cell selected by the command register 130 of FIG. Done. In this state, when the TMS signal goes low, the TAP controller 110 transitions to the data register capture state 213 to store the content to be scanned in the boundary scan cell selected by the command register 130. In this state, when the TAP controller 110 is in the data register capture state 213 while the rising edge is applied to the TCK signal, the controller enters the data register shift state 214. However, if the TMS signal remains high while the rising edge is applied to the TCK signal, the TAP controller 110 transitions directly from the data register capture state 213 to the data register exit state 215. In the data register shift state 214, the data register shifts to finally output data stored in a boundary scan cell.

When the TAP controller 110 is in the data register shift state 214 and the TMS signal remains high and the rising edge is applied to the TCK signal, the TAP controller 110 is in an exit data register state 215 that is an intermediate state for transition. Transitions to). If the TMS signal remains high in the exit data register state 215 and a rising edge is applied to the TCK signal, the TAP controller 110 inputs the data stored in the boundary scan cell to the target circuit to be tested. Transition to the data register update state 218, and if the TMS signal remains low, the TAP controller 110 transitions to the data register pause state 216, which is an intermediate state for state transition. If the TMS signal remains high and the rising edge is applied to the TCK signal in the data register suspended state 216, then the TAP controller 110 transitions to the second data register exit state 217, which is also an intermediate state for state transition. In this state, if the TMS signal remains low and the rising edge is applied to the TCK signal, the TAP controller 110 returns to the data register shift state 214. However, if the TMS signal remains high, the TAP controller 110 transitions from the second data register exit state 217 to the data register update state 218.

Here, if the TMS signal remains high and the rising edge is applied to the TCK signal while the TAP controller 110 is in the data register select scan state 212, then the TAP controller 110 sends a command register 130 to FIG. Transition to instruction register select scan state 219 which determines whether to control. When the TAP controller 110 transitions to the instruction register capture state 220, the instruction register 130 is ready for instruction shift and when the TAP controller 110 transitions to the instruction register shift state 221, the instruction register ( Shifts the 4-bit instruction inputted at 130). If the TMS signal remains high in command register capture state 220, TAP controller 110 transitions to command register exit state 222, which is an intermediate state for state transition. When the TMS signal remains high in the command register exit state 222, the rising edge applied to the TCK signal causes the TAP controller 110 to enter the command register update state 225, while the rising edge causes the TCK signal to rise. When the TMS signal remains low while being applied to the TAP controller 110 enters the instruction register stop state 223, which is an intermediate state for the state transition.

If the TMS signal remains high and the rising edge is applied to the TCK signal in the command register suspended state 223, the TAP controller 110 enters the second command register exit state 224, which is also an intermediate stage for state transition. If the rising edge is applied to the TCK signal while the TMS signal remains low, the TAP controller 110 returns to the instruction register shift state 221. However, if the TMS signal remains high while the rising edge is applied to the TCK signal, the TAP controller 110 updates the instruction register to store the instruction shifted from the second instruction register exit state 224 to the instruction register 130. Transition to state 225. When the TAP controller 110 is in the instruction register update state 225 and the rising edge is applied to the TCK signal, the TAP controller 110 enters the data register select scan state 212 and the TMS signal when the TMS signal remains high. Keeps low to enter idle state 211.

In the test system using the conventional JTAG operating as described above, eight state transitions occur during the instruction storing process. That is, as shown in FIG. 2, the 4-bit instruction, which is a serial input, is shifted to the run test / idle 211 in the test logic reset 210 state in order to store the 4-bit instruction in the command register 130 of FIG. Transition to register select scan state 212, where transition to instruction register select scan state 219, where transition to instruction register capture state 220, where transition to instruction register shift state 221, where There are a total of eight state transitions that transition from the instruction register exit state 222 to the instruction register update state 225.

Since the instruction storing process is a process for storing 4-bit data input in serial, it is reasonable to theoretically consume 5 clocks. However, as described above, a total of eight state transitions occur during the instruction storing process. Experimental results show that it consumes 10 clocks during instruction storage. There was a problem in that the test process consumed five more clocks. These unnecessary clock consumptions include run test / idle 211, data register selection scan state 212, instruction register selection scan state 219, instruction register capture state 220, and instruction register shift state 221. Occurs in transition. Due to such unnecessary clock consumption, there is a problem that performance degradation such as test speed delay of a test system using JTAG occurs.

The present invention has been invented to solve the above problems, and in order to eliminate unnecessary clock consumption by eliminating the instruction storing process in the progress of the TAP controller on the JTAG-based test system, the front end of the TAP controller is eliminated. Design a command processing module that can process the command storage process, and generate the TMS signal by itself according to the external TMS signal that determines the state of the TAP controller in this command processing module to perform the command storage process. The first purpose of the present invention is to provide a method of improving the performance of a test system using JTAG to prevent the test speed delay of the test system using the JTAG, thereby improving performance.

It is also a second object of the present invention to provide a system for carrying out the first object described above.

The present invention for achieving such a first object,

In the control method of the JTAG based test system formed by including a command processing module in front of the TAP controller,

Receiving an input of the TMS pin as an internal enable pin from the command processing module and recognizing that a signal input through the TDI pin is a command when the input of the TMS pin is in a '1' state and storing the same in a command register; And a step of ignoring when the input of the TMS pin is '0' before the TAP controller generates the control signal.

In addition, a system for performing the second object of the present invention,

In a JTAG-based test system including a TAP controller, a TCK pin receives a clock signal TCK, and inputs a command for determining whether to scan data or specific information to be input to a target circuit to be tested through the TDI pin. Receives the input of the TMS pin, which determines the state of the TAP controller, as an enable pin, and recognizes that the signal applied through the TDI pin is a command only when the input of the TMS pin is '1' and stores it in the command register. It includes a command processing module.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram illustrating the structure and operation of the command processing module and the TAP controller in the test system using the JTAG according to the present invention, and FIG. 4 is a diagram for explaining the operation of the TAP controller shown in FIG. 5 is a flowchart illustrating a simulation result for reducing unnecessary clock consumption in a test system using a JTAG according to the present invention.

As shown in FIG. 3, the test system using the JTAG according to the present invention includes an instruction processing module 310 that does not exist in the conventional system. The command processing module 310 receives a clock signal TCK through the TCK pin 302 and inputs a command for determining whether to scan data or specific information to be input to the target circuit to be tested through the TDI pin 304. And a test mode select (TMS) signal for determining a state of the TAP controller 320 through the TMS pin 306.

The instruction processing module 310 receives the input of the TMS pin 306 to the enable pin 311, that is, only when the input of the TMS pin 306 is in a '1' state, that is, the enable pin. Only when the signal input to 311 is 'high', it recognizes that the signal applied through the TDI pin 304 is a command and operates to store the command in the command register 340. Therefore, the command applied through the TDI pin 304 is stored in the command register 340 only when the input of the TMS pin 306 is in the '1' state, and the input of the TMS pin 306 is in the '0' state. In case of time, that is, when the signal input to the enable pin (311) is 'low' it is ignored.

That is, since the same clock signal is input to the instruction processing module 310 and the TAP controller 320 at the TCK pin 302, the TMS pin is connected to the TAP controller 320 through the internal TMS pin 312 in synchronization with the clock signal. Only when the input of 306 is '1' state, the command applied through the TDI pin 304 is stored in the command register 340.

In addition, the command processing module 310 generates a control signal of the TAP controller 320 through the internal TMS pin 312, and is configured to store a command in the command register 340 composed of 4 bits. That is, the command processing module 310 receives a control signal of the TAP controller 320 when a command for determining what data or information to scan is input to a target circuit such as a semiconductor for a test through the TDI pin 304. To generate the command in the command register 340.

Therefore, the command processing module 310 is operated to perform a command storing process before generating a control signal to the TAP controller 320 in the conventional JTAG-based test system to remove unnecessary clock consumption. As the command processing module 310 is operated to perform before generating a control signal to the TAP controller 320, the operation of the TAP controller 320 according to the present invention is deleted as shown in FIG. This greatly reduces the clock consumption consumed to perform the instruction storage process.

In detail, since the command processing module 310 recognizes that the signal applied through the TDI pin 304 is a command only when the input of the TMS pin 306 is '1', the input of the TMS pin 306 is input. When the value becomes '1', the command processing module 310 issues a command to determine whether to scan data or information to be input to a target circuit such as a semiconductor for a test input through the TDI pin 304. ) To end the command storing process, outputs a high signal to the TAP controller 320, enters the test logic reset state 410 for initializing all contents, and then executes the command processing.

The instruction processing process is the same as the conventional method as shown in FIG. That is, when the input of the TMS pin 306 is 0, the TAP controller 320 controls the run test / idle state 411 to enter the JTAG into the operating state, and the TMS signal is high and the rising edge is the TCK signal. When applied to the TAP controller 320 moves to a data register selection scan state 412 where all of the dead data registers selected by the current instruction maintain their full state.

If the TMS signal is held low while the rising edge is applied to the TCK signal, the TAP controller 320 transitions to the data register capture state 413 and the boundary scan cell selected by the command register 340. You can choose whether to control. In this state, when the TMS signal goes low, the TAP controller 320 transitions to the data register capture state 413 to store the content to be scanned in the boundary scan cell selected by the command register 340. In this state, when the TMS signal goes low, the TMS signal transitions to the data register shift state 214 for moving the data stored in the boundary scan cell to serial output to the TDO pin as the final output, and the TMS signal remains high. If so, the TAP controller 320 transitions directly from the data register capture state 413 to the data register exit state 415.

When the TAP controller 320 is in the data register shift state 414 and the TMS signal remains high and the rising edge is applied to the TCK signal, the TAP controller 320 is an intermediate data exit state register state 415 for state transitions. Transitions to). If the TMS signal remains high in the exit data register state 415 and a rising edge is applied to the TCK signal, the TAP controller 320 inputs the data stored in the boundary scan cell to the target circuit to be tested. Transition to the data register update state 418, and if the TMS signal remains low, the TAP controller 320 transitions to the data register pause state 416, which is an intermediate state for transition. If the TMS signal remains high and the rising edge is applied to the TCK signal in the data register suspend state 416, then the TAP controller 320 transitions to a second data register exit state 417, which is also an intermediate state for state transition. In this state, if the TMS signal remains low and the rising edge is applied to the TCK signal, the TAP controller 320 returns to the data register shift state 414. However, if the TMS signal remains high, then the TAP controller 320 transitions from the second data register exit state 417 to the data register update state 418.

As described above, the test system using JATG according to the present invention operates as described in FIG. 5 to perform a command storing process before the command processing module 310 generates a control signal from the TAP controller 320. There is an improvement in performance, and the simulation results reduce the clock consumption by 50%. That is, the JTAG-based test system according to the present invention of FIG. 5B consumes 5 clocks in the instruction storing process, whereas the conventional method shown in FIG. 5A consumes 10 clocks in the instruction storing process. The performance was shown to reduce consumption by 50%.

As described above, the test system using the JTAG according to the present invention is operated to perform a command storing process before the command processing module 310 generates a control signal in the TAP controller 320, thereby preventing unnecessary clock consumption by preventing JTAG. There is an effect to improve the performance, such as test speed delay of the test system using.

Although the preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, the present invention is not limited thereto and may be improved or modified by those skilled in the art within the scope of the technical idea of the present invention.

1 is a block diagram illustrating an instruction storage circuit in a test system using a conventional JTAG.

FIG. 2 is a flowchart illustrating an operation of a TAP controller in the command storage circuit shown in FIG. 1.

3 is a circuit diagram illustrating the structure and operation of a command processing module and a TAP controller in a test system using a JTAG according to the present invention.

FIG. 4 is a flowchart for explaining an operation of the TAP controller shown in FIG. 2.

5 (A) and (B) is a clock diagram for showing a simulation result for showing the reduction of unnecessary clock consumption in the test system using the JTAG according to the present invention compared to the conventional test system using the JTAG.

<Explanation of symbols for the main parts of the drawings>

             302: TCK pin 304: TDI pin

             306: TMS pin 310: instruction processing module

             311: Enable pin 320: TAP controller

             340: command register

Claims (2)

In the control method of the JTAG-based test system formed by including the command processing module 310 in front of the TAP controller 320, When the input of the TMS pin 306 is input to the internal enable pin 311 by the command processing module 310 and the input of the TMS pin 306 is '1', it is input through the TDI pin 304. Recognizing that the signal being a command is a command and storing it in the command register 340; And operating to ignore the input when the input of the TMS pin 306 is in a '0' state, before the TAP controller 320 generates a control signal. How to improve the performance of a test system using JTAG. In the JTAG-based test system including a TAP controller 320, The clock signal TCK is applied through the TCK pin 302, and a command for determining whether to scan data or specific information to be input to the target circuit to be tested is input through the TDI pin 304, and the TAP controller 320 is input. A signal applied through the TDI pin 304 is received only when the input of the TMS pin 306 that determines the state of the input signal is enabled to the enable pin 311 and the input of the TMS pin 306 is '1'. Test system using a JTAG including a command processing module 310 that is operable to recognize the command and to store it in the command register (340).