KR20050090207A - Memory device having hierarchy bit line architecture - Google Patents

Abstract

A memory device having a hierarchical bit line architecture according to the present invention improves redundancy efficiency by using a redundant memory cell array block having a merged main bit line architecture. The present invention relates to a memory device having a hierarchical bit line structure capable of improving yield since all redundancy memory cells can be tested in a mode. The hierarchical bit line includes a main bit line to which a plurality of sub bit lines are connected. A memory block including a plurality of main memory cell array blocks having a structure and a plurality of redundancy memory cell array blocks having a hierarchical bit line structure having a redundant main bit line to which a plurality of redundancy sub bit lines are connected; A large number of sensing and amplifying data on the line And a word line driving block for driving the word line to which the main bit line sense amplifier and the selected memory cell are connected.

Description

Memory device having hierarchy bit line architecture

The present invention relates to a memory device having a hierarchical bit line architecture, and more particularly, redundancy using a redundant memory cell array block having a merged main bit line architecture. The present invention relates to a memory device having a hierarchical bit line structure capable of improving efficiency and improving yield since all redundancy memory cells can be tested in a test mode.

In general, as the dynamic random access memory (DRAM) is highly integrated, the cell size becomes smaller. As a result, cell capacity is also reduced.

In addition, in order for the bit line sense amplifier to stably sense and amplify using this small cell capacitance, the bit line capacitance to the cell capacitance must be small.

However, as the number of memory cells connected to one bit line increases as the DRAM becomes more integrated, the bit line capacitance with respect to the cell capacitance becomes larger.

Therefore, there is a limit to increase the cell density, and the time required for the sensing operation of the bit line sense amplifier is increased, resulting in a decrease in the overall operation speed.

In addition, as the cell density increases, fail cells increase, and after replacing fail cells with redundancy cells, redundancy efficiency decreases because it is impossible to test whether the replaced redundancy cells fail, and as a result, the efficiency of the memory device decreases. There is this.

An object of the present invention for solving the above problems is to reduce the bit line capacitance to the memory cell capacitance by hierarchically configuring the bit line.

Another object of the present invention is to merge the main bit lines to reduce the total number of bit lines.

It is still another object of the present invention to improve redundancy efficiency by hierarchically configuring bit lines of a redundant memory cell array block.

Yet another object of the present invention is to improve yield by testing all redundancy memory cells in test mode.

A memory device having a hierarchical bit line structure according to the present invention for achieving the above object includes a plurality of main memory cell array blocks and a plurality of main memory cell array blocks having a hierarchical bit line structure including a main bit line to which a plurality of sub bit lines are connected. A memory block including a plurality of redundancy memory cell array blocks having a hierarchical bit line structure having redundancy main bit lines to which redundancy sub bit lines are connected; A plurality of main bit line sense amplifiers for sensing and amplifying data carried on the main bit line; And a word line driving block driving the word line to which the selected memory cell is connected.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a main part of a memory device having a hierarchical bit line structure according to the present invention.

The memory device includes a memory block 2, a word line driver 4, and a main bit line sense amplifier array block 6. The memory blocks 2 are arranged symmetrically with respect to the main bit line sense amplifier array block 6.

The memory block 2 includes a sub memory block 8, a column redundancy memory cell array block 10, a low redundancy memory cell array block 12, and a common redundancy memory cell array block 14.

The sub memory block 8 includes a plurality of main memory cell array blocks 16. The sub bit line SBL0 of the main memory cell array block 16 is connected to the main bit lines MBLT0 and MBLB0.

The column redundancy memory cell array block 10 includes a plurality of sub column redundancy memory cell array blocks 18. The redundancy sub bit line RSBL0 of the sub column redundancy memory cell array block 18 is connected to the redundancy main bit lines RMBLT0 and RMBLB0.

The redundancy sub bit line RSBL0 of the low redundancy memory cell array block 8 is commonly connected to the main bit lines MBLT0 and MBLB0 of the sub memory block 8.

In addition, the sub-column redundancy memory cell array block 18 is commonly connected to the word lines of the main memory cell array block 16.

The redundancy sub bit line RSBL0 of the common redundancy memory cell array block 14 is commonly connected to the redundancy main bit line RMBL0 of the column redundancy memory block 10. The common redundancy memory cell array block 14 is also commonly connected to the word lines of the low redundancy memory cell array block 12.

FIG. 2 is a conceptual diagram illustrating a method of replacing a fail row with a redundancy row and replacing a fail column with a redundancy column in the embodiment shown in FIG. 1.

As shown in FIG. 2, a fail row of the memory block 2 is replaced with a redundancy row of the low redundancy memory cell array block 12 and the common redundancy memory cell array block 14. The fail column is replaced with a redundancy column of the column redundancy memory block 10 and the common redundancy memory cell array block 14. Generally, the fail column of any main memory cell array block 16 is replaced with a redundancy column with a column at the same position as the fail column of all main memory cell array blocks 16. That is, all the memory cells connected to the fail column (main bit line MBLT0) are replaced by all the redundancy memory cells connected to the redundancy column (redundancy main bit line RMBLT0) at the same time.

FIG. 3 is a detailed circuit diagram illustrating the sub memory block 8 and the column redundancy memory block 10 shown in FIG. 1. Here, the folded bit line structure will be described as an example.

The sub memory block 8 includes a plurality of main memory cell array blocks 16, a plurality of sub bit line sense amplifiers 24, and a plurality of switch units 26.

The main memory cell array block 16 includes a plurality of sub memory cell array blocks 20. The sub memory cell array block 20 includes a plurality of memory cells 22 connected to the sub bit lines SBL0 and SBL1. Here, the plurality of memory cells 22 are selected by the word lines WL0 to WLn.

The sub bit line sense amplifier 24 includes NMOS transistors NM1 and NM2 whose drains are connected to the sub bit lines SBL0 and SBL1 respectively, the sub bit line sense amplifier control signal SBLVOL is applied to the source, and the gate is cross-coupled. . In addition, the sub bit line sense amplifier 24 may use various types of sense amplifiers depending on the system used.

The switch section 26 includes NMOS transistors NM3 and NM4. Here, the NMOS transistor NM3 is controlled by the switch control signal SBSWL to selectively connect the sub bit line SBL0 to the main bit line MBLT0, and the NMOS transistor NM4 is controlled by the switch control signal SBSWR to selectively select the sub bit line SBL1 as the main bit line. Connect to MBLT0.

Accordingly, the sub memory cell array block 20 has a merged main bit line structure in which two sub bit lines SBL0 and SBL1 are connected via a switch unit 26 to one main bit line MBLT0 as a pair. Have

The column redundancy memory block 10 is configured in the same way as the sub memory block 8. That is, the column redundancy memory block 10 includes a plurality of main column redundancy memory cell array blocks 18, a plurality of redundancy sub bit line sense amplifiers 30, and a plurality of switch units 32.

The main column redundancy memory cell array block 18 includes a plurality of sub column redundancy memory cell array blocks 28. The sub column redundancy memory cell array block 28 includes a plurality of redundancy memory cells 30 connected to the redundancy sub bit lines RSBL0 and RSBL1. Here, the plurality of redundancy memory cells 30 are selected by the word lines WL0 to WLn.

The redundancy sub bit line sense amplifier 32 has a drain connected to the redundancy sub bit lines RSBL0 and RSBL1 respectively, a sub bit line sense amplifier control signal SBLVOL is applied to the source, and the gates are cross-coupled to the NMOS transistors NM5 and NM6. Include. In addition, the redundancy sub bit line sense amplifier 32 may use various types of sense amplifiers depending on the system used.

The switch section 34 includes NMOS transistors NM7 and NM8. Here, the NMOS transistor NM7 is controlled by the switch control signal SBSWL to selectively connect the redundancy sub-bit line RSBL0 to the redundancy main bit line RMBLT0, and the NMOS transistor NM8 is controlled by the switch control signal SBSWR to selectively select the redundancy sub-bit line RSBL1. Connect to the redundancy main bit line RMBLT0.

Thus, the sub-column redundancy memory cell array block 28 is a merged main in which two redundancy sub-bit lines RSBL0 and RSBL1 are connected to one redundancy main bit line RMBLT0 via a switch unit 34 in one pair. It has a bit line structure.

In addition, the low redundancy memory cell array block 12 and the common redundancy memory cell array block 14 have the same configuration as the sub memory block 8 and the column redundancy memory block 10 shown in FIG. 3.

4A and 4B are operation timing diagrams illustrating a read operation of the embodiment shown in FIG. 1.

4A is a timing diagram illustrating a case where high level data is read.

First, the sub bit lines SBL0 and SBL1, the main bit lines MBLT0 and MBLB0, and the sub bit line sense amplifier control signal SBLVOL are precharged to the half voltage HVCC in the precharge period t0. In general, the half voltage HVCC has a half value of the high level data voltage VCC.

The input address is decoded to activate the selected word line WL0 in the address decoding section t1.

The selected word line WL0 is activated in the cell data sensing period t2 so that the high level data stored in the memory cell 22 is transferred to the sub bit line SBL0 by charge sharing.

In the sub bit line amplification period t3, the sub bit line sense amplifier control signal SBLVOL is activated to a low level, and the potential of the reference sub bit line SBL1 is amplified to a low level by the sub bit line sense amplifier 24.

In the data transfer period t4, the switch control signal SBSWL is activated to a high level, so that the switch NM3 is turned on. Therefore, data carried on the sub bit line SBL0 is transferred to the main bit line MBLT0. At this time, the potential of the reference main bit line MBLB0 is lowered to a predetermined level.

In the main bit line amplification period t5, the data loaded on the main bit line MBLT0 is amplified to a high level, and the reference main bit line MBLB0 is amplified to a low level. At this time, since the switch NM3 is turned on, the potential of the sub bit line SBL0 is also amplified to a high level to restore the data destroyed by the charge distribution in the cell data sensing period t2.

4B is an operation timing diagram when reading low level data.

First, the sub bit lines SBL0 and SBL1, the main bit lines MBLT0 and MBLB0, and the sub bit line sense amplifier control signal SBLVOL are precharged to the half voltage HVCC in the precharge period t0.

The input address is decoded to activate the selected word line WL0 in the address decoding section t1.

The selected word line WL0 is activated in the cell data sensing period t2, and low-level data stored in the memory cell 22 is transferred to the sub bit line SBL0 by charge sharing.

In the sub bit line amplification period t3, the sub bit line sense amplifier control signal SBLVOL is activated to a low level, and the data loaded on the sub bit line SBL0 is amplified to a low level by the sub bit line sense amplifier 24.

In the data transfer period t4, the switch control signal SBSWL is activated to a high level, so that the switch NM3 is turned on. Therefore, data carried on the sub bit line SBL0 is transferred to the main bit line MBLT0. At this time, the potential of the reference main bit line MBLB0 is lowered to a predetermined level.

In the main bit line amplification period t5, the data loaded on the main bit line MBLT0 is amplified to a low level, and the reference main bit line MBLB0 is amplified to a high level.

Meanwhile, when the currently input address is an address for selecting a fail memory cell, a redundancy memory cell of the replaced column redundancy memory block 10 or a redundancy memory cell of the low redundancy memory cell array block 12 is selected to perform a read operation. In this case, the operation is implemented in the same manner as the above operation according to the operation timing diagrams disclosed in FIGS. 4A and 4B.

5 is a block diagram illustrating a memory block test circuit according to the present invention.

The memory cell array block test circuit includes a redundancy coding unit 34, a main address decoder control unit 36, a redundancy address decoder control unit 38, a main address decoder 40, a redundancy address decoder 42, and a main memory cell array block ( 44, a redundancy memory cell array block 46, and a redundancy test mode detector 48.

The main address decoder 40 decodes the input address ADD to select the corresponding word line of the main memory cell array block 44.

The redundancy address decoder 42 decodes the input address ADD to select the corresponding word line of the redundancy memory cell array block 46.

The redundancy coding unit 34 activates the control signal CON to deactivate the main address decoder 40 when the input address ADD is an address signal for the fail cell, and activates the redundancy address decoder 42.

The main address decoder controller 36 generates the main control signal MCON according to the test mode detection signal TMD output from the redundancy test mode detector 44 regardless of the control signal CON output from the redundancy coding unit 34 in the test mode. To control the active state of the main address decoder 40. That is, when the control signal CON is deactivated, the main address decoder 40 is activated when the test mode detection signal TMD is inactivated, and the main address decoder 40 is deactivated when the control signal CON is activated. On the other hand, when the test mode detection signal TMD is activated, the main address decoder 40 is deactivated regardless of the control signal CON.

The redundancy address decoder control unit 38 generates the redundancy control signal RCON according to the test mode detection signal TMD output from the redundancy test mode detection unit 44 regardless of the control signal CON output from the redundancy coding unit 34 in the test mode. The active state of the redundancy address decoder 42 is controlled. That is, when the test mode detection signal TMD is inactivated, the redundancy address decoder 42 is deactivated when the control signal CON is deactivated, and the redundancy address decoder 42 is activated when the control signal CON is activated. On the other hand, when the test mode detection signal TMD is activated, the redundancy address decoder 42 is activated regardless of the control signal CON.

When the redundancy test mode detector 48 enters the test mode and the test mode signal TM is activated, the redundancy test mode detector 48 activates the test mode detection signal TMD and outputs the test mode detection signal TMD to the main address decoder control unit 36 and the redundancy address decoder control unit 38. Therefore, when the test mode signal TM is activated, the test mode detection signal TMD is activated and the redundancy address decoder 42 is activated regardless of the state of the control signal CON output from the redundancy coding unit 48.

As described above, since the redundancy test mode detection unit 48 activates the redundancy address decoder 42 regardless of the address ADD input in the test mode, the redundancy test mode detection unit 48 can change the corresponding redundancy addresses in order to test all the redundancy memory cells. have.

As described above, the memory device having a hierarchical bit line structure according to the present invention has an effect of reducing bit line capacitance to cell capacitance by hierarchically configuring bit lines.

In addition, the present invention has the effect of reducing the total number of bit lines by merging the main bit lines.

In addition, the present invention has the effect of improving the yield by testing all the redundancy memory cells in the test mode.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1 is a block diagram illustrating a major part of a memory device having a hierarchical bit line structure according to the present invention.

FIG. 2 is a conceptual diagram illustrating a method of replacing a fail row with a redundancy row and a fail column with a redundancy column in the embodiment illustrated in FIG. 1.

3 is a detailed circuit diagram illustrating a sub memory block and a column redundancy memory cell array block shown in FIG. 1.

4A and 4B are operation timing diagrams showing a read operation of the embodiment shown in FIG.

5 is a block diagram illustrating a memory block test circuit in accordance with the present invention.

Claims (11)

A hierarchical bit line structure having a plurality of main memory cell array blocks having a hierarchical bit line structure having a main bit line connected to a plurality of sub bit lines, and a redundancy main bit line having a plurality of redundant sub bit lines connected thereto. A memory block including a plurality of redundancy memory cell array blocks having a plurality of redundancy memory cells; A plurality of main bit line sense amplifiers for sensing and amplifying data carried on the main bit line; And And a word line driving block for driving a word line to which the selected memory cell is connected. The method of claim 1, wherein the redundancy memory cell array block A plurality of low redundancy memory cell array blocks; And 12. A memory device having a hierarchical bit line structure comprising a plurality of column redundancy memory cell array blocks. The method of claim 2, And wherein the low redundancy memory cell array block comprises a column redundancy memory cell array. The method of claim 1, wherein the main memory cell array block A plurality of sub bit lines connected with a plurality of memory cells and connected to the main bit lines; And a plurality of sub bit line sense amplifiers for sensing and amplifying data carried on the sub bit lines. The method of claim 4, wherein And the main memory cell array block further comprises transfer means for transferring data carried in the sub bit line to the main bit line. The method of claim 1, The redundancy memory cell array block has a hierarchical bit line structure, wherein the redundancy memory cell array block has the same structure as the main memory cell array block. The memory device of claim 6, wherein the low redundancy memory cell array block comprises: A plurality of redundancy sub bit lines connected to a plurality of redundancy memory cells and connected to the main bit lines; And And a plurality of redundancy sub-bit line sense amplifiers for sensing and amplifying the data carried on the redundancy sub-bit lines. The method of claim 6, wherein the column redundancy memory cell array block A plurality of redundancy sub bit lines connected to a plurality of redundancy memory cells and connected to the main bit lines; And And a plurality of redundancy sub-bit line sense amplifiers for sensing and amplifying the data carried on the redundancy sub-bit lines. The method of claim 1, And a test block for testing all of the redundancy memory cells of the redundancy memory cell array block in a test mode. The method of claim 9, wherein the test block A main address decoder for decoding the input address and selecting a word line corresponding to the address of the normal sub memory cell array block; A redundancy address decoder configured to decode the address to select a word line corresponding to the address of the redundancy memory cell array block; Redundancy decoding means for deactivating the main address decoder and activating the redundancy address decoder when the address is an address for a fail memory cell; And Redundancy test mode detecting means for deactivating the main address decoder in a test mode and activating the redundancy address decoder. The method of claim 10, In the normal operation, the active state of the main address decoder is controlled according to the signal output from the redundancy coding means, and in the test mode, the active state of the main address decoder is controlled according to the signal output from the redundancy test mode detecting means. Main address decoder control means; And In the normal operation, the active state of the redundancy address decoder is controlled according to the signal output from the redundancy coding means, and in the test mode, the active state of the redundancy address decoder is controlled according to the signal output from the redundancy test mode detecting means. And a redundancy address decoder control means.