KR20050079535A - Redundancy circuit for a semiconductor device - Google Patents

Abstract

The present invention relates to a redundancy circuit of a semiconductor device, by arranging fuses in an array form, dividing the addresses to be detected into two groups and decoding them, and selecting one of the fuse arrays using a decoded signal to detect the replaced address. A redundancy circuit of a semiconductor device is proposed that can have a fast response speed in detecting an address to be replaced by redundancy.

Description

Redundancy circuit for a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundancy circuit of a semiconductor device, and more particularly, to a redundancy circuit capable of increasing the response speed of a redundancy circuit.

In general, a semiconductor device has a redundancy block in order to improve the yield by repairing only a specific address where a defect occurs when a device failure occurs. The speed reduction of the redundancy block is related to the signal placement in the chip and the fuse used in the redundancy. That is, a fuse for address coding is used to repair only a specific address.

In general, the current flow is sensed to transmit redundancy data to the outside. The current flowing through these fuses means that they must pass through the NMOS transistors and fuses in the corresponding pass, which must wait as long as the multiple NMOS transistors and fuses are charged. This self-provided type determines the response speed, and thus, the more the address to be detected, the longer the response time becomes.

Accordingly, an object of the present invention is to solve the above problems by coding an address to be detected and applying a signal corresponding to word line and bit line coding, respectively, so that only one fuse response time is waited for fast response speed. It is to provide a redundancy circuit of a semiconductor device.

The redundancy circuit of the semiconductor device according to the present invention is arranged in a matrix form and includes a plurality of redundancy fuse cells composed of a transistor and a fuse connected to a source terminal of the transistor, and a gate terminal of the transistor in the row direction of the redundancy fuse cell. A plurality of connected redundancy word lines, a plurality of redundancy bit lines connected to a source terminal of the transistor in the column direction of the redundancy fuse cell, and a plurality of redundancy bit lines and a redundancy IO signal output terminal connected to a plurality of Y A plurality of transfer transistors are respectively driven in accordance with the decoding signal, a precharge transistor for applying a predetermined precharge voltage to the plurality of redundancy bit lines, and a common ground line connected to the fuse.

The method further includes a first decoder for coding an external address signal and transmitting an X decoding signal to the plurality of redundancy word lines, and a second decoder for coding the address signal and transmitting a Y decoding signal to the plurality of transmission transistors.

The transistor constituting the redundancy fuse cell may use an NMOS transistor, the transfer transistor may use an NMOS transistor, and the precharge transistor may use a PMOS transistor connected between a power supply voltage and the redundancy bit line.

The present invention also provides a redundancy circuit of a semiconductor device including a plurality of fuse blocks which decode an address signal and output redundancy IO signals, respectively, in accordance with a cutting state of a plurality of redundant fuse cells arranged in a matrix.

The redundancy fuse cell may include a transistor and a fuse connected to a source terminal of the transistor.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

1 is a block diagram of an overall redundancy circuit of the present invention.

2 is a circuit diagram of a single fuse block of the present invention.

Referring to FIGS. 1 and 2, the redundancy circuit of the present invention codes an address signal Add <0: N> so that a plurality of redundancy IO signals RIO are generated by cutting the plurality of fuses arranged in matrix with the decoding signal. And a plurality of fuse blocks 100-1 to 100-N for outputting < 0: N>.

The fuse block 100 is arranged in a matrix form, and includes a plurality of redundancy fuse cells 110 composed of a transistor F1 and a fuse F1 connected to a source terminal of the transistor T1, and a redundancy fuse cell 110. A plurality of redundancy word lines RWL <1: N> connected to a gate terminal of the transistor T1 in a row direction and a source terminal of the transistor T1 in a column direction of the redundancy fuse cell 110; Connected between a plurality of redundancy bit lines RBL <1: N> and a plurality of redundancy bit lines RBL and a redundancy IO signal RIO output terminal in accordance with a plurality of Y decoding signals RY <1: N>. A plurality of transfer transistors TT-1 to TT-N each driven, precharge transistors PT-1 to PT-N for applying a predetermined precharge voltage to the plurality of redundancy bit lines RBL, It includes a common ground line (GND) connected to the fuse (F1).

A first decoder (not shown) for coding an external address signal Add <0: N> and transmitting an X decoding signal to a plurality of redundancy word lines RWL, and an address signal Add <0: N> A second decoder (not shown) for coding and transmitting the Y decoding signal RY to the transmission transistors TT-1 to TT-N may be further included. The first and second decoders may be formed through separate decoding circuits, or may use X and Y decoders used in semiconductor devices.

The transfer transistors TT-1 to TT-N are preferably NMOS transistors. The precharge transistors PT-1 to PT-N preferably use PMOS transistors connected between the power supply voltage and the redundancy bit line RBL and driven according to the ground power supply. It is preferable to use an NMOS transistor as the transistor T1 constituting the redundancy fuse cell 110.

The operation of the redundancy circuit of the present invention having the above-described configuration is as follows.

When a cell corresponding to a predetermined address has gone through a predetermined cell test, it is preferable to cut the fuse in the redundancy circuit corresponding to the address where the closed date occurs. Through this, when an address having a closed day is input, the redundancy circuit of the present invention generates the corresponding IO signal. Of course, as in the opposite case, the fuse corresponding to the remaining addresses may be cut except for the fuse corresponding to the address at which the failure occurred.

The row direction and column direction are determined according to the X decoding signal and the Y decoding signal RY generated according to the external address signal Add <0: N>, thereby detecting the replaced address by turning on the corresponding transistor. Done. The fuse corresponding to the replaced address must be determined to be cut or connected according to the information of the corresponding IO. When the unit fuse cell detects a replacement address, this information corresponds to one information of the IO to be replaced, and it is preferable to configure the number of IOs to be coded so that each output of the unit fuse block indicates the IO to be replaced. Do.

When an address signal Add <0: N> to be detected is applied to the redundancy circuit, the X signal is applied to each of the redundancy word lines RWL <1: N> by coding it. The transistor sharing the redundancy word lines RWL <1: N> in the fuse block 100 is turned on. On the other hand, the redundancy bit lines RBL <1: N> are precharged to a predetermined precharge voltage (power supply voltage Vcc, logic high state) by the precharge transistors PT-1 to PT-N.

The turned-on transistor T1 changes the state of the precharge voltage of the redundancy bit line RBL according to the state of the fuse F1 connected to the source terminal. That is, when the fuse F1 is connected, the precharge voltage of the redundancy bit line RBL is discharged, and the ground power supply Vss is applied to the redundancy bit line RBL, and the redundancy bit when the fuse F1 is cut off. The line RBL maintains the precharge voltage as it is.

According to the address to be detected, the Y decoding signal RY is applied to turn on any one of the plurality of readout transfer transistors TT-1 to TT-N. The IO signal RIO is output according to the voltage state of the redundancy bit line RBL to which the turned-on transfer transistors TT-1 to TT-N are connected.

For example, when the fuse of the A redundancy fuse cell of FIG. 2 is blown and an address signal corresponding thereto is applied, the external address signal Add <0: N> is decoded and the redundancy word line RWL <1: N> is decoded. ), The second redundancy word line signal RWL2 becomes a high level to turn on the transistor in the A redundancy fuse cell, and the second Y decoding signal RY-2 of the Y decoding signals RY <1: N> At a high level, the second transmission transistor TT-2 is turned on.

At this time, since the fuse of the A fuse cell is cut off, the precharge signal having the high level applied by the second precharge transistor PT-2 is received through the second transfer transistor TT-2. Will be printed).

If the fuse of the A fuse cell is not disconnected, the precharge signal having a high level applied by the second precharge transistor PT-2 by the transistor and the fuse in the A fuse cell is the ground power supply GND (Vss). Will fall into. The turned-on second transfer transistor TT-2 outputs a low level ground power supply as an IO signal.

As described above, since the present invention waits only one fuse cell, that is, one transistor and one fuse response time, a response speed faster than that of the related art can be obtained.

As described above, the present invention arranges the fuses in an array form, decodes the addresses to be detected into two groups, and decodes each of them, and selects one of the fuse arrays by using the decoded signal to detect the replaced address. It can have a fast response speed when detecting the address to be replaced.

1 is a block diagram of an overall redundancy circuit of the present invention.

2 is a circuit diagram of a single fuse block of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: fuse block 110: redundancy fuse cell

Claims (5)

A plurality of redundancy fuse cells arranged in a matrix and composed of a transistor and a fuse connected to a source terminal of the transistor; A plurality of redundancy word lines connected to gate terminals of the transistors in a row direction of the redundancy fuse cells; A plurality of redundancy bit lines connected to source terminals of the transistor in a column direction of the redundancy fuse cell; A plurality of transmission transistors connected between the plurality of redundancy bit lines and the redundancy IO signal output stages to respectively drive the plurality of Y decoding signals; A precharge transistor for applying a predetermined precharge voltage to the plurality of redundancy bit lines; And Redundancy circuit of a semiconductor device comprising a common ground line connected to the fuse. 2. The apparatus of claim 1, further comprising: a first decoder for coding an external address signal to transmit an X decoded signal to the plurality of redundancy word lines; And And a second decoder configured to code the address signal to transmit a Y decoding signal to the plurality of transfer transistors. The PMOS transistor of claim 1, wherein the transistor constituting the redundancy fuse cell uses an NMOS transistor, the transfer transistor uses an NMOS transistor, and the precharge transistor is a PMOS transistor connected between a power supply voltage and the redundancy bit line. Redundancy circuit of a semiconductor device using. A redundancy circuit of a semiconductor device comprising a plurality of fuse blocks for decoding an address signal, and outputting a redundancy IO signal according to the decoded signal and a cut state of a plurality of redundant fuse cells arranged in a matrix. The redundancy circuit of claim 4, wherein the redundancy fuse cell comprises a transistor and a fuse connected to a source terminal of the transistor.