KR20050077860A - Method for forming cu interconnection line in semiconductor device - Google Patents

Abstract

A copper wiring formation method is disclosed. An insulating film pattern including an opening for copper wiring is formed on the wafer. A dielectric barrier film for preventing copper diffusion is deposited on the opening surface and the top surface of the insulating film pattern. The dielectric barrier layer is partially etched to remove the dielectric barrier layer formed under the opening via layer. The copper film is filled to fill the inside of the opening. The copper film is polished to expose a dielectric barrier film on the insulating film pattern. A capping metal film is selectively deposited on the exposed copper film. According to the above method, it is possible to form a copper film having a uniform surface in the wafer. In addition, the copper wiring process is simplified, and the reliability of the copper wiring is improved.

Description

Method for forming Cu interconnection line in semiconductor device

The present invention relates to a metal wiring forming method of a semiconductor device. More specifically, it is related with the metal wiring formation method which consists of copper.

As semiconductor devices are becoming highly integrated, line widths, thicknesses, and spacings between wirings are gradually decreasing. In addition, the size of the contact electrically connecting the conductive patterns is gradually decreasing. Therefore, there is a need for a metal material having a low resistance in order to form a fine line width electrical wiring without reducing the response speed. Further, in order to increase the density of devices, the wiring must be formed in a multilayer structure.

In the conventional semiconductor device, the wiring structure using aluminum is mainly used due to the low contact resistance and the ease of processing. However, as semiconductor devices have been highly integrated, the aluminum wiring structure has been limited in use due to poor bonding spikes, electromigration problems, etc., and also has a lower resistance than aluminum for improving the response speed of the semiconductor device. This is required.

Accordingly, recently, copper wiring having a lower resistance than that of aluminum is mainly used. However, since copper is rapidly diffused in silicon or most metal layers and difficult to be etched by a conventional photolithography process, copper is generally formed as an electrical wiring by a damascene process.

A method of forming a copper wiring by the damascene process will be briefly described. An interlayer insulating film is formed on a wafer and patterned to form a copper wiring forming trench or hole. Before depositing the copper, a barrier metal film is formed to prevent diffusion of copper, and then a copper film is formed to fill the trench or hole. Subsequently, a first chemical mechanical polishing process for removing the copper film and a second chemical mechanical polishing process for removing the barrier metal film are sequentially performed to form a wiring structure. Subsequently, a diffusion barrier film made of an insulating material is deposited for etching prevention and copper diffusion prevention for subsequent upper wiring formation.

According to the method, since the copper polishing and the barrier metal film polishing must be performed through each chemical mechanical polishing process, there is a problem in that the process cost is increased. In addition, as the polishing process is performed twice, the film becomes uneven in the same wafer, and there is a problem in that the film becomes uneven between each of the wafers in progress. In addition, dishing of copper wiring is likely to occur by the polishing step.

After the chemical mechanical polishing process, an electromigration defect occurs at the interface between the exposed copper surface and the diffusion barrier film formed on the copper surface. In order to reduce the electromigration defect, there is a need for a method capable of enhancing the adhesion between the copper surface and the diffusion barrier.

As an example of a method for enhancing the adhesion, a method of selectively depositing a metal cladding film only on a copper surface formed after performing the chemical mechanical polishing process is disclosed in Korean Patent Laid-Open Publication No. 2002-10505. However, after the process of depositing the metal cladding film, a process of depositing an etch stop layer for preventing excessive etching due to misalignment at the time of forming the upper wiring has to be further performed. .

Accordingly, it is an object of the present invention to provide a method for forming a copper wiring in which uniformity is improved by wafer and by position in the wafer, electromigration is reduced, and the process is simplified.

The present invention to achieve the above object,

An insulating film pattern including an opening for copper wiring is formed on the wafer. A dielectric barrier film for preventing copper diffusion is deposited on the opening surface and the top surface of the insulating film pattern. The dielectric barrier layer is partially etched to remove the dielectric barrier layer formed under the opening via layer. The copper film is filled to fill the inside of the opening. The copper film is polished to expose a dielectric barrier film on the insulating film pattern. A capping metal film is selectively deposited on the exposed copper film.

According to this method, since the barrier metal film used conventionally is not used, the grinding | polishing process for copper wiring formation can be shortened after 1 time. For this reason, the uniformity of the said copper wiring improves. In addition, by forming the capping metal film, it is possible to minimize the electromigration failure. In addition, there is no need to form a separate etch stop layer after the capping metal film is formed, thereby simplifying the process.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1F are cross-sectional views illustrating a method of forming a copper wiring in a semiconductor device according to a first embodiment of the present invention.

Referring to FIG. 1A, a lower interlayer insulating layer 12 is formed on a semiconductor wafer 10 on which devices such as transistors (not shown) are formed. The lower interlayer insulating layer 12 includes a conductive pattern 14 electrically connected to copper wires formed by a subsequent process, and an upper surface of the conductive pattern 14 is the lower interlayer insulating layer 12. Exposed to the surface.

A first etch stop layer 16 and a metal interlayer insulating layer 18 are formed on the lower interlayer insulating layer 12. Subsequently, the metal interlayer insulating layer 18 and the first etch stop layer 16 of the portion where the copper wiring electrically connected to the conductive pattern 14 will be formed are selectively etched to form the wiring forming opening 20. do. The opening 20 may have a trench, a via hole, or a trench and a via hole.

In the present embodiment, the opening 20 has a dual damascene structure in which trenches and via holes are provided at the same time. Hereinafter, the opening forming method having the dual damascene structure will be briefly described.

First, a lower metal interlayer insulating film 18a for forming via holes, a second etch stop film 19, and an upper metal interlayer insulating film 18b for forming trenches are formed on the first etch stop layer 16. do. By performing a general photolithography process, the upper metal interlayer insulating layer 18b, the second etch stop layer 19, and the lower metal interlayer insulating layer 18a are sequentially etched, and then the lower first etch stop layer 16 is performed. ) Is etched to form via holes exposing the conductive pattern 14. Subsequently, the photoresist layer is filled while the via hole is filled, and a photo process of patterning a line type trench through the via holes is performed. The upper metal interlayer insulating layer 18b is etched to form trenches.

As described above, an opening of the dual damascene structure may be formed by first forming a via hole and then forming a trench. Alternatively, the opening of the dual damascene structure may be formed by first forming a trench and then forming a via hole. have.

Referring to FIG. 1B, a dielectric barrier layer 22 made of a dielectric material is deposited on the surface of the wiring forming opening 20 and the upper surface of the metal interlayer insulating layer 18. The dielectric barrier film 22 is a film for preventing the copper formed in the opening 20 from being diffused into the metal interlayer insulating film 18 by a subsequent process. Examples of the material that can be used as the dielectric barrier film 22 include silicon nitride (SiN), silicon carbide (SiC), or silicon carbide nitride (SiCN).

Hereinafter, a portion where the via layer will be formed in the opening will be referred to as an opening via layer, and a portion where the copper line will be formed in the opening will be described as an opening trench.

The dielectric barrier layer 22 may have a thicker thickness of the layer formed on the upper surface of the metal interlayer insulating layer 18 than the bottom portion of the via layer 20. This is because the dielectric barrier film 22 formed at the bottom portion of the via layer 20 is to be removed through a subsequent process. In order to form the dielectric barrier film 22 having the shape, the dielectric barrier film 22 is deposited by a plasma enhanced chemical vapor deposition (PE-CVD) method.

Referring to FIG. 1C, the dielectric barrier layer 22a formed on the bottom of the via layer 20 via layer is removed. The removal process may be performed by anisotropically etching the dielectric barrier layer 22a so that all of the dielectric barrier layer 22a formed at the bottom of the via layer 20 may be removed. Since the dielectric barrier layer 22a is formed on the upper surface of the metal interlayer insulating layer 18 thicker than the bottom portion of the via layer 20 via layer, the dielectric barrier layer 22a is formed on the inner bottom of the opening 20 by the anisotropic etching. Even if all of the dielectric barrier film 22a is removed, the dielectric barrier film 22a formed on the sidewall of the opening 20, the bottom of the opening trench and the top surface of the metal interlayer insulating film 18 remains at a predetermined thickness.

Referring to FIG. 1D, a seed layer (not shown) is formed on the dielectric barrier layer 22a and the lower conductive pattern 14. The seed film is preferably formed of copper. Specifically, it is formed of a copper film deposited by physical vapor deposition (PVD), a copper film deposited by chemical vapor deposition (CVD), or a laminated film of the PVD copper film and the CVD copper film. can do. The seed layer may be formed of silver (Ag) or ruthenium (Ru) in addition to copper.

Subsequently, a copper film 24 is formed on the seed film to fill the inside of the opening 20. The copper film 24 may be deposited by an electroplating method or a CVD method, and more preferably, the copper film 24 is deposited by an electroplating method in order to embed the copper in the narrow openings 20 without voids.

The process of filling the opening 20 with copper varies depending on the size of the opening 20, and the gap fill characteristics of the copper are changed by the combination of additives in the electrolyte used during the electroplating. I can regulate it.

Referring to FIG. 1E, the overdeposited copper is removed to form the copper interconnect 26 so that the copper film remains only inside the opening 20. The copper removal may be performed by a polishing process. The polishing process is preferably performed using a slurry in which the copper film 24 is quickly removed while the dielectric barrier film 22a under the copper film 24 is hardly removed. To this end, the polishing process is carried out in an abrasive free slurry polishing (AFP) process using a slurry consisting of only water and chemicals, not including abrasive particles.

When the AFP process is performed, the film is mainly removed by chemical polishing by chemical and by mechanical polishing by contact between the wafer and the polishing pad, and the film is not removed by mechanical polishing by abrasive particles. However, the copper film 24 is mainly removed by chemical polishing by the chemical and mechanical polishing by contact between the wafer and the polishing pad, and the dielectric barrier film 22a is in contact with the chemical polishing and the wafer and the polishing pad. It is hardly removed by mechanical polishing by.

That is, by using the AFP process having excellent copper removal ability, it is possible to minimize the occurrence of copper residue on the dielectric barrier 22a film, and selectively select the dielectric barrier film 22a on the copper interlayer insulating film 18. You can leave The dielectric barrier layer 22a serves as an etch stop layer for preventing excessive etching in the subsequent formation of the upper wiring.

At this time, since the process of removing the dielectric barrier film 22a is not required by another polishing process, the copper wiring 26 is formed only by one polishing process for removing the copper film 24. Therefore, the polishing process can be reduced as compared with the case of using a conventional metal barrier film, thereby simplifying the process and reducing the process cost.

In addition, since the metal interlayer insulating film 18 under the dielectric barrier film 22a is not consumed at all during the polishing process, the thickness of the metal interlayer insulating film 18 can be uniformly formed.

In addition, as the polishing process is performed several times, resistance non-uniformity generated according to the degree of polishing of each pattern in each position on the wafer and the state of the polishing pad used for each wafer to wafer. The resulting nonuniformity can be intensified. Therefore, an effect of increasing the polishing uniformity can be expected due to the simplification of the polishing process.

Referring to FIG. 1F, a capping metal film 28 is selectively formed on the copper wire 26. The capping metal layer 28 may be formed by an electroless plating method, for example, CoWP or CoWB. Alternatively, the capping metal layer 28 may be formed by depositing tungsten (W) by chemical vapor deposition. By depositing the capping metal layer 28, the interfacial adhesion with the upper wiring formed by the subsequent process may be increased, thereby reducing the electro migration.

Thereafter, although not shown, the same processes are repeatedly performed to form the upper wiring.

Example 2

2A to 2F are cross-sectional views illustrating a method of forming a copper wiring in a semiconductor device according to a second embodiment of the present invention.

Referring to FIG. 2A, a metal interlayer insulating film 102 is formed on a wafer 100 made of a semiconductor material. Although not shown on the wafer 100, a conductive pattern for connecting with elements such as transistors and copper wiring formed by a subsequent process is formed.

The openings 104 may be formed by selectively etching a portion of the interlayer insulating layer 102 in which wirings are to be formed. The openings have different opening widths for each position formed in the wafer. In detail, in the semiconductor device, first openings 104a having a relatively small width are formed in a cell region in which a pattern is formed very densely, and a second having a relatively wider width than the cell region in the ferry and core regions. Openings 104b are formed.

Each of the openings 104 has a dual damascene structure in which trenches and via holes are provided at the same time, and FIGS. 2A to 2F are cross-sectional views of portions in which only trenches are formed. Thus, it is noted that the via holes are not shown in the respective cross sections.

Referring to FIG. 2B, a dielectric barrier film 106 made of a dielectric material is deposited on the surfaces of the first and second openings 104a and 104b and the upper surface of the metal interlayer insulating film 102. Examples of the material that can be used as the dielectric barrier film 106 include silicon nitride (SiN), silicon carbide (SiC), or silicon carbide nitride (SiCN).

The dielectric barrier film 106 is deposited by a plasma enhanced chemical vapor deposition (PE-CVD) method. The dielectric barrier film formed by the above method is thinly formed on the bottom portion of the via hole, not shown, and relatively thick on the bottom portion of the trench and the top surface of the metal interlayer insulating layer.

The dielectric barrier layer 106 formed on the bottom of the via hole (not shown) inside the first and second openings 104a and 104b may be selectively removed, and the inside of the first and second openings 104a and 104b may be removed. The dielectric barrier film 106 formed at the bottom of the trench is left to a predetermined thickness. The removal process may be performed by a front side anisotropic etching process.

Subsequently, a seed layer (not shown) is formed on the dielectric barrier layer 106 and the bottoms of the first and second openings 104a and 104b. The seed film is preferably formed of copper.

Referring to FIGS. 2C and 2D, a copper film is formed by an electroplating method to fill the first and second openings, and at the same time, the pad and the wafer come into contact with an area where the copper film is overplated and protrudes. Electrochemical mechanical deposition (ECMD) is performed on the contact portion of the wafer to selectively prevent plating. By performing the above process, it is possible to reduce the generation of the step difference of the copper film caused by the difference in the opening width between the first and second openings.

In more detail, when the copper film is filled using the electroplating method, as shown in FIG. 2C, the inside of the first opening 104a is completely filled with copper, but the inside of the second opening 104b. The copper will be partially filled. If the formation of the copper film continues in this manner, the step of the copper film between the first opening region and the second opening region is severely generated. This step will lead to defects such as dishing in subsequent chemical mechanical polishing process times.

However, when the ECMD process is performed, the relatively high stepped first copper film 110 formed in the cell region comes into contact with the pad, thereby suppressing plating of the copper film, and forming a relatively low level formed in the ferry region. The second copper film 112 having the step does not contact the pad. Therefore, as shown in FIG. 2D, the thickness of the copper film is uniformly formed regardless of the opening width of the opening, thereby reducing the occurrence of defects such as dishing in the subsequent polishing process.

Referring to FIG. 2E, the overdeposited copper is removed by electropolishing so that the copper film remains only inside the first and second openings 104a and 104b to form a copper interconnect 114.

The electropolishing method is a method of electrically plating copper and changing electrodes to oxidize copper deposited on the wafer. In order to perform polishing by the electropolishing method, it must be conducted through copper formed on the wafer. Therefore, in order to prevent the electropolishing from being performed any more by locally removing the copper, a multiple electric polishing bath having internal partitions can be applied to each of the plurality of regions of the wafer or Preference is given to using multiple cathods.

When the polishing process is performed by the electropolishing method, a stop point of polishing may be detected by detecting a change in current, voltage, or reflectivity.

After removing the overdeposited copper by the electropolishing method, it is more preferable to perform an AFP process for completely removing the copper residue remaining on the dielectric barrier film 106. The electropolishing method is not easy to remove the copper residues that remain locally because the copper must be conducted at the wafer surface to remove the copper.

In the case of removing the overdeposited copper by the electropolishing method, the upper portion of the copper film filled in the first and second openings 104a and 104b is dished so that defects such as uneven wiring resistance in each region of the wafer are eliminated. There is an advantage that can be minimized.

Referring to FIG. 2F, a capping metal film 116 is selectively formed on the copper wiring 114. The capping metal layer 116 may be formed by an electroless plating method, for example, CoWP or CoWB. Alternatively, the capping metal layer 116 may be formed by depositing tungsten by chemical vapor deposition.

Thereafter, although not shown, the same process may be repeatedly performed to form the upper wiring.

Example 3

Hereinafter, a method for forming a copper wiring of a semiconductor device according to the third embodiment of the present invention will be described. The copper wiring forming method according to the third embodiment is the same as the second embodiment except for filling the copper film in the first and second openings. Therefore, redundant description is omitted.

Performing the same process as described in FIGS. 2A and 2B results in openings having widths of at least two groups or more. Specifically, in the semiconductor device, first openings having a relatively small width are formed in the cell region where the pattern is formed very densely, and second openings having a relatively wider width are formed in the ferry and core regions than the cell region. do.

After depositing a dielectric barrier film made of a dielectric material on the surfaces of the first and second openings and the upper surface of the metal interlayer insulating film, the dielectric barrier film on the bottom of the via hole inside the first and second openings is selectively removed.

The inside of the first and second openings is filled with a copper film using electroplating. At the time of the said electroplating for the said copper film formation process, the composition of the electrolyte solution used is changed one or more times.

Specifically, plating is performed using an electrolyte composition having excellent gap fill characteristics until the first openings having a relatively small width are filled, and an electrolyte composition having excellent planarization characteristics when filling the second wide openings. The electrolyte composition having excellent gap fill and planarization properties can be adjusted by adjusting the types and concentrations of the additives. Through such step electroplating, it is possible to reduce the step of the copper film appearing along the width of the opening, thereby reducing dishing in the copper film polishing process.

Subsequently, the processes of FIGS. 2E and 2F are performed in the same manner to form a copper wiring. Alternatively, copper wirings may be formed in the same manner as in FIGS. 1E and 1F according to the first embodiment.

As described above, according to the present invention, the uniformity of the copper wiring can be improved and the electromigration defect can be minimized. In addition, there is no need to form a separate etch stop layer after the capping metal film is formed, thereby simplifying the process.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

1A to 1F are cross-sectional views illustrating a method of forming a copper wiring in a semiconductor device according to a first embodiment of the present invention.

2A to 2F are cross-sectional views illustrating a method of forming a copper wiring in a semiconductor device according to a second embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 100: wafer 18, 102: metal interlayer insulating film

20: opening 22, 106: dielectric barrier film

24: copper film 26: copper wiring

28: capping metal film 104a: first opening

104b: second opening 110: first copper film

112: second copper film 116: capping metal film

Claims (12)

Forming an insulating film pattern including an opening for copper wiring on the wafer; Depositing a dielectric barrier layer for preventing diffusion of copper on the opening surface and an upper surface of the insulating layer pattern; Partially etching the dielectric barrier film so that the dielectric barrier film formed on the bottom of the opening bottom is removed; Filling a copper film to fill the inside of the opening; Polishing the copper film to expose a dielectric barrier film on the insulating film pattern; And Selectively depositing a capping metal film on the exposed copper film. The method of claim 1, wherein the dielectric barrier film is made of silicon nitride (SiN), silicon carbide (SiC), or silicon carbide nitride (SiCN). The method of claim 1, wherein the dielectric barrier film is formed by a plasma-enhanced chemical vapor deposition method such that the film is deposited thicker on a flat portion than on an inclined portion. The method of claim 1, wherein depositing copper inside the opening comprises: Depositing seed copper on the dielectric barrier film; And And plating a copper layer on the seed copper by an electroplating method. The method of claim 4, further comprising performing an electrochemical mechanical deposition process to reduce a copper pattern step after plating the copper. The method of claim 1, wherein the depositing of copper inside the opening is performed by a chemical vapor deposition method. The semiconductor device of claim 1, wherein the polishing of the copper is performed by a chemical mechanical polishing process using an abrasive free slurry after performing an electropolishing or an electropolishing process. How to form metal wiring. The metal wiring of claim 7, wherein a multiple electric polishing bath or a multiple cathod is used to ensure uniformity between wafers during the electropolishing process. Way. 8. The method of claim 7, wherein the polishing stop point is identified by measuring current, voltage, and reflectivity during the electrical polishing process. The method of claim 1, wherein the selective capping metal film is formed of CoWP, CoWB, or tungsten formed by a chemical vapor deposition method, which is formed by electroless plating. The method of claim 1, wherein the opening for copper wiring on the wafer has a dual damascene structure including a via hole and a trench. The method of claim 11, wherein the bottom of the bottom of the opening is a bottom of the via hole.