KR20050071959A - Circuit for detecting fail of dot clock, timing controller, and liquid crystal display device - Google Patents

Abstract

A dot clock fail detection circuit, a timing controller, and a liquid crystal display device are provided. The dot clock fail detection circuit is a circuit that detects whether a dot clock signal inputted to a timing controller of a liquid crystal display fails or generates a detection signal, and includes a logic circuit including a plurality of flip-flops and an inverter, and an OR circuit. It is provided. The logic circuit generates output signals in response to a clock signal generated from a clock generator such as a dot clock signal and an RC oscillator. An OR circuit generates the detection signal by ORing the output signals. The dot clock fail detection circuit may detect a fail of the dot clock when the dot clock signal is abnormally input to the timing controller.

Description

Circuit for detecting fail of dot clock, timing controller, and liquid crystal display device

The present invention relates to a liquid crystal display device, and more particularly, to a dot clock fail detection circuit, a timing controller and a liquid crystal display device including the same.

Liquid crystal display (LCD) devices have advantages of miniaturization, thinness, and low power consumption, and are used in notebook computers, office automation devices, and audio / video devices. In particular, an active matrix type liquid crystal display device using a thin film transistor as a switch element is suitable for displaying a dynamic image.

1 is a block diagram schematically illustrating a conventional liquid crystal display. Referring to FIG. 1, the liquid crystal display 100 may include an interface 110, a timing controller 130, a source driver 150, a gate driver 170, and an LCD panel. (LCD panel, 190). The timing controller is also referred to as a panel timing controller, and the resolution of the LCD panel 190 may be SXGA level or UXGA level.

The interface 110 may be a low voltage differential signal (LVDS) interface or a TTL interface, and input data RGB1 and a control signal between the graphic board (not shown) and the timing controller 130. Are used for the transmission of the signals (DCLK, DE, VSYNC, HSYNC).

The timing controller 130 controls the source driver 150 in response to the input data RGB1 and the control signals DCLK, DE, VSYNC, and HSYNC, which are pixel data transmitted through the interface 110. The driving output data RGB2 and the control signals MCLK, SPH, TP, REV, and POL are output, and the control signals CPV, STV, and OE driving the gate driver 170 are output. The output data RGB2 is image data finally displayed on the LCD panel 190.

Each of the control signals DCLK, DE, VSYNC, and HSYNC input to the timing controller 130 is a dot clock signal, a data enable signal, a vertical synchronization signal, and a horizontal synchronization signal. (horizontal synchronization) signal. Each of the control signals MCLK, SPH, TP, REV, and POL driving the source driver 150 includes a source clock signal, a horizontal start signal, a line latch signal, An alternative signal and a liquid crystal polarity reverse signal are shown. Each of the control signals CPV, STV, and OE driving the gate driver 170 represents a gate clock signal, a vertical start signal, and an output enable signal. Meanwhile, the dot clock signal DCLK serves as a reference signal for determining the output timing of the output data RGB2 and the control signals [MCLK, STH, TP, REV, POL], [CPV, STV, OE]. do.

The source driver and the gate driver 150 and 170 respectively respond to the output data RGB2 and the respective control signals [MCLK, STH, TP, REV, POL], [CPV, STV, OE]. Output signals SO and GO are generated to drive the LCD panel 190. That is, the source driver and the gate driver 150 and 170 serve as a driving circuit for driving the LCD panel 190.

Control signals for driving the source driver 150 and the gate driver 170 may be generated by using both a dot clock signal, a data enable signal, a vertical synchronization signal, and a horizontal synchronization signal (DCLK, DE, VSYNC, HSYNC). Or may be generated using only the dot clock signal and the data enable signal DCLK, DE.

However, when the dot clock signals DCLK_F1 and DCLK_F2 that fail due to the dot clock signal DCLK are input to the timing controller 130, a problem occurs in the liquid crystal display 100. Here, the dot clock signals DCLK_F1 and DCLK_F2 in which a fail is generated in the dot clock signal DCLK are high without being toggled for a predetermined time as in the example shown in FIG. 2 in the dot clock signal DCLK. It may be a signal that is maintained at a high level or a low level.

That is, when a fail occurs in the dot clock signal DCLK and the dot clock signal DCLK as the reference signal is not normally input to the timing controller 130, output data for driving the source driver 150 and the gate driver 170. (RGB2) and control signals [MCLK, STH, TP, REV, POL], [CPV, STV, OE] do not occur normally. As a result, an abnormal screen such as an unwanted pattern may be displayed on the LCD panel 190, and the liquid crystal of the LCD panel 190 may be deteriorated.

A first technical problem to be achieved by the present invention is to provide a dot clock fail detection circuit capable of detecting whether a dot clock signal has failed.

It is a second object of the present invention to provide a timing controller for controlling stable image data to be displayed on an LCD panel by using a detection signal which is an output of the dot clock fail detection circuit.

Another object of the present invention is to provide a liquid crystal display including the timing controller.

In order to achieve the first technical problem, a dot clock fail detection circuit according to the present invention relates to a circuit for detecting whether a dot clock signal input to a timing controller of a liquid crystal display is failing and generating a detection signal. A dot clock fail detection circuit according to the present invention includes a logic circuit for generating output signals in response to the dot clock signal and a predetermined clock signal, and an OR circuit for ORing the output signals to generate the detection signal. It features.

According to a preferred embodiment, the clock signal is generated from a clock generator included in the timing controller, the clock generator comprising an RC oscillator.

According to a preferred embodiment, the logic circuit comprises a first flip-flop for latching the clock signal in response to the dot clock signal to generate an inverted signal of a first output signal, and the clock in response to the dot clock signal. A second flip-flop for latching an inverted signal of the signal to generate a second output signal; and inverting the inverted signal of the first output signal in response to an inverted signal of the clock signal to produce one of the output signals. A third flip-flop for generating a third output signal and a ground voltage in response to the clock signal to generate a fourth output signal as one of the output signals, and being input through the sync set terminal; And a fourth flip-flop for setting the fourth output signal to a high level in response to an inverted signal of the second output signal.

According to a preferred embodiment, the first, second, third and fourth flip-flops are each D flip-flop.

In order to achieve the second technical problem, a timing controller according to the present invention relates to a timing controller of a liquid crystal display device including an LCD panel displaying image data. The timing controller according to the present invention includes a normal mode signal generator for generating a normal mode signal for controlling normal image data to be displayed on the LCD panel when a dot clock signal is normally input, and using the predetermined clock signal. A dot clock fail detection circuit that detects whether a dot clock signal is failed and generates a detection signal, and an abnormality that is activated when the detection signal indicates a fail of the dot clock signal to control to display stable image data on the LCD panel And a multiplexer for selecting and outputting one of the normal mode signal and the abnormal mode signal in response to the detection signal.

According to a preferred embodiment, the clock signal is generated from a clock generator included in the timing controller, the clock generator comprising an RC oscillator.

In order to achieve the third technical problem, a liquid crystal display according to the present invention relates to a liquid crystal display including an LCD panel for displaying image data. The liquid crystal display according to the present invention detects whether or not the inputted dot clock signal is failed using a predetermined clock signal, and if it is detected that it is not a fail according to the detection result, outputs a normal mode signal to the detection result. And a timing controller for outputting an abnormal mode signal when detected as a fail, and a driving circuit for driving the LCD panel in response to the normal mode signal or the abnormal mode signal, wherein the normal mode signal is transmitted to the LCD panel. Normal image data is controlled to be displayed, and the abnormal mode signal is characterized by controlling to display stable image data on the LCD panel.

According to a preferred embodiment, the clock signal is generated from a clock generator included in the timing controller, the clock generator comprising an RC oscillator.

The dot clock fail detection circuit according to the present invention can detect the failure of the dot clock when the dot clock signal is abnormally input to the timing controller. In addition, the timing controller according to the present invention can control the stable image data to be displayed on the LCD panel by selectively outputting the normal mode signal and the abnormal mode signal using the detection signal which is the output of the dot clock fail detection circuit. In addition, the liquid crystal display according to the present invention may display a stable screen by including the timing controller.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a block diagram illustrating a timing controller according to an embodiment of the present invention. Referring to FIG. 3, the timing controller 200 includes a normal mode signal generator 210, a clock generator 220, a dot clock fail detection circuit 230, and an abnormal mode signal generator. 240, and a multiplexer 250. The timing controller 200 may be applied to the timing controller 130 of FIG. 1.

The normal mode signal generator 210 controls the normal image data to be displayed on the LCD panel in response to the input data RGB1, the dot clock signal DCLK, and the control signals DE, VSYNC, and HSYNC. Generates a mode signal. The frequency of the dot clock signal DCLK may be 54 (MHz) to 108 (MHz).

The clock generator 220 generates a predetermined clock signal RCLK. The clock generator 220 may be an RC oscillator, and the frequency of the clock signal RCLK may be 8 (MHz) to 12 (MHz).

The dot clock fail detection circuit 230 outputs the detection signal OFF_DOTS in response to the dot clock signal DCLK and the clock signal RCLK. For example, the high level detection signal OFF_DOTS may indicate that the dot clock signal has failed, and the low level detection signal OFF_DOTS may indicate that the dot clock signal has not failed. . The dot clock fail detection circuit 230 may be reset by the reset signal RSTB directly input to the timing controller 200.

The abnormal mode signal generator 240 is activated when the detection signal OFF_DOTS indicates a fail of the dot clock signal DCLK, and generates an abnormal mode signal for controlling display of stable image data on the LCD panel. . For example, a logic state when the detection signal OFF_DOTS indicates a fail may be at a high level, and output data included in the abnormal mode signal may be black data or white data. It may be stable data.

In response to the detection signal OFF_DOTS, the multiplexer 250 selects one of the normal mode signal and the abnormal mode signal to generate output signals RGB2, S_CNT and G_CNT. Among the output signals, S_CNT is a control signal for driving the source driver of the liquid crystal display, and includes a source clock signal MCLK, a horizontal start signal STH, a line latch signal TP, a selection signal REV, and a liquid crystal polarity. The inversion signal POL, and the output signal G_CNT is a control signal for driving the gate driver of the liquid crystal display, and includes a gate clock signal CPV, a vertical start signal STV, and an output enable signal OE. ). For example, the multiplexer 250 may select the abnormal mode signal in response to the high level detection signal OFF_DOTS, and select the normal mode signal in response to the low level detection signal OFF_DOTS.

Therefore, the timing controller 200 according to the present invention can control the stable image data to be displayed on the LCD panel by selectively outputting the normal mode signal and the abnormal mode signal by using the detection signal which is the output of the dot clock fail detection circuit. .

4 is a circuit diagram illustrating an example of the dot clock fail detection circuit illustrated in FIG. 3 in more detail. Referring to FIG. 4, the dot clock fail detection circuit 230 includes a logic circuit and an OR circuit 236.

The logic circuit generates output signals NOTTS_H and NDOTS_L in response to a dot clock signal DCLK and a predetermined clock signal RCLK. The logic circuit includes an inverter 231, a first flip-flop 232, a second flip-flop 233, a third flip-flop 234, and a fourth flip-flop 235. do. Preferably, the first, second, third, and fourth flip-flops 232, 233, 234, 235 are each D flip-flop.

The first flip-flop 232 latches the clock signal RCLK input to the input terminal D in response to the dot clock signal DCLK input through the clock terminal CK to output the terminal. The first output signal DOTS_H and the inverted signal DOTS_HB of the first output signal DOTS_H are generated through Q and the inverted output terminal / Q.

The second flip-flop 233 inverts the clock signal RCLK input to the input terminal D through the inverter 231 in response to the dot clock signal DCLK input through the clock terminal CK. The signal is latched to generate a second output signal DOTS_L through the output terminal Q.

The first and second flip-flips 232 and 233 may have an inverted signal DOTS_HB and a second inverted signal of the first output signal DOTS_H in response to the reset signal RSTB input through the reset terminal CLR. The output signal DOTS_L is reset to a low level.

The third flip-flop 234 may receive the inverted signal of the first output signal DOTS_HB input to the input terminal D in response to the inverted signal of the clock signal RCLK input through the clock terminal CK. The DOTS_HB is latched to generate a third output signal NOTTS_H through the output terminal Q.

The fourth flip-flop 235 latches the ground voltage VSS input to the input terminal D in response to the clock signal RCLK input through the clock terminal CK to output the output terminal ( The fourth output signal NDOTS_L is generated through Q). In addition, the fourth flip-flop 235 may set the fourth output signal NOTTS_L to a high level in response to an inverted signal of the second output signal DOTS_L input through the synchronous set terminal CSN. Set to.

The OR circuit 236 performs an OR on the output signals NDOTS_H and NDOTS_L of the logic circuit to generate a detection signal OFF_DOTS.

Therefore, the dot clock fail detection circuit 200 according to the present invention may detect a fail of the dot clock DCLK when the dot clock signal DCLK is abnormally input to the timing controller 200.

FIG. 5 is a timing diagram illustrating an operation of the dot clock fail detection circuit illustrated in FIG. 4 when the dot clock signal is normally input.

Referring to FIG. 5, the first output signal DOTS_H latches the clock signal RCLK at the rising edge of the dot clock signal DCLK to transition to a high level or a low level. At the same time, the first output signal DOTS_H is inverted and converted into an inverted signal DOTS_HB of the first output signal DOTS_H. In a similar manner, the second output signal DOTS_L also latches the inverted signal of the clock signal RCLK at the rising edge of the dot clock signal DCLK and transitions to the high level or the low level.

Next, the third output signal NOTTS_H latches the inverted signal DOTS_HB of the first output signal DOTS_H at the falling edge of the clock signal RCLK to maintain the low level. The fourth output signal NOTTS_L is set to a high level when the second output signal DOTS_L is at a low level at the rising edge of the clock signal RCLK, and thus is maintained at the low level instead of being set to the high level.

Next, the detection signal OFF_DOTS maintains a low level by ORing the third and fourth output signals NOTTS_H and NDOTS_L. Therefore, when the dot clock signal DCLK is normally input, the logic state of the detection signal OFF_DOTS is at a low level.

FIG. 6 is a timing diagram illustrating an operation of the dot clock fail detection circuit illustrated in FIG. 4 when a fail occurs due to a low level of a dot clock signal in a high level period of a clock signal.

Referring to FIG. 6, the first output signal DOTS_H latches the clock signal RCLK at the rising edge of the dot clock signal DCLK and transitions to a high level. At the same time, the first output signal DOTS_H is inverted and converted into an inverted signal DOTS_HB of the first output signal DOTS_H. In a similar manner, the second output signal DOTS_L also latches the inverted signal of the clock signal RCLK at the rising edge of the dot clock signal DCLK and transitions to the low level.

Next, the third output signal NOTTS_H latches the inverted signal DOTS_HB of the first output signal DOTS_H at the falling edge of the clock signal RCLK to maintain the low level. The fourth output signal NOTTS_L is set at a high level when the second output signal DOTS_L is at a low level at the rising edge of the clock signal RCLK.

Next, the detection signal OFF_DOTS transitions to a high level by ORing the third and fourth output signals NOTTS_H and NDOTS_L. Therefore, when the dot clock signal DCLK is abnormally input, the logic state of the detection signal OFF_DOTS is at a high level.

FIG. 7 is a timing diagram illustrating an operation of the dot clock fail detection circuit illustrated in FIG. 4 when a fail occurs due to a low level of a dot clock signal in a high level period of a clock signal.

Referring to FIG. 7, the first output signal DOTS_H latches the clock signal RCLK at the rising edge of the dot clock signal DCLK and transitions to the low level. At the same time, the first output signal DOTS_H is inverted and converted into an inverted signal DOTS_HB of the first output signal DOTS_H. In a similar manner, the second output signal DOTS_L also latches the inverted signal of the clock signal RCLK at the rising edge of the dot clock signal DCLK to transition to a high level.

Next, the third output signal NOTTS_H latches the inverted signal DOTS_HB of the first output signal DOTS_H at the falling edge of the clock signal RCLK and transitions to the high level. The fourth output signal NOTTS_L is set to a high level when the second output signal DOTS_L is at a low level at the rising edge of the clock signal RCLK, and thus is maintained at the low level instead of being set to the high level.

Next, the detection signal OFF_DOTS transitions to a high level by ORing the third and fourth output signals NOTTS_H and NDOTS_L. Therefore, when the dot clock signal DCLK is abnormally input, the logic state of the detection signal OFF_DOTS is at a high level.

6 and 7 illustrate a case in which the dot clock signal DCLK is failed to a low level, but the dot clock signal DCLK is at a low level even when the dot clock signal DCLK is failed to a high level. A timing diagram similar to the case of failing may be shown.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Herein, specific terms have been used, but they are used only for the purpose of illustrating the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

The dot clock fail detection circuit according to the present invention can detect the failure of the dot clock when the dot clock signal is abnormally input to the timing controller.

In addition, the timing controller according to the present invention can control the stable image data to be displayed on the LCD panel by selectively outputting the normal mode signal and the abnormal mode signal using the detection signal which is the output of the dot clock fail detection circuit.

In addition, the liquid crystal display according to the present invention may display a stable screen by including the timing controller.

The detailed description of each drawing is provided in order to provide a thorough understanding of the drawings cited in the detailed description of the invention.

1 is a block diagram schematically illustrating a conventional liquid crystal display.

2 is a timing diagram illustrating an example of failing dot clock signals.

3 is a block diagram illustrating a timing controller according to an embodiment of the present invention.

4 is a circuit diagram illustrating an example of the dot clock fail detection circuit illustrated in FIG. 3 in more detail.

FIG. 5 is a timing diagram illustrating an operation of the dot clock fail detection circuit illustrated in FIG. 4 when the dot clock signal is normally input.

FIG. 6 is a timing diagram illustrating an operation of the dot clock fail detection circuit illustrated in FIG. 4 when a fail occurs due to a low level of a dot clock signal in a high level period of a clock signal.

FIG. 7 is a timing diagram illustrating an operation of the dot clock fail detection circuit illustrated in FIG. 4 when a fail occurs due to a low level of a dot clock signal in a high level period of a clock signal.

<Description of Symbols for Main Parts of Drawings>

200: timing controller 210: normal mode signal generator

220: clock generator 230: dot clock fail detection circuit

240: abnormal mode signal generator 250: multiplexer

Claims (11)

In a dot clock fail detection circuit for detecting a dot clock signal inputted to a timing controller of a liquid crystal display device and generating a detection signal, A logic circuit for generating output signals in response to the dot clock signal and a predetermined clock signal; And And an OR circuit for ORing the output signals to generate the detection signal. The method of claim 1, And the clock signal is generated from a clock generator included in the timing controller. The method of claim 2, Wherein the clock generator comprises an RC oscillator. 4. The logic circuit of claim 3 wherein the logic circuit is A first flip-flop in response to the dot clock signal, latching the clock signal to generate an inverted signal of a first output signal; A second flip-flop in response to the dot clock signal, latching an inverted signal of the clock signal to generate a second output signal; A third flip-flop, in response to the inversion signal of the clock signal, latching the inversion signal of the first output signal to generate a third output signal as one of the output signals; And Latching a ground voltage in response to the clock signal to generate a fourth output signal as one of the output signals, and outputting the fourth output in response to an inverted signal of the second output signal input through a synchronous set terminal; And a fourth flip-flop for setting the signal to a high level. The method of claim 4, wherein And the first, second, third and fourth flip-flops are each D flip-flop. In a timing controller of a liquid crystal display device comprising an LCD panel for displaying image data, A normal mode signal generator configured to generate a normal mode signal for controlling normal image data to be displayed on the LCD panel when a dot clock signal is normally input; A dot clock fail detection circuit configured to generate a detection signal by detecting whether the dot clock signal is failed using a predetermined clock signal; An abnormal mode signal generator configured to be activated when the detection signal indicates a fail of the dot clock signal to generate an abnormal mode signal for controlling stable image data to be displayed on the LCD panel; And And a multiplexer for selecting and outputting one of the normal mode signal and the abnormal mode signal in response to the detection signal. The method of claim 6, And the clock signal is generated from a clock generator included in the timing controller. The method of claim 7, wherein And the clock generator comprises an RC oscillator. A liquid crystal display device comprising an LCD panel for displaying image data, comprising: It detects whether or not the inputted dot clock signal fails using a predetermined clock signal, outputs a normal mode signal if it is detected that it is not a fail according to the detection result, and abnormal mode signal if it detects a fail according to the detection result. A timing controller that outputs the timing controller; And A driving circuit for driving the LCD panel in response to the normal mode signal or the abnormal mode signal, And the normal mode signal controls to display normal image data on the LCD panel, and the abnormal mode signal controls to display stable image data on the LCD panel. The method of claim 9, And the clock signal is generated from a clock generator included in the timing controller. The method of claim 10, And the clock generator comprises an RC oscillator.