KR20050071203A - Method of driving plasma display panel - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel to prevent bright spot mis-discharge.

The initialization period of the driving method of the plasma display panel of the present invention is a stabilization period for setting the wall charge position of the discharge cells so that the surface discharge type discharge occurs in all discharge cells during the set-up period, and the surface discharge type in the discharge cells A setup period for generating wall charges in the discharge cell by causing the discharge of the battery and a set down period for erasing some of the wall charges generated during the setup period are included.

Description

Driving Method of Plasma Display Panel {Method of Driving Plasma Display Panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a plasma display panel, and more particularly, to a method of driving a plasma display panel to prevent bright spot mis-discharge.

Plasma Display Panels (hereinafter referred to as "PDPs") are characterized by emitting phosphors by 147 nm ultraviolet rays generated during discharge of an inert mixed gas such as He + Xe, Ne + Xe or He + Xe + Ne. An image containing graphics is displayed. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a scan electrode Y and a sustain electrode Z formed on the upper substrate 10, and an address electrode formed on the lower substrate 18. X). Each of the scan electrode Y and the sustain electrode Z has a line width smaller than the line widths of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z and is formed at one edge of the transparent electrode 13Y, 13Z).

The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode Y and the sustain electrode Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode X is formed in the direction crossing the scan electrode Y and the sustain electrode Z. The partition wall 24 is formed in parallel with the address electrode X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert mixed gas is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into an initialization period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gray levels according to the number of discharges.

Here, the initialization period is divided into a setup period in which the rising ramp waveform is supplied and a set down period in which the falling lamp waveform is supplied. For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 2, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period is increased at a rate of 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. .

3 shows driving waveforms of a PDP supplied to two subfields.

Referring to FIG. 3, the PDP is driven by being divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period, the rising ramp waveform Ramp-up is applied to all the scan electrodes Y simultaneously. This rising ramp waveform (Ramp-up) causes a slight discharge in the cells of the full screen to generate wall charges in the cells. During the set down period, after the rising ramp waveform Ramp-up is supplied, the falling ramp waveform Ramp-down falling at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan electrodes Y. It is applied at the same time. Ramp-down generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by setup discharges, and uniformly distributing the wall charges required for address discharges in the cells of the full screen. Will remain.

In the address period, a negative scan pulse scan is sequentially applied to the scan electrodes Y and a positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. Wall charges are generated in the cells selected by the address discharge.

On the other hand, the positive electrode DC voltage of the sustain voltage level Vs is supplied to the sustain electrodes Z during the set down period and the address period.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. Then, the cell selected by the address discharge is sustained in the form of surface discharge between the scan electrode Y and the sustain electrode Z each time the sustain pulse sus is applied while the wall voltage and the sustain pulse sus in the cell are added. Discharge occurs. Finally, after the sustain discharge is completed, an erase ramp waveform (erase) having a small pulse width is supplied to the sustain electrode Z to erase wall charges in the cell.

Here, the discharge generation principle of the sustain period and the wall charge initialization principle of the initialization period will be described in detail using a hexagonal voltage curve as shown in FIG. 4. Here, the Vt close curve is used as a method for measuring the discharge generation principle and the voltage margin of the PDP.

In FIG. 4, the hexagonal region inside the voltage curve is a region in which the cell voltage inside the discharge cell is shifted, and no discharge occurs when the cell voltage is located in the hexagonal inner region (ie, when the cell voltage is located in the hexagonal outer region). And (Y) indicates the direction in which the cell voltage moves when a negative voltage is applied to the scan electrode (Y). Similarly, each of Y (+), X (+), X (-), Z (+), and Z (-) is a negative electrode or a positive electrode for the scan electrode Y, the address electrode X, and the sustain electrode Z. It indicates the direction in which the cell voltage moves when the voltage of the castle is applied.

The Vtxy displayed in the first quadrant opposite discharge region of the voltage curve graph represents a voltage at which discharge starts between the address electrode X and the scan electrode Y when a voltage is applied to the address electrode X. FIG. Therefore, the straight line representing the first quadrant opposite discharge region of the voltage curve graph is set to a length equal to the voltage at which the discharge between the address electrode X and the scan electrode Y is started. Vtzy, which is displayed in the quadrant surface discharge region of the voltage curve graph, indicates a voltage at which discharge starts between the sustain electrode Z and the scan electrode Y when a voltage is applied to the sustain electrode Z. FIG. Similarly, Vtxz, Vtzx, Vtyz, and Vtyx each represent a discharge start voltage between the electrodes. On the other hand, the voltages of Vtxy, Vtzy, Vtxz, Vtzx, Vtyz, and Vtyx vary slightly from panel to panel (by cell size and process deviation), and accordingly, the shape of the voltage curve varies slightly.

Referring to the operation of the sustain period, the wall charges in the discharge cells in which the address discharge is generated are located in the third quadrant of the graph as shown in FIG. Subsequently, when the positive sustain pulse is applied to the scan electrode Y as shown in FIG. 3, the voltage values of the wall charges positioned in the third quadrant and the voltage values of the positive sustain pulse are added to the cell voltage. It moves by passing through the surface discharge area located in (that is, moving to the Y (+) side). In this case, sustain discharge is generated between the scan electrode Y and the sustain electrode Z in the discharge cells.

After the sustain discharge is generated, the wall charges are located in the first quadrant of the graph as shown in FIG. Here, since the sustain discharge is generated strongly, the wall charges are located in the first quadrant of the graph spaced apart by approximately the sustain voltage Vs in the center region of the voltage curve. Subsequently, when the positive sustain pulse is applied to the sustain electrode Z, the voltage values of the wall charges positioned in the first quadrant and the voltage values of the positive sustain pulse are added together, so that the cell voltage is located in the first quadrant of the graph as shown in FIG. 6. It is moved via the discharge area (i.e., moved to the Z (+) side). At this time, sustain discharge is generated between the sustain electrode Z and the scan electrode Y in the discharge cells.

On the other hand, after the sustain discharge is generated, the wall charges are located in the third quadrant of the graph as shown in FIG. Here, since the sustain discharge is strongly generated, the wall charges are located slightly lower, that is, in the third quadrant of the graph, at a distance separated by the sustain voltage (Vs) from the center region of the voltage curve to the -X axis. In fact, in the sustain period, the sustain discharge is generated by repeating the processes as shown in FIGS. 5 and 6 a predetermined number of times.

After the sustain discharge is completed, the wall charges are positioned in the first quadrant of the graph as shown in FIG. 7 (that is, the last sustain pulse is applied to the scan electrode Y). After the sustain discharge, the erase ramp waveform (erase) is applied to the sustain electrodes Z. ) Is supplied. When the erase lamp waveform (erase) is supplied to the sustain electrode (Z), the cell voltage is moved via the surface discharge region of the first quadrant of the graph (that is, moved to the Z (+) side) as shown in FIG. Here, a weak discharge (i.e., a ramp waveform) is generated in the cell, and the cell voltage is moved through the quadrant surface discharge area of the graph. Then, the wall charges are moved to the position of A1 by moving at a slope of 1/2.

That is, after the erase discharge is completed, the wall charges are moved to the position of A1 as shown in FIG. 8. Then, the wall charges of the cells in which the sustain discharge has not occurred in the sustain period (that is, the cells in which the address discharge has not occurred in the previous subfield) maintain the position of A2 in FIG. 8 (that is, the address discharge has not occurred). The wall charges of the cells maintain the position of A2 from the initialization period of the previous subfills to the initialization period of the next subfield).

Thereafter, the rising ramp waveform Ramp-up is supplied to the scan electrodes Y. When the rising ramp waveform Ramp-up is supplied to the scan electrodes Y, the cell voltages of the discharge cells that are discharged in the sustain period of the previous subfield are passed through the surface discharge region of three quadrants from A1 (i.e., Move to +) side to move. Here, when the cell voltage passes through the surface discharge region of the three quadrants of the graph (weak weak discharge due to the lamp pulse), the wall charges move at a slope of 1/2. Thus, the wall charges located at the point of A1 are moved to the position of A3 (the time at which the cell voltage is moved to point C). The cell voltage is lowered to point C of the graph because it must be located in the voltage curve. Here, when the cell voltage is located at the vertex of the third quadrant (ie, point C), the wall charges move with a slope of one. Thus, the wall charges located at the point of A3 are moved to the point B with a slope of one.

On the other hand, when the rising ramp waveform Ramp-up is supplied to the scan electrodes Y, the cell voltages of the discharge cells in which the sustain discharge is not generated in the previous subfield are passed through the surface discharge region of the third quadrant from the point of A2 (that is, , Move to the Y (+) side). Here, when the cell voltage passes through the surface discharge region of the third quadrant of the graph (weak weak discharge due to the lamp pulse), the wall charges are moved at a slope of 1/2. Thus, the wall charges located at the point of A2 are moved to the position of A4 (the time at which the cell voltage is moved to point C). The cell voltage is lowered to point C of the graph because it must be located in the voltage curve. Here, when the cell voltage is located at the vertex of the third quadrant (ie, point C), the wall charges move with a slope of one. Thus, the wall charges located at the point of A4 are moved to the point B with a slope of one.

That is, when the rising ramp waveform (Ramp-up) is supplied in the initialization period, the wall charges of all the discharge cells are moved to the point B. Thereafter, a falling ramp waveform Ramp-down falling from the rising ramp waveform Ramp-up is supplied to the scan electrodes Y.

 When the falling ramp waveform Ramp-down is supplied to the scan electrodes Y, the cell voltage located at the point C is moved to the point C1 as shown in FIG. 9. Then, a positive voltage is applied to the sustain electrode Z when the falling ramp waveform Ramp-down falls with a slope. Then, the cell voltage located at the point C1 is moved to the point of C2. Then, since the ramp ramp down continues, the cell voltage is moved from the point of C2 through the surface discharge region of the first quadrant. Here, when the cell voltage passes through the surface discharge region of the first quadrant, the wall charges move at a slope of 1/2. Thus, the wall charges that were located at point B are moved to the position of A2. That is, when the ramp ramp down is supplied in the initialization period, the wall charges located at the point B are moved to the point A2 to initialize the discharge cells.

That is, the conventional PDP initializes the wall charges of the on-cell and the off-cell in which the discharge has not occurred in the previous subfield to the point of A2 during the initialization period. However, in the conventional driving method, there is a problem in that the wall charge of the cell located in the quadrant of the voltage curve cannot be initialized due to the process deviation of the cell or the application of the abnormal voltage.

In detail, the wall charge of the specific discharge cell when the PDP is driven may be located in the quadrant of the voltage curve as shown in FIG. 10. For example, the wall charge of a specific discharge cell may be located at the point C after the sustain period of the previous subfield due to a problem such as abnormal voltage application or process deviation. As such, when the ramp ramp is supplied to the scan electrodes Y while the wall charge of the specific discharge cell is located at the point C, the cell voltage of the specific discharge cell is three quadrants of the voltage curve from the point C. It is moved via the opposite discharge area. Therefore, in a specific discharge cell, there is a problem in that an opposite discharge, that is, a discharge is generated between the address electrode X and the scan electrode Y, causes a false discharge in the form of a bright point. In other words, since the opposite discharge is generated through the phosphor, when the opposite discharge occurs during the initialization period, the panel is displayed in the form of a bright point on the panel. In addition, since the wall charges of the specific discharge cells in which the counter discharge is generated during the initialization period are not initialized in a desired form, false discharge occurs in the specific discharge cells.

Accordingly, it is an object of the present invention to provide a method for driving a plasma display panel which can prevent bright spot mis-discharge.

In order to achieve the above object, the initializing period of the driving method of the plasma display panel of the present invention is a stabilizing period for setting the wall charge position of the discharge cells so that the surface discharge type discharge occurs in all the discharge cells during the set-up period, A setup period for generating wall charges in the discharge cells by causing surface discharge in the cells and a set down period for erasing some wall charges generated during the setup period.

The stabilization period may include applying a first negative anti-discharge pulse to the scan electrodes formed in each discharge cell, and applying a second positive anti-discharge pulse to the sustain electrodes formed in parallel with the scan electrodes in each discharge cell. Applying.

The first false discharge prevention pulse is a ramp pulse falling with a slope.

The second anti-discharge prevention pulse is a pulse of a square wave.

The voltage values of the first anti-discharge prevention pulse and the second anti-discharge prevention pulse are set such that the cell voltages of all the discharge cells are moved through one or four quadrant surface discharge regions of the voltage curve.

The wall charges of all the discharge cells are located in the second or third quadrant of the voltage curve by the discharge generated by the first and second anti-discharge prevention pulses.

Due to the rising ramp waveform applied to the scan electrodes during the set-up period, the cell voltages of all the discharge cells are moved via the surface discharge region of the three quadrants of the voltage curve.

The initialization period of the driving method of the plasma display panel of the present invention is a stabilization period for setting the wall charge position of the discharge cells so that the surface discharge type discharge occurs in all discharge cells during the set-up period, and the surface discharge type in the discharge cells And a set-up period for locating the wall charges within the first quadrant of the voltage curve by causing the discharge to occur, and a set-down period for locating the wall charges located in the first quadrant of the voltage curve to the center of the voltage curve.

The stabilization period may include applying a first negative anti-discharge pulse to the scan electrodes formed in each discharge cell, and applying a second positive anti-discharge pulse to the sustain electrodes formed in parallel with the scan electrodes in each discharge cell. Applying.

The first false discharge prevention pulse is a ramp pulse falling with a slope.

The second anti-discharge prevention pulse is a pulse of a square wave.

The voltage values of the first anti-discharge prevention pulse and the second anti-discharge prevention pulse are set such that the cell voltages of all the discharge cells are moved through the surface discharge region of the first or fourth quadrant of the voltage curve.

The wall charges of all the discharge cells are located in the second or third quadrant of the voltage curve by the discharge generated by the first and second anti-discharge pulses.

During the set-up period, the rising ramp waveform is supplied to the scan electrodes so that the cell voltages of all the discharge cells are moved through the three-quadrant discharge region of the voltage curve to generate the setup discharge, and the wall charges of all the discharge cells are generated by the setup discharge. Are located within one quadrant of the voltage curve.

During the set down period, a falling ramp waveform is applied to the scan electrodes from the base voltage to the negative peak voltage, and a positive DC voltage is applied to the sustain electrodes.

The positive DC voltage is set lower than the sustain voltage of the sustain pulse applied in the sustain period.

The voltage value of the first anti-discharge prevention pulse is set to a negative peak voltage, and the voltage value of the second anti-discharge prevention pulse is set higher than a positive DC voltage.

The voltage value of the second anti-discharge prevention pulse is set higher than the sustain voltage.

The voltage value of the first anti-discharge prevention pulse is set lower than the negative peak voltage, and the voltage value of the second anti-discharge prevention pulse is set equal to the positive DC voltage.

The voltage value of the first anti-discharge prevention pulse is set lower than the negative peak voltage, and the voltage value of the second anti-discharge prevention pulse is set higher than the positive DC voltage.

During the initialization period, scan pulses are sequentially supplied to the scan electrodes from the first negative voltage to the second negative voltage.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 11 to 18.

11 is a waveform diagram illustrating a method of driving a plasma display panel according to a first embodiment of the present invention.

Referring to FIG. 11, the PDP according to the first embodiment of the present invention is driven by being divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

First, the initialization period is a stabilization period for shifting wall charges so that surface discharge-type discharges can occur in all discharge cells, a setup period and setup for forming wall charges in discharge cells by causing surface discharge in all discharge cells. The driving is divided into a set-down period for partially erasing the wall charges formed in the period.

In the stabilization period, the negative first anti-discharge prevention pulse MP1 is applied to the scan electrodes Y and the positive second anti-discharge prevention pulse MP2 is applied to the sustain electrodes Z. The first anti-discharge prevention pulse MP1 and the second anti-discharge prevention pulse MP2 set the position of the wall charge so that surface discharge type discharge can occur in all discharge cells during the subsequent setup period.

The process of changing the position of the wall charges during the stabilization period will be described in detail using the voltage curve. First, the wall charges of the on-cells in which the discharge is generated during the sustain period in the previous subfield are located at the point A1 as shown in FIG. Then, the wall charges of the off-cells in which discharge has not occurred during the sustain period of the previous subfield are located at the point of A2. In addition, the wall charge of the specific discharge cell is located at point C, which is the quadrant of the voltage curve, due to the process deviation and the application of the abnormal voltage.

When the square wave second anti-discharge prevention pulse MP2 is applied to the sustain electrodes Z during the stabilization period, the cell voltages of the on-cells are moved from the point of A1 to the point of F2 (that is, moving to the Z (+) side). Then, the cell voltage moved to the point of F2 passes through the surface discharge region of the first quadrant by the first mis-discharge prevention pulse MP1, which is a ramp waveform falling with the slope applied to the scan electrodes Y (ie, To the Y (-) side). Here, when the cell voltage is moved via the surface discharge region of the first quadrant, the wall charges located at the point of A1 are moved to the point of E2 while moving at an inclination of 1/2.

When the second mis-discharge prevention pulse MP2 of the square wave is applied to the sustain electrodes Z, the cell voltages of the off-cells are moved from the point of A2 to the point of F1 (that is, moving to the Z (+) side). The cell voltage moved to the point F1 passes through the surface discharge region of the first quadrant by the first mis-discharge prevention pulse MP1, which is a ramp waveform falling with the slope applied to the scan electrodes Y. To the Y (-) side). Here, when the cell voltage is moved through the surface discharge region of the first quadrant, the wall charges located at the point of A2 are moved to the point of E1 while moving at an inclination of 1/2.

In addition, when the second mis-discharge prevention pulse MP2 of the square wave is applied to the sustain electrodes Z, the cell voltages of the off-cells are moved from the point of C to the point of F3 (that is, moved to the Z (+) side). The cell voltage moved to the point of F3 is the surface discharge region of one quadrant (or four quadrants) by the first anti-discharge prevention pulse MP1, which is a ramp waveform falling with the slope applied to the scan electrodes Y. Is moved via (i.e., moved to the Y (-) side). Here, when the cell voltage is moved through the surface discharge region of the first quadrant (or the fourth quadrant), the wall charges located at the point of C are moved to the point of E3 while moving in half tilt. That is, the wall charges of all the discharge cells that have passed the stabilization period are located on the left side (two quadrants and three quadrants) of the Y-axis of the voltage curve.

On the other hand, the voltage values of the first anti-discharge prevention pulse MP1 and the second anti-discharge prevention pulse MP2 move through the surface discharge region where the cell voltages of all the discharge cells are located in the first and fourth quadrants of the voltage curve. Is set to be. In practice, voltage values of the first anti-discharge prevention pulse MP1 and the second anti-discharge prevention pulse MP2 are set experimentally in various ways by the resolution, the inch, and the like of the panel.

Thereafter, the rising ramp waveform Ramp-up is supplied to the scan electrodes Y during the setup period. When the rising ramp waveform Ramp-up is supplied, the cell voltages of all the discharge cells are moved through the surface discharge region located in the three quadrants of the voltage curve as shown in FIG. 13. Here, when the cell voltages of all the discharge cells are moved through the surface discharge region of the three quadrants, the wall charges of the on cells converge to the point B shown in FIG. 8 as in the prior art.

That is, in the present invention, it is possible to set the position of the wall charge during the stabilization period so that the surface discharge type setup discharge can occur in all the discharge cells during the setup period, thereby preventing the false discharge in the form of bright spots. In addition, in the present invention, since the wall charge of the specific discharge cell can be initialized to a desired shape, stable discharge can be generated in the specific discharge cell.

In the set-down period, the rising ramp waveform Ramp-up is supplied, and then the falling ramp waveform Ramp-down falling at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up is simultaneously applied to the scan electrodes. . Ramp-down generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by setup discharges, and uniformly distributing the wall charges required for address discharges in the cells of the full screen. Will remain. In fact, the wall charges of all the discharge cells during the set down period converge to the point of A2 as shown in FIG.

In the address period, a negative scan pulse scan is sequentially applied to the scan electrodes Y and a positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. Wall charges are generated in the cells selected by the address discharge.

On the other hand, the positive electrode DC voltage of the sustain voltage level Vs is supplied to the sustain electrodes Z during the set down period and the address period.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. Then, the cell selected by the address discharge is sustained in the form of surface discharge between the scan electrode Y and the sustain electrode Z each time the sustain pulse sus is applied while the wall voltage and the sustain pulse sus in the cell are added. Discharge occurs. Finally, after the sustain discharge is completed, an erase ramp waveform (erase) having a small pulse width is supplied to the sustain electrode Z to erase wall charges in the cell.

Meanwhile, in the present invention, the stabilization period can be applied to various types of driving waveforms. For example, in the application number xx-xxxxxx (described in EPD03-150 application) filed by the applicant of the present application, the wall charges are positioned at the center of the voltage curve during the initialization period. Various driving waveforms have been applied so that the wall charges can be positioned, and for convenience of description, the driving waveforms of the application number xx-xxxxxxx will be described.) Thus, when the wall charges are positioned in the center of the voltage curve, There is a fear that a discharge in the form of a counter discharge is generated during the initialization period. Accordingly, the stabilization period of the present invention is added before the setup period to control the stable surface discharge during the setup period.

14 is a waveform diagram illustrating a method of driving a plasma display panel according to a second embodiment of the present invention.

Referring to FIG. 14, the PDP according to the second embodiment of the present invention is driven by being divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

First, the initialization period is a stabilization period for moving wall charges so that a discharge in a surface discharge form in all discharge cells, a setup period for placing wall charges in a quadrant of the voltage curve by causing surface discharge in all discharge cells, and The wall charges located in the first quadrant are driven in a set down period to move to the center of the voltage curve.

During the stabilization period, the negative first anti-discharge prevention pulse MP1 (lamp wave) is applied to the scan electrodes Y, and the positive second anti-discharge prevention pulse MP2 (square wave) is applied to the sustain electrodes Z. ) Is applied. The first anti-discharge prevention pulse MP1 and the second anti-discharge prevention pulse MP2 set the position of the wall charge so that surface discharge type discharge can occur in all discharge cells during the subsequent setup period.

The process of changing the position of the wall charges during the stabilization period will be described in detail using the voltage curve. First, the wall charge of the on-cells in which the discharge is generated during the sustain period in the previous subfield is located at the point A1 as shown in FIG. 15. Then, the wall charges of the off-cells in which discharge has not occurred during the sustain period of the previous subfield are located at the point D1. (The wall charges of the off-cells are changed from the initialization period of the previous subfield to the initialization period of the next subfield. Keep)

When the second mis-discharge prevention pulse MP2 of the square wave is applied to the sustain electrodes Z during the stabilization period, the cell voltage of the on cells is moved from the point A1 to the point H1 (that is, moving to the Z (+) side). In addition, the cell voltage moved to the point of H1 is passed through the surface discharge region of the first quadrant by the first mis-discharge prevention pulse MP1, which is a ramp waveform falling with the slope applied to the scan electrodes Y. To the Y (-) side). Here, when the cell voltage is moved through the surface discharge region of the first quadrant, the wall charges located at the point of A1 are moved to the point of G1 while moving at an inclination of 1/2.

When the second mis-discharge prevention pulse MP2 of the square wave is applied to the sustain electrodes Z, the cell voltages of the off-cells are moved from the point of D1 to the point of H2 (that is, moved to the Z (+) side). The cell voltage moved to the point of H2 is passed through the surface discharge region of the first quadrant by the first anti-discharge prevention pulse MP1, which is a ramp waveform falling with the slope applied to the scan electrodes Y (ie, To the Y (-) side). Here, when the cell voltage is moved through the surface discharge region of the first quadrant, the wall charges located at the point H2 are moved to the point of G2 while moving at an inclination of 1/2.

In addition, as described in the related art, wall charges of specific discharge cells in which wall charges are positioned in four quadrants of the voltage curve due to process deviation and application of an abnormal voltage are also included in the first and second anti-discharge prevention pulses MP1 and MP2. To the left of the voltage curve Y-axis.

Thereafter, a positive rising ramp waveform Ramp-up is supplied to the scan electrodes Y during the setup period. When the rising ramp waveform Ramp-up is supplied, the cell voltages of all the discharge cells are moved through the surface discharge region located in the three quadrants of the voltage curve as shown in FIG. 16. Here, the voltage value of the rising ramp waveform Ramp-up is set so that the wall charges of all the discharge cells are located in one quadrant of the voltage curve, so the wall charges of all the discharge cells are located in the first quadrant of the voltage curve.

Subsequently, during the set down period, the ramp electrodes are supplied to the scan electrodes Y, which are rapidly lowered to the ground potential GND and gradually lowered from the ground potential GND. During the set down period, a positive DC voltage Vz having a potential lower than the sustain voltage Vs is applied to the sustain electrodes Z. (Applied in the set down period and the address period.) Then, the wall charges of the discharge cells are applied. Converge to the point D1, the center of the curve.

In the address period, a negative scan pulse scan is sequentially applied to the scan electrodes Y, and a positive data pulse data is applied to the address electrodes X. Here, the scan pulse scan is set to fall from the negative third voltage (-V3) to the negative fourth voltage (-V4). That is, since the wall charges converge to the point D1 which is the center of the voltage curve during the set-down period, a scan pulse having a lower potential than the conventional one is applied in order to stably generate the address discharge. On the other hand, wall charges necessary for sustain discharge are formed in the discharge cells supplied with the scan pulse and the data pulse at the same time.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. Then, the cell selected by the address discharge is sustained in the form of surface discharge between the scan electrode Y and the sustain electrode Z each time the sustain pulse sus is applied while the wall voltage and the sustain pulse sus in the cell are added. Discharge occurs. Finally, after the sustain discharge is completed, an erase ramp waveform (erase) having a small pulse width is supplied to the sustain electrode Z to erase wall charges in the cell.

In the second embodiment of the present invention, it is possible to set the position of the wall charge during the stabilization period so that the surface discharge type setup discharge can occur in all the discharge cells during the setup period. You can prevent it. In addition, in the present invention, since the wall charge of the specific discharge cell can be initialized to a desired shape, stable discharge can be generated in the specific discharge cell.

On the other hand, the voltage values of the first anti-discharge prevention pulse MP1 and the second anti-discharge prevention pulse MP2 move through the surface discharge region where the cell voltages of all the discharge cells are located in the first and fourth quadrants of the voltage curve. Is set to be. In practice, the voltage values of the first anti-discharge prevention pulse MP1 and the second anti-discharge prevention pulse MP2 are set experimentally in consideration of the resolution, the inch, and the like of the panel.

For example, the voltage value V1 of the first anti-discharge prevention pulse MP1 is set equal to the voltage value V1 of the falling ramp waveform Ramp-down applied in the set-down period, and prevents the second error discharge. The voltage value of the pulse MP2 may be set higher than the positive DC voltage Vz applied in the setdown period. In fact, when the voltage value V1 of the first anti-discharge prevention pulse MP1 is set equal to the voltage value V1 of the falling ramp waveform Ramp-down, the voltage value of the second anti-discharge prevention pulse MP2. Is set higher than the sustain voltage Vs.

In addition, in the present invention, as shown in FIG. 17, the voltage value of the second mis-discharge prevention pulse MP2 may be set equal to the voltage value of the positive DC voltage Vz applied in the set-down period. At this time, the voltage value (-V3) of the first anti-discharge prevention pulse MP1 is set lower than the voltage value (-V1) of the falling ramp waveform (Ramp-down) to stably set the position of the wall charge.

In the present invention, as shown in Fig. 18, the second mis-discharge prevention pulse MP2 is set higher than the positive DC voltage Vz to which the voltage value is applied during the set-down period and the voltage of the first mis-discharge prevention pulse MP1. The value -V4 may be set lower than the voltage value -V1 of the ramp ramp down. That is, in the present invention, the first mis-discharge prevention pulse MP1 and the second mis-discharge prevention pulse MP2 may be set experimentally in various ways.

As described above, according to the driving method of the plasma display panel according to the present invention, the wall charge is generated so that the discharge in the form of surface discharge occurs in the setup period by applying an anti-discharge prevention pulse to the scan electrodes and the sustain electrodes before the setup period. Control their location. Accordingly, in the present invention, the wall charges of all discharge cells can be initialized to a desired position during the initialization period while preventing the discharge of the bright point.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a diagram showing an example of a luminance weight value of a subfield included in one frame.

3 is a waveform diagram showing driving waveforms applied to electrodes during a period of a subfield;

4 is a diagram showing positions of wall charges in discharge cells in which address discharge has occurred.

5 is a view illustrating a process in which a sustain discharge is generated when a sustain pulse is supplied to the wall charge shown in FIG. 4.

FIG. 6 is a view showing positions of wall charges formed by the sustain discharge of FIG. 5; FIG.

7 is a view showing a process of moving the wall charge by the erase pulse.

FIG. 8 is a view illustrating a process in which wall charges are moved by the rising ramp waveform shown in FIG. 3.

9 is a view showing a process of moving the wall charge by the falling ramp waveform shown in FIG.

10 is a view showing a process in which counter discharge occurs in a specific discharge cell during an initialization period.

Fig. 11 is a waveform diagram showing a driving method of the plasma display panel according to the first embodiment of the present invention.

12 is a view illustrating a process of moving wall charges during the stabilization period shown in FIG.

FIG. 13 is a view showing a process in which a discharge in the form of surface discharge occurs during the setup period shown in FIG.

14 is a waveform diagram showing a driving method of a plasma display panel according to a second embodiment of the present invention;

FIG. 15 is a view illustrating a process of moving wall charges during the stabilization period shown in FIG. 14;

FIG. 16 is a view illustrating a process in which a surface discharge type discharge is generated during a setup period shown in FIG. 14;

Fig. 17 is a waveform diagram showing a driving method of a plasma display panel according to a third embodiment of the present invention.

18 is a waveform diagram showing a driving method of a plasma display panel according to a fourth embodiment of the present invention;

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y, 12Z: transparent electrode

13Y, 13Z: bus electrode 14, 22: dielectric layer

16: protective film 18: lower substrate

24: partition 26: phosphor layer

Claims (21)

A method of driving a plasma display panel in which a plurality of subfields including an initialization period form one frame, The initialization period is A stabilization period for setting the wall charge positions of the discharge cells so that surface discharge type discharge can occur in all discharge cells during the setup period; A setup period for generating wall discharges in the discharge cells to form wall charges in the discharge cells; And a set down period for erasing some of the wall charges generated during the set-up period. The method of claim 1, The stabilization period is Applying a negative first anti-discharge pulse to the scan electrodes formed for each discharge cell; And applying a positive second anti-discharge prevention pulse to the sustain electrodes formed to be parallel to the scan electrodes for each of the discharge cells. The method of claim 2, And the first anti-discharge prevention pulse is a ramp pulse that falls with a slope. The method of claim 2, And said second anti-discharge prevention pulse is a pulse of square wave. The method of claim 2, The voltage values of the first anti-discharge prevention pulse and the second anti-discharge prevention pulse are set such that the cell voltages of all the discharge cells are moved through the surface discharge region of the first or fourth quadrant of the voltage curve. A method of driving a plasma display panel. The method of claim 5, And the wall charges of all the discharge cells due to the discharge generated by the first anti-discharge prevention pulse and the second anti-discharge prevention pulse are located in two or three quadrants of the voltage curve. The method of claim 6, And the cell voltages of all the discharge cells are moved through the surface discharge region of three quadrants of the voltage curve by the rising ramp waveform applied to the scan electrodes during the setup period. A method of driving a plasma display panel in which a plurality of subfields including an initialization period form one frame, The initialization period is A stabilization period for setting the wall charge positions of the discharge cells so that surface discharge type discharge can occur in all discharge cells during the setup period; A setup period for generating surface discharge in the discharge cells to position wall charges within the quadrant of the voltage curve; And a set down period for locating wall charges located in one quadrant of the voltage curve to the center of the voltage curve. The method of claim 8, The stabilization period is Applying a negative first anti-discharge pulse to the scan electrodes formed for each discharge cell; And applying a positive second anti-discharge prevention pulse to the sustain electrodes formed to be parallel to the scan electrodes for each of the discharge cells. The method of claim 9, And the first anti-discharge prevention pulse is a ramp pulse that falls with a slope. The method of claim 9, And said second anti-discharge prevention pulse is a pulse of square wave. The method of claim 9, The voltage values of the first anti-discharge prevention pulse and the second anti-discharge prevention pulse are set such that the cell voltages of all the discharge cells are moved through the surface discharge region of the first or fourth quadrant of the voltage curve. A method of driving a plasma display panel. The method of claim 12, And the wall charges of all the discharge cells due to the discharge generated by the first anti-discharge prevention pulse and the second anti-discharge prevention pulse are located in two or three quadrants of the voltage curve. The method of claim 9, During the setup period, a rising ramp waveform is supplied to the scan electrodes so that the cell voltages of all the discharge cells are moved through the three-quadrant discharge region of the voltage curve to generate a setup discharge. And wall charges of the discharge cells are located in one quadrant of the voltage curve. The method of claim 14, And a falling ramp waveform falling from a base voltage to a negative peak voltage during the set down period, and applying a positive DC voltage to the sustain electrodes. The method of claim 15, And wherein the positive DC voltage is set lower than the sustain voltage of the sustain pulse applied in the sustain period. The method of claim 16, The voltage value of the first anti-discharge prevention pulse is set to the negative peak voltage, and the voltage value of the second anti-discharge prevention pulse is set higher than the positive DC voltage. . The method of claim 17, And the voltage value of the second anti-discharge prevention pulse is set higher than the sustain voltage. The method of claim 16, The voltage value of the first anti-discharge prevention pulse is set lower than the negative peak voltage, and the voltage value of the second anti-discharge prevention pulse is set equal to the positive DC voltage. Driving method. The method of claim 16, The voltage value of the first anti-discharge prevention pulse is set lower than the negative peak voltage, and the voltage value of the second anti-discharge prevention pulse is set higher than the positive DC voltage. Way. The method of claim 8, And a scan pulse sequentially falling from the first negative voltage to the second negative voltage is sequentially supplied to the scan electrodes during the address period following the initialization period.