KR20050068899A - Non-volatile memory device and method for fabricating the same - Google Patents

Abstract

The present invention relates to a nonvolatile memory device and a method of manufacturing the same. In the present invention, a series of irregularities are further formed on the surface of the floating gate pattern, thereby maximizing an effective bonding surface of the floating gate pattern and the control gate pattern. The final device can be induced to maintain the optimum coupling ratio between the floating gate pattern and the control gate pattern while maintaining the minimum size.

Of course, through the additional formation of the unevenness, when the bonding ratio between the floating gate pattern and the control gate pattern is maximized, the final finished device can perform a series of erase operations, program operations, read operations, etc., given to it without any problem. You can do it normally.

Description

Non-volatile memory device and method for manufacturing the same {Non-volatile memory device and method for fabricating the same}

The present invention relates to a non-volatile memory device, and more particularly, to form a series of irregularities on the surface of the floating gate pattern, through which the floating gate pattern and the control gate pattern By maximizing the effective junction, a non-volatile memory device can be induced to ensure that the final finished device maintains the optimum coupling ratio between the floating gate pattern and the control gate pattern while maintaining the minimum size. It is about. The present invention also relates to a method of manufacturing such a nonvolatile memory device.

Recently, as the demand for a nonvolatile memory, for example, a flash memory, which can electrically program or erase data is rapidly increasing, the geometry of each structure constituting the nonvolatile memory also undergoes many structural changes.

As shown in Fig. 1, a nonvolatile memory according to the prior art generally includes a tunnel insulating film 3 formed on an entire surface of a semiconductor substrate 1 in which an active region is defined by an element isolation film 2, and the tunnel insulating film. A floating gate pattern 4 disposed on the upper portion of (3), an ONO pattern (hereinafter, referred to as an "ONO pattern") formed on the floating gate pattern 4 (5); The control gate pattern 6 formed on the upper portion of the ONO pattern 5 is combined. In this case, a source / drain diffusion layer (not shown) is additionally disposed on a part of the semiconductor substrate 1.

Under this conventional regime, the task of increasing the junction ratio between the floating gate pattern 4, the ONO pattern 5 and the control gate pattern 6 is a very important variable in determining the performance of the final nonvolatile memory. Works.

This is because if the bonding ratio between the floating gate pattern 4 and the control gate pattern 6 is lowered, the overall capacitance of the capacitor composed of the combination of the floating gate pattern 4, the ONO pattern 5 and the control gate pattern 6 is reduced. Not only does the capacitance significantly decrease, but also the voltage applied to the control gate pattern 6 is not sufficiently distributed in the floating gate pattern 4, which may cause a problem that the overall driving voltage of the device is greatly increased. Because.

However, even if such a decrease in the bonding rate between the floating gate pattern 4 and the control gate pattern 6 has a great adverse effect on the functioning of the device, to overcome this, the floating gate pattern 4 and the control gate pattern 6 The reality is that it is not possible to find ways to increase the size of the product.

This is because, if the size of the floating gate pattern 4 and the control gate pattern 6 is expanded too large, in the aftermath, the overall size of the device is greatly increased, so that it is not possible to flexibly cope with the recently required miniaturization. This is because a problem may be caused unnecessarily.

As described above, while deeply recognizing that the decrease in the bonding ratio between the floating gate pattern 4 and the control gate pattern 6 greatly affects the normal function of the device, in consideration of the overall size increase problem of the device, No specific countermeasures have been prepared.

Of course, in a situation where the decrease in the junction rate between the floating gate pattern 4 and the control gate pattern 6 persists, if no further action is taken, the final inactive memory element is a series of erase operations given to it, Program operation, read operation, etc. cannot be performed normally.

Accordingly, an object of the present invention is to further form a series of irregularities on the surface of the floating gate pattern, thereby maximizing the effective bonding surface of the floating gate pattern and the control gate pattern, while the final finished device is kept to a minimum size In other words, the bonding rate between the floating gate pattern and the control gate pattern can be maintained in an optimal state.

Another object of the present invention is to further form a series of irregularities on the surface of the floating gate pattern, thereby maximizing the bonding ratio between the floating gate pattern and the control gate pattern, through which the final finished device is given a series of erase operations , Program operation, read operation, etc. can be performed normally.

Still other objects of the present invention will become more apparent from the following detailed description and the accompanying drawings.

In order to achieve the above object, in the present invention, a floating gate formed on a tunnel insulating film formed on an entire surface of a semiconductor substrate in which an active region is defined, and formed on an upper portion of the tunnel insulating film located in the active region, and having at least one unevenness on a portion of the surface thereof. A nonvolatile memory device comprising a combination of a pattern, an ONO pattern (Oxide-Nitride-Oxide pattern) formed while covering the unevenness on the floating gate pattern, and a control gate pattern formed while covering the unevenness on the ONO pattern.

In another aspect of the present invention, there is provided a method of forming a tunnel insulating film on an entire surface of a semiconductor substrate in which an active region is defined, forming a floating gate raw material layer on an upper portion of the tunnel insulating film, and a sacrificial insulating film on an upper portion of the floating gate raw material layer. Forming a pattern, forming a spacer on the sidewalls of the sacrificial insulating film pattern, removing the sacrificial insulating film pattern, and selectively leaving only the spacer on top of the floating gate raw material layer; Selectively etching the layers to form irregularities on the surface of the floating gate raw material layer, forming an ONO raw material layer and a control gate raw material layer on top of the floating gate raw material layer so that the irregularities are covered; The ONO raw material layer and the control gate raw material layer are collectively etched and placed in the active region, It discloses a method of manufacturing the nonvolatile memory device comprising a combination of steps of forming the floating gate pattern, ONO and a control gate pattern takes a pattern sequentially stacked.

Hereinafter, a nonvolatile memory device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 2, a nonvolatile memory device according to the present invention includes a tunnel insulating film 13 formed on the entire surface of a semiconductor substrate 11 in which an active region is defined by an isolation layer 12, for example, a tunnel oxide film; A floating gate pattern 14 made of polysilicon disposed on the tunnel insulating layer 13, an ONO pattern 15 formed on the floating gate pattern 14, and an upper portion of the ONO pattern 15. The formed control gate pattern 16 of the lolly silicon material is combined. In this case, a source / drain diffusion layer is further disposed on a part of the semiconductor substrate 11.

Under this structure, as mentioned above, if the bonding ratio between the floating gate pattern 14 and the control gate pattern 16 is lowered, the floating gate pattern 14, the ONO pattern 15 and the control gate pattern ( Not only does the problem of greatly reducing the overall capacitance of the capacitor formed by the combination of 16), but also the voltage applied to the control gate pattern 16 is not sufficiently distributed to the floating gate pattern 14, the overall drive voltage of the device This greatly high problem can be caused.

In this sensitive situation, as shown in the figure, the present invention takes measures to further arrange a series of irregularities 14a on the surface of the floating gate pattern 14.

Of course, in this case, due to the influence of the unevenness 14a, a series of unevenness 15a can naturally be formed on the surface of the ONO pattern 15 formed on the floating gate pattern 14, The bonding rate between the floating gate pattern 14 and the control gate pattern 16 can be significantly increased.

In the related art, since the floating gate pattern and the control gate pattern are only in contact with each other in a flat state, the floating gate pattern and the control gate pattern may increase the bonding rate of the floating gate pattern and the control gate pattern unless the size of the floating gate pattern and the control gate pattern is increased. There were many limitations to follow.

However, in the case of the present invention, as described above, since the action of additionally forming a series of unevenness 14a on the surface of the floating gate pattern 14 is taken, under the regime of the present invention, the floating gate pattern 14 and the control are The gate pattern 16 can naturally maximize the effective bonding surface of each other without increasing the size of each, and eventually, when the present invention is implemented, the final device is floating, while maintaining the minimum size The junction ratio between the gate pattern 14 and the control gate pattern 16 can be maintained in an optimal state.

Of course, through the additional formation of the unevenness 14a, when the bonding ratio between the floating gate pattern 14 and the control gate pattern 16 is maximized, the final finished device may have a series of erase operations, program operations, The read operation can be performed normally without any problem.

Hereinafter, a method of manufacturing a nonvolatile memory device according to the present invention having the above-described configuration will be described in detail.

As shown in FIG. 3A, in the present invention, a series of Shallow Trench Isolation processes, or LOCal Oxidation of Silicon processes, etc. are selectively performed to selectively form an active region of the semiconductor substrate 11. The device isolation layer 12 is defined.

Subsequently, in the present invention, a series of thermal oxidation processes, chemical vapor deposition processes, and the like are selectively performed to form a tunnel insulating film 13, for example, a tunnel oxide film on the entire surface of the semiconductor substrate 11.

Subsequently, in the present invention, a series of chemical vapor deposition processes are performed to form a series of floating gate raw material layers 14b, for example, a polysilicon layer on the tunnel insulating film 13, and then a series of chemical vapor deposition processes. Is further advanced to form a series of sacrificial insulating film material layers 101a, for example, oxide film layers, on top of the floating gate material layer 14b.

Next, in the present invention, after the series of photoresist patterns 102 are formed on the previous sacrificial insulation material layer 101a, the sacrificial insulation material layers 101a are partially removed using the photoresist pattern 102 as a mask. As a result, as shown in FIG. 3B, a sacrificial insulating film pattern 101 exposing a part of the floating gate raw material layer 14b is formed. Thereafter, the former photoresist pattern 102 is removed from the top of the sacrificial insulation pattern 101.

Subsequently, in the present invention, a series of chemical vapor deposition processes are performed, and as shown in FIG. 3C, the spacer raw material layer 103a, for example, is disposed on the floating gate raw material layer 14b including the sacrificial insulating film pattern 101. After the nitride layer is formed to a thickness of preferably 300 to 1000 GPa, the spacer raw material layer 103a is etched through a series of etch-back processes, for example, reactive ion etching, as shown in FIG. 3D. The spacer 103 having a rounded profile is formed on the sidewall of the sacrificial insulating layer pattern 101.

Next, in the present invention, a series of etching processes, preferably, a wet etching process using an HF solution is performed, and as shown in FIG. 3E, the entire amount of the sacrificial insulating film pattern 101 is removed to thereby remove the floating gate material layer. Only the front spacer 103 is selectively left on top of the 14b.

In this situation, in the present invention, a series of etching processes are performed using the spacer 103 as an etching mask, and the floating gate raw material layer 14b is shaved downward, thereby through the floating gate raw material as shown in FIG. 3F. A series of uneven | corrugated 14a is formed in the surface of the layer 14b. Of course, in this case, the spacer 103 serving as an etching mask of the floating gate raw material layer 14b is naturally removed from the upper portion of the floating gate raw material layer 14b due to the influence of the etching procedure.

Through the above procedure, when the unevenness 14a is formed on the floating gate raw material layer 14b, the present invention proceeds a series of chemical vapor deposition processes sequentially, as shown in Figure 3g, floating gate The ONO raw material layer 15b is further formed on the raw material layer 14b. In this case, the ONO raw material layer 15b can naturally retain a series of unevenness 15a on its surface due to the influence of the unevenness 14a provided in the floating gate raw material layer 14b.

Subsequently, in the present invention, a series of chemical vapor deposition processes are performed to form a series of control gate raw material layers 16a, for example, a polysilicon layer on the ONO raw material layer 15b, and then a series of photolithography processes are performed. By collectively etching the floating gate raw material layer 14b, the ONO raw material layer 15b, and the control gate raw material layer 16a therethrough, as shown in FIG. 3H, a series of sequential stacked structures are taken while being located in the active region. The floating gate pattern 14, the ONO pattern 15, and the control gate pattern 16 are formed.

Of course, in this case, due to the influence of the unevenness 14a, 15a formed on the surface of the floating gate pattern 14 and on the surface of the ONO pattern 15, the floating gate pattern 14 and the control gate pattern 16 are respectively It is possible to naturally maximize the effective joint surface between each other without increasing the size.

Subsequently, in the present invention, a series of impurity ion implantation processes are performed to form a series of source / drain diffusion layers on a part of the semiconductor substrate 11, and a series of manufacturing procedures are completed.

Such a nonvolatile memory device according to the present invention may be variously modified according to circumstances.

For example, as shown in FIG. 4, under another embodiment of the present invention, the floating gate pattern 14 constituting the nonvolatile memory device further includes another unevenness, thereby providing a plurality of, for example, two unevennesses. 14a may be provided. Of course, in this case, due to the increase in the unevenness 14a, the floating gate pattern 14 and the control gate pattern 16 can maximize the effective bonding surface between each other, compared to the previous embodiment.

Hereinafter, a method of manufacturing a nonvolatile memory device according to another exemplary embodiment of the present invention described above will be described in detail.

First, as shown in FIG. 5A, in the present invention, a series of thermal oxidation processes, chemical vapor deposition processes, and the like are selectively performed on the semiconductor substrate 11 having the device isolation film 12 to target the semiconductor substrate 11. A tunnel insulating film 13, for example, a tunnel oxide film, is formed on the entire surface of the?

Subsequently, in the present invention, a series of chemical vapor deposition processes are performed to form a series of floating gate raw material layers 14b, for example, a polysilicon layer on the tunnel insulating film 13, and then a series of chemical vapor deposition processes. Is further advanced to form a series of sacrificial insulating film material layers 104a, for example, an oxide film layer, on top of this floating gate material layer 14b.

Next, in the present invention, after forming a series of photoresist patterns on the above-described sacrificial insulation material layer 104a, the sacrificial insulation material layer 104a is partially removed by using the photoresist pattern as a mask, as shown in FIG. 5B. As described above, the sacrificial insulating film pattern 104 exposing a part of the floating gate raw material layer 14b is formed. Thereafter, the previous photoresist pattern is removed from the top of the sacrificial insulation pattern 104.

Subsequently, in the present invention, a series of chemical vapor deposition processes are performed, and as shown in FIG. 5C, the spacer raw material layer 105a, for example, is disposed on the floating gate raw material layer 14b including the sacrificial insulating film pattern 104. After forming the nitride layer to a thickness of preferably 300 kPa to 1000 kPa, the spacer raw material layer 105 is etched through a series of etch-back processes, for example, reactive ion etching, as shown in FIG. 5D. A pair of spacers 105 having rounded profiles are formed on both sidewalls of the sacrificial insulating layer pattern 104.

Next, in the present invention, a series of etching processes, preferably, a wet etching process using an HF solution is performed, and as shown in FIG. 5E, the entire sacrificial insulating film pattern 104 is removed to thereby remove the floating gate material layer. Only the front spacer 105 is selectively left on top of the 14b.

In this situation, in the present invention, a series of etching processes are performed using the spacer 105 as an etching mask, and the floating gate raw material layer 14b is shaved downward, thereby, as shown in FIG. 5F, the floating gate raw material. A pair of uneven | corrugated 14a is formed in the surface of the layer 14b. Of course, in this case, the pair of spacers 105 serving as an etching mask of the floating gate raw material layer 14b are naturally removed from the upper portion of the floating gate raw material layer 14b due to the influence of the etching procedure.

Through the foregoing procedure, when the unevenness 14a is formed on the floating gate raw material layer 14b, a series of chemical vapor deposition processes are sequentially performed in the present invention, as shown in FIG. 5G, the floating gate. The ONO raw material layer 15b is further formed on the raw material layer 14b. In this case, the ONO raw material layer 15b can naturally retain a series of unevenness 15a on its surface due to the influence of the unevenness 14a provided in the floating gate raw material layer 14b.

Subsequently, in the present invention, a series of chemical vapor deposition processes are performed to form a series of control gate raw material layers 16a, for example, a polysilicon layer on the ONO raw material layer 15b, and then a series of photolithography processes are performed. By collectively etching the floating gate raw material layer 14b, the ONO raw material layer 15b, and the control gate raw material layer 16a, a series of sequential stacked structures are taken while being located in the active region, as shown in FIG. 5H. The floating gate pattern 14, the ONO pattern 15, and the control gate pattern 16 are formed.

Of course, in this case, due to the influence of the two unevennesses 14a and 15a formed on the surface of the floating gate pattern 14 and the surface of the ONO pattern 15, the floating gate pattern 14 and the control gate pattern 16 are respectively It is possible to naturally maximize the effective joint surface between each other without increasing the size of.

Subsequently, in the present invention, a series of impurity ion implantation processes are performed to form a series of source / drain diffusion layers on a part of the semiconductor substrate 11, and a series of manufacturing procedures are completed.

As described above in detail, in the present invention, a series of unevenness is further formed on the surface of the floating gate pattern, thereby maximizing the effective bonding surface of the floating gate pattern and the control gate pattern, whereby the final finished device has a minimum size. While maintaining, the bonding ratio between the floating gate pattern and the control gate pattern can be maintained to be optimal.

Of course, through the additional formation of the unevenness, when the bonding ratio between the floating gate pattern and the control gate pattern is maximized, the final finished device can perform a series of erase operations, program operations, read operations, etc., given to it without any problem. You can do it normally.

While specific embodiments of the invention have been described and illustrated above, it will be apparent that the invention may be embodied in various modifications by those skilled in the art.

Such modified embodiments should not be understood individually from the technical spirit or point of view of the present invention and such modified embodiments should fall within the scope of the appended claims of the present invention.

1 illustrates an exemplary nonvolatile memory device according to the prior art.

2 is an exemplary diagram illustrating a nonvolatile memory device according to the present invention.

3A to 3H are flowcharts sequentially illustrating a method of manufacturing a nonvolatile memory device according to the present invention.

4 is an exemplary diagram illustrating a nonvolatile memory device according to another embodiment of the present invention.

5A through 5H are flowcharts sequentially illustrating a method of manufacturing a nonvolatile memory device according to another exemplary embodiment of the present invention.

Claims (7)

A tunnel insulating film formed on the entire surface of the semiconductor substrate in which the active region is defined; A floating gate pattern formed on an upper portion of the tunnel insulating layer positioned in the active region and having at least one unevenness on a portion of a surface thereof; An ONO pattern (Oxide-Nitride-Oxide pattern) formed while covering the unevenness on the floating gate pattern; And a control gate pattern formed on the ONO pattern to cover the irregularities. Forming a tunnel insulating film on the entire surface of the semiconductor substrate in which the active region is defined; Forming a floating gate material layer on the tunnel insulating film; Forming a sacrificial insulating film pattern on the floating gate material layer; Forming a spacer on sidewalls of the sacrificial insulating pattern; Selectively removing only the spacers on the floating gate material layer by removing the sacrificial insulating layer pattern; Selectively etching the floating gate raw material layer using the spacers as a mask to form irregularities on a surface of the floating gate raw material layer; Forming an ONO raw material layer and a control gate raw material layer on the floating gate raw material layer to cover the unevenness; Collectively etching the floating gate material layer, the ONO material layer, and the control gate material layer to form a floating gate pattern, an ONO pattern, and a control gate pattern positioned in the active region and taking a series of sequential stacked structures. A method of manufacturing a nonvolatile memory device, characterized in that. The method of claim 2, wherein the forming of the spacers comprises: forming a spacer raw material layer on the sacrificial insulating layer pattern; And etching back the spacer raw material layer to leave a rounded spacer on a side of the sacrificial insulating layer pattern. 4. The method of claim 3, wherein the spacer raw material layer is formed of a nitride layer. The method of manufacturing a nonvolatile memory device according to claim 3, wherein the spacer raw material layer is formed to a thickness of 300 mW to 1000 mW. The method of claim 2, wherein the sacrificial insulating layer pattern is formed of an oxide layer. The method of claim 2, wherein the sacrificial insulating layer pattern is removed by a wet etching method using an HF solution.