KR20050068199A - Liquid crystal display device and method for manufacturing using the same - Google Patents

Abstract

The present invention discloses a liquid crystal display device and a method of manufacturing the same, which can improve crosstalk defects by reducing resistance by using a common bus line around a liquid crystal injection hole of a liquid crystal display device as a double wiring structure. The disclosed invention has a dual wiring structure in which a common bus line disposed on one edge region of a substrate for liquid crystal injection and an auxiliary wiring arranged to overlap an upper portion of the common bus line are electrically contacted. .

Here, the double wiring disposed in the liquid crystal injection hole of the substrate is formed by overlapping the auxiliary wiring with the common bus line and the insulating layer interposed on the substrate, and the common bus line and the auxiliary wiring of the liquid crystal injection hole region of the array substrate. The line width is narrowly formed to prevent contamination, and the auxiliary line and the common bus line are electrically contacted at both edge regions of the auxiliary line by an ITO connecting metal.

Description

Liquid crystal display and its manufacturing method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR MANUFACTURING USING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method of manufacturing the same. More specifically, cross talk defects can be improved by reducing resistance by using a common wiring line around a liquid crystal injection hole of a liquid crystal display device as a double wiring structure. The present invention relates to a liquid crystal display device and a manufacturing method thereof.

Recently, due to the rapid development of technology in the semiconductor industry, liquid crystal display devices are being manufactured with smaller and lighter weight and more powerful products. Cathode ray tube (CRT), which is widely used in information display devices, has many advantages in terms of performance and price, but has many disadvantages in terms of miniaturization or portability.

On the other hand, liquid crystal displays have been attracting attention as an alternative means of overcoming the shortcomings of CRTs because they have advantages such as miniaturization, light weight, and low power consumption. Currently, almost all information processing devices that require display devices are required. The situation is attached to.

The liquid crystal display device described above has a structure in which an array substrate for forming a TFT element and a pixel electrode and a color filter substrate having red, green, and blue color filter layers are formed with a liquid crystal layer interposed therebetween.

When the two substrates are bonded together as described above, a liquid crystal panel is manufactured, an electric field is generated on the pixel electrode by applying a driving signal and a data signal to the liquid crystal panel region, and the liquid crystal molecules are twisted by the generated electric field to proceed from the backlight. The transmittance of light is controlled.

The light whose transmittance is adjusted will display an image while traveling through the color filter layer of the color filter substrate.

1 is a plan view illustrating an array substrate of a liquid crystal display according to the related art.

As illustrated in FIG. 1, in the array substrate 10, a plurality of gate bus lines and data bus lines are vertically intersected to define a unit pixel area, and pixel electrodes for generating an electric field are disposed on the unit pixel area. have.

The region in which the pixel electrodes are arranged is a display region 15 for displaying an image. A gate pad for transmitting a signal to the display region 15 and a data pad are formed in an edge region of the array substrate 10.

In addition, a plurality of gate bus lines and data bus lines are connected to the gate pad and the data pad in a seal margin area 10b between the gate pad and the data pad 10a and the display area 15.

A common bus line is formed around the display area 15 and the pad area 10a to apply a common voltage to the common electrode disposed on the upper substrate.

On the common bus line 21 formed at the edge corner region of the array substrate 10, a silver contact portion 20 for electrical connection with the common electrode of the upper substrate is formed.

Ag is doped in the silver contact portion 20 to be electrically connected to the common electrode of the upper substrate.

The common bus line 21 is formed on a glass substrate because it is formed during a gate bus line forming process. When a signal is applied to the gate bus line, a common voltage is applied to the common bus line 21 with respect to a gate voltage. Is applied.

FIG. 2A is an enlarged plan view of the liquid crystal injection hole region (region A) of FIG. 1, and FIG. 2B is a cross-sectional view taken along line II ′ of FIG. 2A.

As shown in FIGS. 2A and 2B, the width of the common bus line 21 formed in the liquid crystal injection hole region of the array substrate has a narrower width than that of other common bus lines.

When the width of the common bus line 21 is not reduced, when the array substrate is completed, an upper substrate, which is a color filter substrate, is bonded, and when the liquid crystal is injected through the liquid crystal injection hole region, the upper substrate is formed on the array substrate. There was a problem that contamination occurs in the injection hole region during the liquid crystal injection by the common bus line 21.

Therefore, in order to prevent the problem of contamination in the liquid crystal injection hole region as described above, a portion of the wiring of the common bus line 21 is removed in a pattern.

In the cross-sectional view of the region II ′ of FIG. 2B, a common bus line 21 is formed on the substrate 30, and a gate insulating film 3 is coated on the common bus line 21.

The protective film 5 is coated on the gate insulating film 3, and only the common bus line 21 is formed on the real margin region 10b.

However, there is a problem that the wiring resistance increases by reducing the line width of the common bus line formed in the liquid crystal injection hole region as described above.

As described above, when the wiring resistance of the common bus line rises, signal distortion of the common voltage occurs, and the distorted common voltage causes cross talk defects, resulting in deterioration of image quality.

The present invention provides a liquid crystal display device that can improve crosstalk defects due to signal distortion caused by a reduction in wiring width by forming wiring lines of a common bus line formed in a liquid crystal injection hole region of a liquid crystal display device array substrate. And to provide a method for producing the object.

In order to achieve the above object, the liquid crystal display device according to the present invention,

A common bus line disposed on one edge region of the substrate for liquid crystal injection;

The auxiliary wiring disposed to overlap the upper portion of the common bus line may be electrically contacted to have a double wiring structure.

Here, the double wiring disposed in the liquid crystal injection hole of the substrate is formed by overlapping the auxiliary wiring with the common bus line and the insulating layer interposed on the substrate, and the common bus line and the auxiliary wiring of the liquid crystal injection hole region of the array substrate. The line width is narrowly formed to prevent contamination, and the auxiliary line and the common bus line are electrically contacted at both edge regions of the auxiliary line by an ITO connecting metal.

And a silver contact portion is formed on the auxiliary wiring.

In addition, the liquid crystal display device manufacturing method according to the present invention,

Forming a gate electrode, a gate bus line, and a common bus line on the glass substrate;

A gate insulating film, an amorphous silicon film, and a metal film are sequentially coated and deposited on the substrate on which the gate bus line is formed, and then etched to form auxiliary wiring on the common bus line of the TFT channel layer, the source / drain electrode, and the liquid crystal injection hole region. Forming;

Applying a protective film on the substrate on which the source / drain electrodes and the auxiliary wirings are formed, and then forming contact holes by etching both edge regions of the auxiliary wirings; And

Depositing an ITO metal film on the substrate on which the contact hole is formed, and etching the same to form an ITO connection metal on the pixel electrode and the auxiliary wiring region to contact the common bus line and the auxiliary wiring; do.

And contact holes formed at both edges of the auxiliary line to form a contact hole by etching a gate insulating layer and a protective layer on the common bus line, and forming a contact hole by etching the protective layer on the auxiliary line. Both sides of the edge is characterized in that the contact with the common bus line formed in the lower portion and the ITO connecting metal.

In addition, the common bus line and the auxiliary line formed in the liquid crystal injection hole region may have a narrow line width.

According to the present invention, by forming the wiring of the common bus line formed in the liquid crystal injection hole region of the liquid crystal display array substrate as the double wiring, it is possible to improve the crosstalk defect due to the signal distortion caused by the reduction in the wiring width.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view showing a liquid crystal display array substrate according to the present invention.

As shown in FIG. 3, an array substrate includes a display area in which a plurality of gate bus lines and data bus lines are vertically intersected to define a unit pixel area, and pixel electrodes for generating an electric field are formed on the unit pixel area. Gate pads and data pads are formed in the pad area 100a for applying a driving signal and a data signal to the gate bus line and the data bus line outside the display area 115.

A plurality of gate bus lines, data bus lines, and common bus lines 121 are formed between the gate pad and the data pad and the display area 115.

The common bus line 121 is formed along the periphery of the display area 115 and is formed on the glass substrate together with the gate bus line.

In addition, a plurality of gate bus lines and data bus lines are connected to the gate pad and the data pad between the gate pad and the data pad and the display area 115.

On the common bus line 121 formed at the edge edge region of the array substrate 100, a silver contact portion 120 for electrical connection with the common electrode of the upper substrate is formed, and the silver contact portion 120 is formed on the common bus line 121. Ag is doped and electrically connected to the common electrode of the upper substrate.

In the present invention, since the line width of the common bus line 121 is reduced in the liquid crystal injection hole region of the array substrate 100, an auxiliary wiring (200 in FIG. 4) is formed and is common with the auxiliary wiring (200 in FIG. 4). A connection unit 130 connecting the bus line 121 is formed opposite the data pad area and the data pad area.

The auxiliary line is formed to overlap an area where the line width of the common bus line 121 decreases when forming the source / drain electrodes.

Accordingly, the common bus line 121 existing in the liquid crystal injection hole region has a double wiring structure, and the common bus line 121 formed on the glass substrate and the auxiliary wiring formed on the common bus line 121 (FIG. 4). 200 is connected to the connecting portion 130, and the connecting portion 130 is made of ITO metal.

That is, since the auxiliary wiring and the common bus line have a double structure, the line width and thickness are increased, so that the resistance is reduced, so that the crosstalk failure that has occurred in the prior art does not occur.

4A is an enlarged cross-sectional view of the liquid crystal injection hole region (region B) of FIG. 3, and FIG. 4B is a cross-sectional view of K-K ′ of FIG. 4A.

4A and 4B, in the present invention, the auxiliary line 200 is formed to overlap the upper portion of the common bus line 121 formed in the liquid crystal injection hole region of the array substrate.

The auxiliary line 200 is a metal forming a source / drain electrode and overlaps the common bus line 121 with a gate insulating layer and an active layer therebetween.

In the cross-sectional view of the region K-K 'of FIG. 4B, a common bus line 121 is formed on the substrate 300, and a gate insulating layer 150 is coated on the common bus line 121. The active layer 160 is formed on the gate insulating layer 150, and the auxiliary line 200 is formed on the active layer 160.

A protective film 190 is formed on the auxiliary line 200.

 In the region where the width of the wiring line of the common bus line 121 is reduced in the liquid crystal injection hole region, the width of the auxiliary wiring 200 is also reduced. However, since there are two upper and lower wiring lines, the resistance can be prevented from increasing by increasing the line width. Can be.

Therefore, the present invention prevents the distortion of the common voltage by preventing the increase in resistance of the common bus line 121 while preventing the occurrence of contamination occurring in the conventional liquid crystal injection hole.

5 is a plan view showing a double wiring structure according to the present invention.

As shown in FIG. 5, the common bus line 121 and the auxiliary line 200 are connected by the connection unit 130, and the connection unit 130 is made of ITO metal and electrically connected thereto.

Since the auxiliary line 200 overlapping the common bus line 121 is formed to be connected to the Vcom pad along the injection hole, the silver contact part 120 formed on the common bus line 121 is formed. It was formed on the auxiliary line 200.

Since the common bus line 121 is formed on the glass substrate, and the auxiliary line 200 is formed on the active layer, when the contact hole is formed on the passivation layer, the common bus line 121 is formed on the common bus line 121. A contact hole 140 is formed to open the coated gate insulating layer and the passivation layer, and to open the passivation layer on the auxiliary line 200.

In the process of forming the ITO pixel electrode on the region where the contact hole 140 is formed, the common bus line 121 and the auxiliary line 200 are electrically connected using ITO metal.

In the drawing, the common bus line 121 and the auxiliary line 200 are electrically connected to each other in the data pad area, but the common bus line 121 and the auxiliary line 200 in the other area of the data pad area are electrically connected. The connection also has the same structure.

However, since the Vcom pad does not exist in the other region of the data pad, the auxiliary line 200 is electrically connected to the common bus line 121.

6 is a cross-sectional view taken along the line X-X 'of FIG.

As illustrated in FIG. 6, when the gate bus line and the gate electrode are formed on the glass substrate 300, the common bus line 121 is formed along the periphery of the display area.

Therefore, although the common bus line 121 is present on the glass substrate 300 and the gate insulating film 150 is coated on the common bus line 121 in the TFT forming process, it is illustrated based on a four mask process. As described above, the auxiliary line 200 is formed on the common bus line 121 with the gate insulating layer 150 and the active layer 160 interposed therebetween.

This is because the active layer 160 remains under the data bus line and the auxiliary line 200 because the active layer 160 and the source / drain electrodes are formed at the same time in the four mask process.

When the source / drain electrodes are formed, an auxiliary line 200 is formed at an upper portion overlapping with the common bus line 121, so that a gate insulating layer may be formed between the auxiliary line 200 and the common bus line 121. 150, an active layer 160 is present.

When the source / drain electrodes of the TFT are formed, the passivation layer 190 is applied to the entire area of the substrate 300 and a contact hole is formed. The contact hole forming process opens the passivation layer 190 on the drain electrode. In addition, the gate pad and the data pad are opened. At this time, an area where the auxiliary line 200 and the common bus line 121 are connected is opened.

Accordingly, the region to be connected to the auxiliary line 200 is not overlapped with the auxiliary line 200, but the contact layer is formed by etching the passivation layer 190 and the gate insulating layer 150, and in the region of the auxiliary line 200. The protective layer 190 is etched to form contact holes.

After performing the contact hole process as described above, in order to form the pixel electrode, an ITO metal film is deposited and etched on the entire region of the substrate to form the pixel electrode, and the gate pad and data pad regions opened in the contact hole process of the passivation layer. Form an ITO contact pad on.

When forming the pixel electrode as described above, the connection portion 130 made of ITO metal is also formed in the contact hole region formed on the auxiliary line 200 and the common bus line 121 to assist the common bus line 121. The wiring 200 is electrically contacted.

Therefore, in the present invention, in the liquid crystal injection hole region of the array substrate, the structure of the common bus line is a double wiring electrically connected to an auxiliary wiring made of a source / drain electrode metal thereon.

Therefore, although the common bus line line width is reduced to prevent contamination in the liquid crystal injection hole region, the double wiring structure has an advantage of preventing the increase in resistance.

As described in detail above, the present invention forms a common bus line wiring formed in the liquid crystal injection hole region of the liquid crystal display array substrate by double wiring, thereby preventing crosstalk defects due to signal distortion caused by the reduction in wiring width. There is an effect that can be improved.

The present invention is not limited to the above-described embodiments, and various changes can be made by those skilled in the art without departing from the gist of the present invention as claimed in the following claims.

1 is a plan view showing an array substrate of a liquid crystal display according to the prior art.

FIG. 2A is an enlarged plan view of the liquid crystal injection hole region (Area A) of FIG.

FIG. 2B is a sectional view taken along line II ′ of FIG. 2A;

3 is a plan view showing a liquid crystal display array substrate according to the present invention.

4A is an enlarged cross-sectional view of the liquid crystal injection hole region (region B) of FIG. 2.

4B is a cross-sectional view taken along the line K-K 'of FIG. 4A.

5 is a plan view showing a double wiring structure according to the present invention.

FIG. 6 is a sectional view taken along the line X-X 'of FIG. 5; FIG.

* Description of the symbols for the main parts of the drawings

121: common bus line 200: auxiliary wiring

300: glass substrate 150: gate insulating film

190: protective film 130: connection portion

Claims (9)

A common bus line disposed on one edge region of the substrate for liquid crystal injection; And an auxiliary line arranged to overlap the upper portion of the common bus line to be electrically contacted to have a double line structure. The method of claim 1, And the dual wirings disposed in the liquid crystal injection hole of the substrate are formed by overlapping auxiliary wirings with a common bus line and an insulating layer interposed therebetween. According to claim 1, And a line width of the common bus line and the auxiliary line in the liquid crystal injection hole region of the array substrate is narrow to prevent contamination. The method of claim 1, And the auxiliary line and the common bus line are electrically contacted at both edge regions of the auxiliary line by an ITO connecting metal. The method of claim 1, And a silver contact portion is formed on the auxiliary line. Forming a gate electrode, a gate bus line, and a common bus line on the glass substrate; A gate insulating film, an amorphous silicon film, and a metal film are sequentially coated and deposited on the substrate on which the gate bus line is formed, and then etched to form auxiliary wiring on the common bus line of the TFT channel layer, the source / drain electrode, and the liquid crystal injection hole region. Forming; Applying a protective film on the substrate on which the source / drain electrodes and the auxiliary wirings are formed, and then forming contact holes by etching both edge regions of the auxiliary wirings; And Depositing an ITO metal film on the substrate on which the contact hole is formed, and etching the same to form an ITO connection metal on the pixel electrode and the auxiliary wiring region to contact the common bus line and the auxiliary wiring; Liquid crystal display device manufacturing method. The method of claim 6, The contact holes formed at both edges of the auxiliary line may form a contact hole by etching a gate insulating layer and a protective layer on the common bus line, and form a contact hole by etching the protective layer on the auxiliary line. Display device manufacturing method. The method of claim 6, And both edges of the auxiliary line are contacted by a common bus line formed below and the ITO connecting metal. The method of claim 6, The common bus line and the auxiliary line formed in the liquid crystal injection hole region have a narrow line width.