KR20050067556A - Semiconductor device including contact and method for forming the same - Google Patents

Abstract

The present invention is to provide a semiconductor device and a method of manufacturing the same, which are suitable for suppressing the reduction of the refresh and the increase of the electric field of the junction caused by the increase in contact resistance due to high integration, the semiconductor device of the present invention is a semiconductor substrate, A plurality of gate lines formed on the gate buffer oxide layer and the gate buffer oxide layer may be formed on the gate buffer oxide layer formed on the surface of the semiconductor substrate and extending from the sidewalls of the gate line. A silicon epitaxial layer formed on the surface of the semiconductor substrate exposed by the source, a source / drain formed in the semiconductor substrate under the silicon epitaxial layer, and the top and side surfaces of the silicon epitaxial layer while covering the gate line. Embedded polysilicon plugs.

Description

A semiconductor device including a contact and a method of manufacturing the same {SEMICONDUCTOR DEVICE INCLUDING CONTACT AND METHOD FOR FORMING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a semiconductor device including a contact and a method of manufacturing the same.

Higher integration due to the problem that the contact area decreases due to the reduction of design rules in the semiconductor device manufacturing process, resulting in an increase in contact resistance, resulting in a refresh fail due to a lack of current margin. This results in inevitable results in recent semiconductor devices that require lower production costs due to increased net die.

Therefore, in order to lower contact resistance, the impurity concentration of the junction is conventionally increased.

1 is a view briefly illustrating a method for forming a contact of a semiconductor device according to the prior art.

As shown in FIG. 1, after the gate lines stacked in the order of the gate oxide film 12, the gate electrode 13, and the gate hard mask 14 are formed on the semiconductor substrate 11, spacers are disposed on the gate lines. A gate buffer oxide film 15 and a gate side wall nitride film 16 are formed.

Then, after the source / drain 17 is formed on the semiconductor substrate 11 between the gate lines, the interlayer insulating film 18 is deposited on the entire surface.

Subsequently, the interlayer insulating layer 18 is etched using self-aligned contact etching to form the contact hole 19, and then ion dopants are further implanted into the source / drain 17 to reduce contact resistance. 20 is formed.

However, in the case of forming the ion implantation layer 20 to increase the impurity concentration of the junction, such as the source / drain 17, as in the conventional technique described above, the electric field of the source / drain 17 is increased. This results in a further increase in hot carrier degradation and a decrease in refresh, which in turn leads to a decrease in yield, which results in worse production costs.

The present invention has been proposed to solve the above problems of the prior art, and provides a semiconductor device and a method of manufacturing the same suitable for suppressing the decrease in refresh caused by the increase in contact resistance due to the high integration and the increase in the electric field of the junction. have.

The semiconductor device of the present invention for achieving the above object is a semiconductor substrate, a plurality of gate lines formed on the semiconductor substrate, the side portion extending from the sidewall of the gate line by a predetermined length covering the top and sidewalls of the gate line A gate buffer oxide film formed on the surface of the semiconductor substrate, a silicon epitaxial layer formed on the surface of the semiconductor substrate exposed by an extended portion of the gate buffer oxide film, a source formed in the semiconductor substrate under the silicon epitaxial layer / And a polysilicon plug buried between the gate lines covering the drain and the upper and side surfaces of the silicon epitaxial layer, wherein the gate buffer oxide film is an oxide film, an atom formed by a wet oxidation method or a dry oxidation method. Oxide film deposited by layer deposition, low pressure chemical vapor deposition It is characterized in that it is selected from the oxide film deposited by the deposited oxide film or the plasma enhanced chemical vapor deposition method, the width of the extension portion of the gate buffer oxide film is characterized in that the thickness 50 ~ 300Å.

In the method of manufacturing a semiconductor device of the present invention, forming a plurality of gate lines on a semiconductor substrate, sequentially forming a gate buffer oxide film and a gate side wall nitride film on the gate line, and forming the gate side wall nitride film on the gate side wall nitride film. Forming an interlayer insulating film until the gap between the gate lines is sufficiently filled; etching the interlayer insulating film while leaving the gate sidewall nitride film and the gate buffer oxide film in the form of a spacer covering the top and sidewalls of the gate line. Forming a contact hole exposing a surface of the semiconductor substrate, growing a silicon epitaxial layer on the surface of the semiconductor substrate exposed to the bottom of the contact hole, and selectively removing the gate sidewall nitride film to increase the area of the contact hole And the contact hole having the enlarged area And embedding the polysilicon plug, and after removing the gate sidewall nitride layer, further comprising an ion implantation step for forming a source / drain in the semiconductor substrate under the silicon epitaxial layer. do.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2 is a diagram showing the structure of a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 2, a field oxide film 22 is formed on the semiconductor substrate 21 to separate the devices, and the gate oxide film 23, the gate electrode 24, and the gate hard mask are disposed on the semiconductor substrate 21. A plurality of gate lines stacked in the order of 25 are arranged at predetermined intervals.

In addition, a gate buffer oxide layer 26 is formed to cover the sidewalls and the upper portion of the gate line, and the gate buffer oxide layer 26 has an extension portion 26a extending from the sidewall of the gate line by a predetermined length to the surface of the semiconductor substrate 21. Is formed on the phase. Here, the width | variety of the extension part 26a is 50 micrometers-300 micrometers in thickness.

The silicon epitaxial layer 30 is grown on the surface of the semiconductor substrate 21 exposed by the extension portion 26a of the gate buffer oxide film 26, and the silicon epitaxial layer is formed on the silicon epitaxial layer 30. A polysilicon plug 32a is formed that covers the upper portion of the upper portion 30 as well as the side surface of the silicon epitaxial layer 30.

A source / drain 31 is formed in the semiconductor substrate 21 under the silicon epitaxial layer 30.

According to FIG. 2, the silicon epitaxial layer 30 and the polysilicon plug 32a are embedded in the contact hole 29 between the gate lines, and the polysilicon plug 32a is formed of the silicon epitaxial layer 30. The area of the contact hole 29 is increased by covering the top and side surfaces.

The increase in the area of the contact hole 29 will be described later, but it is possible by removing the gate side wall nitride film formed on the sidewall of the gate buffer oxide film 26 to form the polysilicon plug 32a.

3A through 3H are cross-sectional views illustrating a method of manufacturing the semiconductor device illustrated in FIG. 2.

As shown in FIG. 3A, after forming the field oxide film 22 for isolation between devices on the semiconductor substrate 21, the gate oxide film 23, the gate electrode 24, and the gate hard on the semiconductor substrate 21 are formed. The gate lines stacked in the order of the mask 25 are formed. Here, the gate hard mask 25 uses a silicon nitride film (Si ₃ N ₄ ).

In order to remove the etch damage of the surface of the semiconductor substrate 21 generated during the etching process for forming the gate line, dry or wet oxidation is performed to oxidize the surface of the semiconductor substrate, or thermal Used hydrogen bake (H ₂ bake), hydrogen plasma (H ₂ plasma) treatment can proceed.

As shown in FIG. 3B, a gate buffer oxide 26 and a gate sidewall nitride 27 are sequentially deposited on the semiconductor substrate 21 including the gate lines.

In this case, the gate buffer oxide layer 26 is to alleviate the stress caused when the gate side wall nitride layer 27 is deposited. The gate buffer oxide layer 26 is deposited by an oxide layer or an atomic layer deposition method (ALD) formed by a wet oxidation method or a dry oxidation method. It is selected from an oxide film, an oxide film deposited by Low Pressure Chemical Vapor Deposition (LPCVD), or an oxide film deposited by Plasma Enhanced CVD (PECVD). Do.

The gate side wall nitride film 27 is an etching barrier for forming a subsequent contact, and is deposited to have a thickness of 50 kPa to 300 kPa by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).

Next, the interlayer insulating film 28 is deposited on the gate side wall nitride film 27 until the gate lines are sufficiently filled.

As shown in FIG. 3C, the contact hole 29 exposing the surface of the semiconductor substrate 21 between the gate lines by etching the interlayer insulating layer 28 using a Self Aligned Contact (SAC) process. Form. In this case, the gate buffer oxide layer 26 and the gate side wall nitride layer 27 exposed after the interlayer insulating layer 28 are etched are subjected to a subsequent etching process after the interlayer insulating layer 28 is etched to form etching spacers covering both sidewalls of the gate line. Remains.

As shown in FIG. 3D, a pre-cleaning process is performed using HF solution or BOE (Buffered Oxide Etchant) solution to facilitate the subsequent selective epitaxial growth (SEG) process. Through this pre-cleaning process, the native oxide that is expected to remain on the bottom surface of the contact hole 29 may be removed.

Subjected to a hydrogen bake (H ₂ bake) the process addition charter positive process for removing the natural oxide film in the range of 800 ℃ ~1200 ℃ for 20 seconds, or may be performed a cleaning with HF vapor (Vapor).

Next, by using the selective epitaxial growth, the silicon epitaxial layer 30 protruding upward from the bottom of the contact hole 29 is grown to the gate electrode 24 height, that is, 100 Å to 1000 Å thick. .

At this time, the selective epitaxial growth process for forming the silicon epitaxial layer 30 is selected and used from the following first and second methods.

First, the first method uses DCS (SiH ₂ Cl ₂ ) gas as a silicon source gas and a pH ₃ or AsH ₃ gas as a doping gas at a pressure of 0.1torr to 200torr and a temperature in the range of 700 ° C to 1200 ° C. It is formed of a type conductive silicon epitaxial layer. At this time, HCl gas may be added to maintain selectivity such that the n-type conductive silicon epitaxial layer is grown only on the surface of the semiconductor substrate 21.

Next, the second method uses Si ₂ H ₆ gas as the silicon source gas at a pressure of 10 ⁻⁷ torr to 10 ⁻⁴ torr and a temperature in the range of 500 ° C. to 800 ° C., and PH ₃ or AsH ₃ gas as the doping gas. To form an n-type conductive silicon epitaxial layer. At this time, Cl gas may be added to maintain selectivity such that the n-type conductive silicon epitaxial layer is grown only on the surface of the semiconductor substrate 21.

In the above first and second methods, the reason for using the doping gas is to make the silicon epitaxial layer conductive, and thus doping at the subsequent ion implantation process by doping during the silicon epitaxial 30 growth. Concentration control is easy.

As shown in Fig. 3E, the gate side wall nitride film 27 is selectively removed. At this time, the gate side wall nitride layer 27 is removed through a wet dip, so that the lower gate buffer oxide layer 26 is not wet etched, that is, phosphoric acid (H ₃₎ to maintain wet etching selectivity of the nitride layer and the oxide layer. PO ₄ ) proceed in the Bath using the solution.

The area of the contact hole 29 may be increased by removing the gate side wall nitride layer 27 as described above. That is, the area of the contact hole 29 further increases by the area 27a occupied by the gate side wall nitride film 27.

As a result, the gate buffer oxide layer 26 is formed on the surface of the semiconductor substrate 21 with an extension portion 26a extending from the sidewall of the gate line by a predetermined length while covering the sidewall and the top of the gate line. Here, the width | variety of the extension part 26a is 50 micrometers-300 micrometers in thickness.

As shown in FIG. 3F, after the gate sidewall nitride layer 27 is removed to reduce the contact resistance, an n-type dopant is ion-implanted using a blanket ion implantation method to thereby source / drain 31 into the semiconductor substrate 21. Form. In this case, as the n-type dopant at the time of blanket ion implantation, it is selected from ₃₁ P, ₇₅ As or ₁₂₂ Sb, and the dose amount is in the range of 1 × 10 ¹² ions / cm ^{2 to} 5 × 10 ¹³ ions / cm ² , and ion implantation energy Is 20keV to 200keV. In addition, the tilt angel may be used at 0 ° to 9 ° to evenly perform ion implantation, and the wafer rotation may be divided into two, four, eight, or sixteen times. In addition, blanket ion implantation may use bath type or single type equipment. When using a twist type equipment, the range is 0 ° to 63 ° when using twist, and α, β In the case of using, α and β are used at 0 ° to 5 °.

Since the implantation of the silicon epitaxial layer 30 proceeds at the time of forming the source / drain 31, the contact resistance can be reduced, and the ion implantation is performed in the state where the silicon epitaxial layer 30 is present. The increase in the electric field of the drain 31 is suppressed.

As shown in FIG. 3G, the polysilicon film 32 is deposited on the entire surface including the contact hole 29 having an enlarged area after the gate sidewall nitride film 27 is removed.

As shown in FIG. 3H, the polysilicon film 32 is planarized to form the polysilicon contact plug 32a until the surface of the gate buffer oxide film 26 is exposed. Here, the polysilicon film 32 is planarized by chemical mechanical polishing or etch back, wherein the interlayer insulating film 28 and the gate side wall nitride film 27 are simultaneously removed.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, the polysilicon plug is formed after the area of the contact hole is increased, thereby overcoming the contact resistance limit due to the reduction of the design rule, thereby reducing the contact resistance.

In addition, since ion implantation is performed to reduce contact resistance after selective epitaxial growth, the electric field of the junction is reduced, thereby improving the refresh characteristics and increasing the yield.

1 is a view briefly illustrating a method for forming a contact of a semiconductor device according to the prior art;

2 illustrates a contact structure of a semiconductor device according to an embodiment of the present invention;

3A to 3H are cross-sectional views illustrating a method for forming a contact for the semiconductor device illustrated in FIG. 2.

* Explanation of symbols for the main parts of the drawings

21 semiconductor substrate 22 field oxide film

23: gate oxide film 24: gate electrode

25: gate hard mask 26: gate buffer oxide film

27 gate side wall nitride film 28 interlayer insulating film

29 contact hole 30 silicon epitaxial layer

32a: polysilicon plug

Claims (16)

Semiconductor substrates; A plurality of gate lines formed on the semiconductor substrate; A gate buffer oxide layer covering a sidewall and an upper portion of the gate line and having an extended portion extending from the sidewall of the gate line by a predetermined length on a surface of the semiconductor substrate; A silicon epitaxial layer formed on the surface of the semiconductor substrate exposed by the extension portion of the gate buffer oxide film; A source / drain formed in said semiconductor substrate below said silicon epitaxial layer; and A polysilicon plug embedded between the gate lines covering the top and side surfaces of the silicon epitaxial layer Semiconductor device comprising a. The method of claim 1, And the silicon epitaxial layer is grown to a height of the gate electrode. The method of claim 2, The silicon epitaxial layer is 100 kW to 1000 kW thick. The method of claim 1, The gate buffer oxide film, A semiconductor device, comprising: an oxide film formed by wet oxidation or dry oxidation, an oxide film deposited by atomic layer deposition, an oxide film deposited by low pressure chemical vapor deposition, or an oxide film deposited by plasma enhanced chemical vapor deposition. The method of claim 4, wherein And the width of the extension portion of the gate buffer oxide film is 50 mW to 300 mW. Forming a plurality of gate lines on the semiconductor substrate; Sequentially forming a gate buffer oxide film and a gate sidewall nitride film on the gate line; Forming an interlayer insulating film on the gate side wall nitride film until the gate lines are sufficiently filled with the interlayer insulating film; Forming a contact hole exposing the surface of the semiconductor substrate between the gate lines by etching the interlayer insulating layer while leaving the gate side wall nitride layer and the gate buffer oxide layer in the form of a spacer covering the top and sidewalls of the gate line; Growing a silicon epitaxial layer on the surface of the semiconductor substrate exposed at the bottom of the contact hole; Selectively removing the gate side wall nitride film to increase an area of the contact hole; And Embedding a polysilicon plug in the contact hole having a larger area; Method for manufacturing a semiconductor device comprising a. The method of claim 6, After removing the gate side wall nitride film, And implanting an ion implantation step to form a source / drain in the semiconductor substrate under the silicon epitaxial layer. The method of claim 7, wherein The ion implantation step, A method for manufacturing a semiconductor device, comprising using blanket ion implantation. The method of claim 8, In the blanket ion implantation, the dopant is selected from ₃₁ P, ₇₅ As or ₁₂₂ Sb, the dose is in the range of 1 × 10 ¹² ions / cm ^{2 to} 5 × 10 ¹³ ions / cm ² , and the ion implantation energy is 20 keV. The manufacturing method of the semiconductor element characterized by setting it as -200 keV. The method of claim 9, In the blanket ion implantation, the wafer rotation is divided into 2, 4, 8 or 16 cycles while using the tilt angle at 0 ° to 9 ° to evenly proceed ion implantation. . The method of claim 6, The gate buffer oxide film, Method of manufacturing a semiconductor device, characterized in that selected from oxide film formed by wet oxidation or dry oxidation method, oxide film deposited by atomic layer deposition method, oxide film deposited by low pressure chemical vapor deposition method or oxide film deposited by plasma enhanced chemical vapor deposition method. . The method of claim 6, Removing the gate side wall nitride film, The method of manufacturing a semiconductor device, characterized in that it is made through a wet dip, but proceeds in a vessel using a phosphoric acid (H ₃ PO ₄ ) solution. The method of claim 6, The silicon epitaxial layer is, N-type conductive silicon epi by using DCS (SiH ₂ Cl ₂ ) gas as silicon source gas and doping gas as PH ₃ or AsH ₃ gas at pressure of 0.1torr ~ 200torr and temperature ranging from 700 ℃ ~ 1200 ℃ A method of manufacturing a semiconductor device, characterized in that it is formed of a tactile layer. The method of claim 13, When forming the n-type conductive silicon epitaxial layer, HCl gas is added. The method of claim 6, The silicon epitaxial layer is, N-type conductivity type using Si ₂ H ₆ gas as the silicon source gas and PH ₃ or AsH ₃ gas as the doping gas at a pressure of 10 ^-7 torr to 10 ^-4 torr and a temperature in the range of 500 ° C to 800 ° C. A method for manufacturing a semiconductor device, characterized in that it is formed of a silicon epitaxial layer. The method of claim 15, Cl gas is added when the n-type conductive silicon epitaxial layer is formed.