KR100524801B1 - Method of forming contact plug having double doping profile in semiconductor device - Google Patents
Method of forming contact plug having double doping profile in semiconductor device Download PDFInfo
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- KR100524801B1 KR100524801B1 KR10-2002-0060778A KR20020060778A KR100524801B1 KR 100524801 B1 KR100524801 B1 KR 100524801B1 KR 20020060778 A KR20020060778 A KR 20020060778A KR 100524801 B1 KR100524801 B1 KR 100524801B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Abstract
본 발명은 콘택플러그와 접합영역간 접촉저항, 콘택플러그와 스토리지노드 또는 비트라인간 접촉저항을 낮추는데 적합한 반도체 소자의 콘택플러그 형성 방법을 제공하기 위한 것으로, 본 발명은 접합영역이 형성된 반도체 기판 상에 상기 접합영역의 일부분을 노출시키는 개구를 갖는 콘택분리막을 형성하는 단계, 상기 콘택분리막의 개구를 포함한 전면에 도펀트가 주입된 도전막을 증착하는 단계, 상기 도전막의 평탄화를 수행하여 상기 개구 내에 상기 접합영역과 콘택되는 콘택플러그를 형성하는 단계, 제1도펀트를 이온주입하여 상기 콘택플러그의 상층부 표면 아래에 제1이온주입영역을 형성하는 단계, 상기 제1도펀트보다 확산정도가 큰 제2도펀트를 이온주입하여 상기 제1이온주입영역의 아래에 제2이온주입영역을 형성하는 단계, 및 상기 콘택플러그 내에 주입된 도펀트들을 활성화시키는 어닐링 단계를 포함한다.The present invention provides a method for forming a contact plug of a semiconductor device suitable for lowering a contact resistance between a contact plug and a junction region and a contact resistance between the contact plug and a storage node or a bit line. Forming a contact isolation film having an opening exposing a portion of the junction region, depositing a conductive film implanted with a dopant on the entire surface including the opening of the contact isolation film, and planarizing the conductive film so as to planarize the conductive film in the opening; Forming a contact plug to be contacted, ion implanting a first dopant to form a first ion implantation region below a surface of an upper layer of the contact plug, and ion implanting a second dopant having a diffusion degree greater than that of the first dopant Forming a second ion implantation region under the first ion implantation region, and the cone It includes an annealing step for activating the dopants introduced into the plug.
Description
본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체소자의 콘택저항 개선 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for improving contact resistance of a semiconductor device.
DRAM 소자의 셀영역에서 실리콘기판의 접합영역(junction region)과 스토리지노드(storage node), 또는 실리콘기판의 접합영역과 비트라인을 연결하기 위해 사용하는 콘택(contact), 즉 셀콘택(cell contact)의 재질은 대부분 폴리실리콘막이다.In the cell region of a DRAM device, a contact, that is, a cell contact, used to connect a junction region and a storage node of a silicon substrate or a bit line with a junction region of a silicon substrate. The material of is mostly polysilicon film.
이와 같이 폴리실리콘막을 이용한 셀콘택은 전기전도성을 증가시키기 위해 1×1020/cm3 이상의 농도의 n형 도펀트를 도핑한다. 주로 사용되는 n형 도펀트는 인(Phosphorous; P)이다.As such, the cell contact using the polysilicon film is doped with an n-type dopant having a concentration of 1 × 10 20 / cm 3 or more to increase electrical conductivity. Mainly used n-type dopant is Phosphorous (P).
그리고, 셀(Cell)의 저항 성분은 채널저항, 접합영역의 저항, 그리고 접합부의 접촉저항 등이 있고, 이러한 셀의 저항 성분을 낮추기 위해 채널이나 접합영역의 경우 이온주입에너지 또는 도즈를 조절한다.The resistance component of the cell includes a channel resistance, a resistance of the junction region, and a contact resistance of the junction. The ion implantation energy or dose is controlled in the case of the channel or junction region to lower the resistance component of the cell.
특히, 접합부에서의 저항은 그 성분 크기가 크지 않아 콘택물질인 폴리실리콘막내 도펀트의 도핑 농도만을 조절하여 저항을 낮춘다. 때문에 셀 콘택이 작아짐에 따라 접촉부의 저항의 중요성이 증가하고 있다. In particular, the resistance at the junction lowers the resistance by controlling only the doping concentration of the dopant in the polysilicon film as the contact material because the component size is not large. As the cell contact becomes smaller, the importance of the resistance of the contact increases.
접촉부의 저항을 낮추기 위해서는 폴리실리콘막의 농도만으로 스토리지노드와 접촉하는 계면 지역 그리고 접합영역에서의 접촉저항을 낮추는데 한계가 있다. In order to reduce the resistance of the contact portion, there is a limit in reducing the contact resistance in the interface region and the junction region in contact with the storage node only by the concentration of the polysilicon film.
이를 해결하기 위해 선택적 에피택셜 성장법(Selective Epitaxial Growth; SEG)을 이용하여 콘택을 채우는 방법이 제안되었다.In order to solve this problem, a method of filling a contact using a selective epitaxial growth (SEG) method has been proposed.
도 1은 종래기술에 따른 콘택플러그가 형성된 반도체 소자의 단면도이다.1 is a cross-sectional view of a semiconductor device having a contact plug according to the prior art.
도 1을 참조하면, 반도체 기판(11)의 소정 영역에 필드산화막(12)이 형성되고, 반도체 기판(11)상에 게이트산화막(13), 게이트전극(14), 하드마스크(15)의 순서로 적층된 게이트라인을 소정 거리를 두고 복수개 형성된다.Referring to FIG. 1, the field oxide film 12 is formed in a predetermined region of the semiconductor substrate 11, and the gate oxide film 13, the gate electrode 14, and the hard mask 15 are sequentially formed on the semiconductor substrate 11. The plurality of gate lines stacked with each other are formed at a predetermined distance.
그리고, 게이트라인 사이에 노출된 반도체 기판(11)내에 이온주입을 통해 트랜지스터의 소스/드레인과 같은 접합영역(16)이 형성되고, 각 게이트라인의 양측벽에 절연막스페이서(17)가 형성되며, 반도체 기판(11) 상부에 콘택플러그간 절연을 제공하는 콘택분리막(18)이 형성된다.A junction region 16 such as a source / drain of a transistor is formed in the semiconductor substrate 11 exposed between the gate lines, and an insulating film spacer 17 is formed on both sidewalls of each gate line. A contact isolation layer 18 is formed on the semiconductor substrate 11 to provide insulation between contact plugs.
그리고, 콘택분리막(18)이 제공하는 게이트 라인 사이의 개구(opening), 예컨대 콘택홀의 일부분을 선택적에피택셜성장법에 의한 에피택셜실리콘막(19a)이 채우고, 나머지 콘택홀을 저압화학기상증착법(LPCVD)을 이용한 폴리실리콘막(19b)이 채우고 있다.The epitaxial silicon film 19a by the selective epitaxial growth method fills a portion of the opening, for example, the contact hole between the gate lines provided by the contact isolation film 18, and the remaining contact hole is filled with a low pressure chemical vapor deposition method ( The polysilicon film 19b using LPCVD is filled.
이와 같이, 종래기술은 콘택플러그가 에피택셜실리콘막(19a)과 폴리실리콘막(19b)의 이중층으로 이루어진다.As described above, in the prior art, the contact plug is formed of a double layer of the epitaxial silicon film 19a and the polysilicon film 19b.
이와 같은 종래기술에서는 에피택셜 실리콘막(19a)이 정상적으로 접합영역(16)과의 계면에서 성장하기 위해서는 접합영역(16) 계면의 클리닝(cleaning)이 매우 중요하며, 주로 고온의 수소 어닐링을 통해 계면의 산화막을 제거한 후 에피택셜 실리콘막(19a)을 성장시킨다.In such a prior art, in order for the epitaxial silicon film 19a to normally grow at the interface with the junction region 16, cleaning of the interface of the junction region 16 is very important, and mainly through high temperature hydrogen annealing. After the oxide film is removed, the epitaxial silicon film 19a is grown.
그러나, 이러한 클리닝 조건을 이용한다고 하더라도 에피택셜 실리콘막(19a)의 선택적 성장이 어렵다. 즉, 클리닝 공정의 제어가 어렵고 과도 성장에 의한 패싯(facet)이 없는 균일한 에피택셜 실리콘막(19a)의 성장을 이루기가 어렵다.However, even if such cleaning conditions are used, selective growth of the epitaxial silicon film 19a is difficult. That is, it is difficult to control the cleaning process and to achieve the growth of the uniform epitaxial silicon film 19a without the facet due to overgrowth.
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출한 것으로, 콘택플러그와 접합영역간 접촉저항, 콘택플러그와 스토리지노드 또는 비트라인간 접촉저항을 낮추는데 적합한 반도체 소자의 콘택플러그 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems of the prior art, and provides a method for forming a contact plug of a semiconductor device suitable for reducing the contact resistance between the contact plug and the junction region, and the contact resistance between the contact plug and the storage node or the bit line. There is a purpose.
또한, 본 발명의 다른 목적은 콘택플러그 자체의 저항을 낮추는데 적합한 반도체 소자의 콘택플러그 형성 방법을 제공하는데 있다. Another object of the present invention is to provide a method for forming a contact plug of a semiconductor device suitable for lowering the resistance of the contact plug itself.
상기 목적을 달성하기 위한 본 발명의 반도체 소자의 콘택플러그 형성 방법은 접합영역이 형성된 반도체 기판 상에 상기 접합영역의 일부분을 노출시키는 개구를 갖는 콘택분리막을 형성하는 단계, 상기 콘택분리막의 개구를 포함한 전면에 도펀트가 주입된 도전막을 증착하는 단계, 상기 도전막의 평탄화를 수행하여 상기 개구 내에 상기 접합영역과 콘택되는 콘택플러그를 형성하는 단계, 제1도펀트를 이온주입하여 상기 콘택플러그의 상층부 표면 아래에 제1이온주입영역을 형성하는 단계, 상기 제1도펀트보다 확산정도가 큰 제2도펀트를 이온주입하여 상기 제1이온주입영역의 아래에 제2이온주입영역을 형성하는 단계, 및 상기 콘택플러그 내에 주입된 도펀트들을 활성화시키는 어닐링 단계를 포함하는 것을 특징으로 하고, 제1 도펀트는 아세닉(As)이고, 제2 도펀트는 인(P)인 것을 특징으로 한다.A method of forming a contact plug of a semiconductor device according to the present invention for achieving the above object comprises forming a contact isolation film having an opening exposing a portion of the junction area on a semiconductor substrate on which a junction area is formed, including the opening of the contact separation film. Depositing a conductive film implanted with a dopant on the entire surface, and planarizing the conductive film to form a contact plug in contact with the junction region in the opening; Forming a first ion implantation region, ion implanting a second dopant having a greater diffusion degree than the first dopant, and forming a second ion implantation region under the first ion implantation region, and in the contact plug And an annealing step of activating the implanted dopants, wherein the first dopant is acenic (As). And, the characterized in that the second dopant is phosphorus (P).
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자의 콘택플러그 형성 방법을 도시한 공정 단면도이다.2A to 2F are cross-sectional views illustrating a method for forming a contact plug in a semiconductor device according to an embodiment of the present invention.
도 2a에 도시된 바와 같이, 반도체 기판(21)의 소정 영역에 필드산화막(22)을 형성한 후, 반도체 기판(21)상에 게이트산화막(23), 게이트전극(24), 하드마스크(25)의 순서로 적층된 게이트라인을 소정 거리를 두고 복수개 형성한다.As shown in FIG. 2A, after the field oxide film 22 is formed in a predetermined region of the semiconductor substrate 21, the gate oxide film 23, the gate electrode 24, and the hard mask 25 are formed on the semiconductor substrate 21. A plurality of gate lines stacked in order of) are formed at a predetermined distance.
다음에, 게이트라인 사이에 노출된 반도체 기판(21)내에 이온주입을 통해 트랜지스터의 소스/드레인과 같은 접합영역(26)을 형성한 후, 각 게이트라인의 양측벽에 절연막스페이서(27)를 형성한다. 이때, 절연막 스페이서(27)는 산화막 또는 질화막을 게이트라인을 포함한 전면에 증착한 후 에치백(Etchback)하여 형성한다.Next, a junction region 26 such as a source / drain of a transistor is formed through ion implantation in the semiconductor substrate 21 exposed between the gate lines, and then an insulating film spacer 27 is formed on both side walls of each gate line. do. In this case, the insulating film spacer 27 is formed by depositing an oxide film or a nitride film on the entire surface including the gate line and then etching back.
다음에, 절연막 스페이서(27)까지 형성된 반도체 기판(21) 상부에 층간절연막을 증착한 후, 층간절연막을 식각하여 콘택플러그간 절연을 제공하는 콘택분리막(28)을 형성한다.Next, after the interlayer insulating film is deposited on the semiconductor substrate 21 formed up to the insulating film spacer 27, the interlayer insulating film is etched to form a contact isolation film 28 that provides inter-contact plug insulation.
따라서, 콘택분리막(28)은 인접 플러그간 분리 및 절연을 위한 것으로 통상적인 층간절연막(Inter Layer Dielectric; ILD)이고, 예를 들면, BPSG, BSG, TEOS, USG이다.Accordingly, the contact separator 28 is a conventional inter layer dielectric (ILD) for isolation and insulation between adjacent plugs, for example, BPSG, BSG, TEOS, and USG.
다음으로, 콘택분리막(28)이 제공하는 게이트 라인 사이의 개구(opening), 예컨대 콘택홀을 포함한 전면에 저압화학기상증착법(LPCVD)을 이용하여 폴리실리콘막(29)을 증착한다. 이때, 폴리실리콘막(29)을 증착하는 과정중에 도펀트가 주입되며, 도펀트는 인(Phosphorous; P)이 1×1020/cm3∼2×1020/cm3의 수준으로 도핑된다.Next, the polysilicon film 29 is deposited using low pressure chemical vapor deposition (LPCVD) on an entire surface including an opening, for example, a contact hole, provided between the gate lines provided by the contact isolation film 28. In this case, a dopant is implanted during the process of depositing the polysilicon layer 29, and the dopant is doped with phosphorus (P) at a level of 1 × 10 20 / cm 3 to 2 × 10 20 / cm 3 .
도 2b에 도시된 바와 같이, 콘택분리막(28)의 표면이 드러날때까지 폴리실리콘막(29)을 화학적기계적연마를 통해 평탄화하여 폴리실리콘플러그(29a)를 형성한다.As shown in FIG. 2B, the polysilicon film 29 is planarized through chemical mechanical polishing until the surface of the contact isolation film 28 is exposed to form the polysilicon plug 29a.
이때, 폴리실리콘플러그(29a)의 하부는 접합영역(26)에 연결되고, 상부는 후속 스토리지노드나 비트라인 부위에 연결될 것이다.At this time, the lower portion of the polysilicon plug 29a is connected to the junction region 26, and the upper portion thereof is connected to the subsequent storage node or bit line portion.
도 2c에 도시된 바와 같이, 폴리실리콘플러그(29a)의 저항을 낮추기 위해 두번에 걸쳐 이온주입(Implantation; IMP)을 행한다.As shown in FIG. 2C, implantation (IMP) is performed twice in order to lower the resistance of the polysilicon plug 29a.
먼저, 1차 이온주입(1st IMP)은 아세닉(As)을 이온주입한다. 이때, 아세닉의 이온주입은 20KeV∼40KeV의 에너지와 1×1015/cm3∼5×1015/cm3의 도즈로 행하며, 아세닉의 이온주입후 폴리실리콘플러그(29a)의 상층부 표면 아래에 아세닉이온주입층(30)이 형성된다.First, the first ion implantation (1st IMP) ion implantation of the asceic (As). At this time, the ion implantation of the acenic is performed with energy of 20 KeV ~ 40 KeV and a dose of 1 × 10 15 / cm 3 to 5 × 10 15 / cm 3 , and after the ion implantation of the acenic, under the upper surface of the polysilicon plug 29a An ionic ion implantation layer 30 is formed in the.
도 2d에 도시된 바와 같이, 2차 이온주입(2nd IMP)을 행하되, 인(P)을 이온주입한다. 이때, 인(P)의 이온주입 조건은 폴리실리콘플러그(29a)의 깊이에 의해 결정되나 10KeV∼40KeV의 에너지와 2×1015/cm3∼1×1016/cm3의 도즈로 행하며, 인의 이온주입후 아세닉 이온주입층(30) 아래에 인 이온주입층(31)이 형성된다.As shown in FIG. 2D, secondary ion implantation (2nd IMP) is performed, and phosphorus (P) is ion implanted. At this time, the ion implantation conditions of the phosphorus (P) is determined by the depth of the polysilicon plug (29a), but the energy of 10KeV ~ 40KeV and the dose of 2 × 10 15 / cm 3 ~ 1 × 10 16 / cm 3 is carried out, After ion implantation, a phosphorus ion implantation layer 31 is formed under the acenic ion implantation layer 30.
도 2e에 도시된 바와 같이, 폴리실리콘플러그(29a)를 포함한 전면에 제1 층간절연막(32)을 증착 및 평탄화한다.As shown in FIG. 2E, the first interlayer insulating film 32 is deposited and planarized on the entire surface including the polysilicon plug 29a.
후속 열공정으로서 급속어닐링(Rapid Thermal Anneal; RTA)을 수행하여 주입된 도펀트들의 활성화 및 확산을 제어한다. 이때, 급속어닐링은 900℃∼1000℃의 온도에서 이루어진다.Rapid thermal annealing (RTA) is performed as a subsequent thermal process to control the activation and diffusion of the implanted dopants. At this time, rapid annealing is performed at a temperature of 900 ℃ to 1000 ℃.
전술한 급속어닐링시, 폴리실리콘플러그(29a)의 상층부 아래에 형성된 아세닉 이온주입층(30)의 경우는 확산이 크지 않지만 폴리실리콘플러그(29a) 내에 깊이 형성된 인이온주입층(31)은 온도에 민감하게 반응하여 접합영역(26)까지 확산한다. 이는 아세닉(As)은 다른 n형 도펀트들, 특히 인(P)보다 확산이 매우 작기 때문이다.In the above-mentioned rapid annealing, the ion ion implantation layer 30 formed under the upper layer of the polysilicon plug 29a does not have a large diffusion, but the in-ion implantation layer 31 deeply formed in the polysilicon plug 29a has a temperature. Reacts sensitively and diffuses to the junction region 26. This is because ascenic (As) is much smaller in diffusion than other n-type dopants, especially phosphorus (P).
결과적으로, 급속어닐링후 폴리실리콘플러그(29a)의 상층부 계면에는 아세닉활성화층(30a)이 집중되고, 폴리실리콘플러그(29a)의 대부분의 영역은 인활성층(31a)으로 할당된다.As a result, the activating layer 30a is concentrated at the upper interface of the polysilicon plug 29a after rapid annealing, and most of the region of the polysilicon plug 29a is allocated to the inactive layer 31a.
아울러, 인 활성층(31a)은 그 확산이 크기 때문에 접합영역(26)까지 이를수 있는데, 이는 문턱전압의 감소 및 펀치특성에 큰 영향을 주기 때문에 급속어닐링시의 온도 제어가 필요하다.In addition, the phosphorus active layer 31a may reach the junction region 26 because of its large diffusion, which requires a temperature control during rapid annealing because it has a large influence on the reduction of the threshold voltage and the punch characteristics.
이와 같이 급속어닐링후 폴리실리콘플러그(29a)의 상층부 계면에 위치하는 아세닉활성층(30a)은 후속 스토리지노드 또는 비트라인과의 접촉저항을 낮추기 위한 것이고, 인활성층(31a)은 폴리실리콘플러그(29a) 자체의 저항을 낮추면서 접합영역(26)과의 접촉저항을 낮추기 위한 것이다. 특히, 인활성층(31a)내 인(P)이 폴리실리콘플러그(29a)내의 그레인바운더리(grain boundary)를 통해 확산하여 접합영역 계면에서의 저항을 낮춘다.As such, the active layer 30a positioned at the upper interface of the polysilicon plug 29a after rapid annealing is for lowering the contact resistance with subsequent storage nodes or bit lines, and the active layer 31a is made of polysilicon plug 29a. ) Is to lower the contact resistance with the junction region 26 while lowering its own resistance. In particular, phosphorus (P) in the phosphorus active layer 31a diffuses through the grain boundary in the polysilicon plug 29a to lower the resistance at the junction region interface.
한편, 급속어닐링시 웨이퍼 전체의 균일한 분포를 위하여 산소(O2)가 포함되지 않은 분위기에 질소(N2) 가스를 불어넣어 반도체 기판(31)을 회전시킨다.Meanwhile, in the rapid annealing process, the semiconductor substrate 31 is rotated by blowing nitrogen (N 2 ) gas into an atmosphere not containing oxygen (O 2 ) for uniform distribution of the entire wafer.
도 2f에 도시된 바와 같이, 제1 층간절연막(32)을 식각하여 복수개의 폴리실리콘플러그중에서 일측 폴리실리콘플러그(29a)의 상부에 비트라인콘택(33)과 비트라인(34)을 형성한다.As illustrated in FIG. 2F, the first interlayer insulating layer 32 is etched to form bit line contacts 33 and bit lines 34 on one side of the polysilicon plugs 29a.
다음에, 비트라인(34)을 포함한 전면에 제2 층간절연막(35)을 형성한 후, 제2 층간절연막(35)과 제1 층간절연막(32)을 동시에 식각하여 나머지 폴리실리콘플러그(29a)의 상부에 스토리지노드콘택(36)과 스토리지노드(37)를 형성한다.Next, after the second interlayer insulating film 35 is formed on the entire surface including the bit line 34, the second interlayer insulating film 35 and the first interlayer insulating film 32 are simultaneously etched to rest the remaining polysilicon plug 29a. The storage node contact 36 and the storage node 37 are formed on the upper portion of the storage node contact 36.
결국, 폴리실리콘플러그(29a)의 하부층에 인활성층(31a)이 존재하므로 폴리실리콘플러그(29a)와 접합영역(26)간 접촉저항이 낮아지고, 폴리실리콘플러그(29a)의 상부층에 아세닉활성층(30a)이 존재하므로 폴리실리콘플러그(29a)와 스토리지노드콘택(36) 또는 비트라인콘택(33)간 접촉저항이 낮아진다.As a result, since the phosphorus active layer 31a exists in the lower layer of the polysilicon plug 29a, the contact resistance between the polysilicon plug 29a and the junction region 26 is lowered, and the acenic active layer is formed on the upper layer of the polysilicon plug 29a. Since 30a is present, the contact resistance between the polysilicon plug 29a and the storage node contact 36 or the bit line contact 33 is lowered.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명은 콘택플러그의 상부에 연결될 계면의 저항을 낮추고 동시에 접합영역과의 계면의 저항을 낮추므로써 포화전류의 증대를 통해 셀 구동능력을 향상시킬 수 있는 효과가 있다. The present invention as described above has the effect of improving the cell driving ability through the increase of the saturation current by lowering the resistance of the interface to be connected to the top of the contact plug and at the same time the resistance of the interface with the junction region.
도 1은 종래기술에 따른 콘택플러그가 형성된 반도체 소자의 단면도,1 is a cross-sectional view of a semiconductor device having a contact plug according to the prior art;
도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자의 콘택플러그 형성 방법을 도시한 공정 단면도.2A to 2F are cross-sectional views illustrating a method of forming a contact plug in a semiconductor device according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 필드산화막21 semiconductor substrate 22 field oxide film
23 : 게이트산화막 24 : 게이트전극23: gate oxide film 24: gate electrode
25 : 하드마스크 26 : 접합영역25: hard mask 26: junction area
27 : 절연막 스페이서 28 : 콘택분리막27 insulating film spacer 28 contact isolation film
29a : 폴리실리콘플러그 30a : 아세닉 활성층29a: Polysilicon plug 30a: Acetic active layer
31a : 인 활성층31a: phosphorus active layer
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000013402A (en) * | 1998-08-07 | 2000-03-06 | 윤종용 | Fabrication method of memory capacitor |
| KR20010005296A (en) * | 1999-06-30 | 2001-01-15 | 김영환 | Fabricating method for semiconductor device |
| US6246085B1 (en) * | 1997-02-19 | 2001-06-12 | Nec Corporation | Semiconductor device having a through-hole of a two-level structure |
| JP2002198500A (en) * | 2000-12-27 | 2002-07-12 | Mitsubishi Electric Corp | Semiconductor integrated circuit device and manufacturing method therefor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6246085B1 (en) * | 1997-02-19 | 2001-06-12 | Nec Corporation | Semiconductor device having a through-hole of a two-level structure |
| KR20000013402A (en) * | 1998-08-07 | 2000-03-06 | 윤종용 | Fabrication method of memory capacitor |
| KR20010005296A (en) * | 1999-06-30 | 2001-01-15 | 김영환 | Fabricating method for semiconductor device |
| JP2002198500A (en) * | 2000-12-27 | 2002-07-12 | Mitsubishi Electric Corp | Semiconductor integrated circuit device and manufacturing method therefor |
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