KR20050067515A - Semiconductor device for detecting repair state in test mode - Google Patents

Abstract

According to an embodiment of the present invention, a memory device capable of selectively accessing a unit cell and a spare cell in which an error corresponding to an input of a repair address is generated in order to facilitate failure analysis of a semiconductor device that is even a package by performing a repair process using a fuse. According to an aspect of the present invention, there is provided a semiconductor memory device which accesses a unit cell in which an error is found by a spare cell in response to an activated repair signal for data access, wherein the repair address is stored in a repair process. Repair address comparison means for comparing the input addresses for data access and activating and outputting a repair signal; And when the test mode signal is at the first level, buffers the repair signal and outputs the repaired signal as the data access repair signal, and the test mode signal is disabled at the second level regardless of whether the repair signal is activated. It provides a semiconductor memory device having a test control means for outputting the.

Description

A semiconductor device capable of detecting a repair state in a test mode {SEMICONDUCTOR DEVICE FOR DETECTING REPAIR STATE IN TEST MODE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to an efficient test of a semiconductor device capable of repairing an error circuit by blowing a fuse to blow a laser.

If any one of a number of normal cells is defective in the manufacture of a semiconductor memory device, it can not function as a memory and thus is treated as a defective product. However, in spite of defects occurring only in some normal cells in the memory, discarding the entire semiconductor memory device as a defective product is an inefficient processing method in terms of yield.

Therefore, the current yield is improved by replacing the normal cell in which a defect has occurred by using a spare cell previously installed in the memory device.

In the repair operation using a spare cell, a spare low and a spare column are pre-installed in each cell array to replace a defective normal cell in a row / column unit. It proceeds in such a way that the substitution.

In detail, when a wafer is processed and a normal cell having a defect is selected through a test, a program for converting the corresponding address into an address signal of a spare cell is performed in an internal circuit. Therefore, in actual use, when an address signal corresponding to a defective normal cell is input, a spare cell is selected instead.

Among the programming methods described above, the most widely used method is to change the path of an address by burning a fuse with a laser beam, and the wiring broken by laser irradiation is called a fuse.

1 is a block diagram showing a semiconductor memory device according to the prior art.

Referring to FIG. 1, a conventional semiconductor memory device determines whether an input address A <0:21> is a repaired address, and activates and outputs a repair signal htiz in response to the repair address. Preliminary cell block including a comparator 10, a normal cell block 30 including a plurality of normal cells, and a plurality of spare cells for replacing in a repair process when an error occurs in the normal cell block 30. 40 and a data access control unit 20 for controlling whether the normal cell block 30 accesses the data or the spare cell block 40 in response to the repair signal hitz.

The repair address comparison unit 10 is initialized to the initialization signal ba, compares whether the input address A <0:21> is a repair address, and if the repair address is a repair address, activates the repair signal hitz at a low level. Output

Subsequently, the data access control unit 20 controls the overall process of data access. When the repair signal hitz is input in an inactive state, the data access control unit 20 controls the data to be accessed in the normal cell block. If the repair signal hitz is activated and input, an error occurs in the normal cell to be accessed and should be replaced with an evicell. Thus, the spare cell block 40 controls the data to be accessed.

FIG. 2 is a circuit diagram illustrating the repair address comparison unit 10 shown in FIG. 1.

Referring to FIG. 2, the repair address comparison unit 10 receives an initialization signal ba, one side of which is a PMOS transistor MP0 connected to a power supply voltage terminal VDD, and the other side of a node N; One side is connected to a plurality of fuses (f1 ~ f22) connected to the node (N), one side is connected to one side of each fuse, the other side is connected to the ground voltage terminal (VSS), each of the address (A0 ~ A21) It is provided with morph transistors (MN1 ~ MN22) receiving the.

An operation of a memory device according to the related art will be described with reference to FIGS. 1 and 2.

First, the fabricated semiconductor memory device is tested in a wafer state to find a normal cell in which an error is found. If an error is found in the normal cell, the fuses f1 to f22 of the repair address comparison unit 10 are selectively blown so that the spare cell can replace the normal cell in which the error corresponds to the address of the normal cell in which the error occurs. The repair process is performed.

As described above, instead of replacing one unit cell with one spare cell in the repair process, the word line including the normal cell in which an error occurs is replaced with the spare word line. The package process then proceeds.

Subsequently, referring to FIG. 2, the operation of the repair address comparison unit 10 will be described. When the initialization signal ba is input at the low level during the initial operation, the PMOS transistor MP0 is turned on and the node N is at the high level. It is initially set to.

After that, when the MOS transistor turned on by the input address and the blown fuse coincide with each other, the voltage level of the node N is maintained at a high level.

If the MOS transistor and the blown fuse turned on by the input address do not coincide with each other, the node N transitions from the high level to the low level.

If the blown fuse in the repair process is f1, f3, f4, if the input address is 00001101, the node N will maintain a high level, and if another address is input, it will maintain a low level.

When the node N maintains the high level, the input address becomes the repaired address. The node N outputs the repair signal hitz, which is an output signal, at a low level. When the node N transitions to the low level, the input address becomes an address that is not repaired. The repair signal hitz, which is an output signal, is deactivated and outputted to a high level.

Accordingly, one repair address comparison unit 10 compares one address to activate or deactivate the repair signal hitz, and outputs the repair signal. The repair address comparison unit 10 may repair the repair address corresponding to the repair address comparison unit included in the semiconductor memory device. The number will be decided.

As described above, when a small number of normal cells have an error, the repair process is performed so that the spare cells can be replaced and accessed, thereby improving the yield.

However, when testing the package again after the repair process, errors are still often found.

 In this case, a failure analysis is performed on where the error occurred. It is very difficult to know the semiconductor memory device in the state that the repaired address is a problem, or whether there is an error in the spare cell, even if it is already packaged.

The present invention has been proposed to solve the above problems, and in order to facilitate the failure analysis of the semiconductor device, which is even a package through a repair process using a fuse, a unit cell in which an error corresponding to an input of a repair address is generated; An object of the present invention is to provide a memory device capable of selectively accessing a spare cell.

In addition, an object of the present invention is to provide a semiconductor device capable of trimming an internal state by selectively blowing a provided fuse, wherein the semiconductor device can select a state before trimming and a state after trimming in a test mode.

In order to achieve the above object, the present invention provides a semiconductor memory device which accesses a unit cell in which an error is found by replacing a spare cell in response to an activated repair signal for data access, wherein the repair address is stored in a repair process. Repair address comparison means for comparing the input addresses for data access and activating and outputting a repair signal; And when the test mode signal is at the first level, buffers the repair signal and outputs the repaired signal as the data access repair signal, and the test mode signal is disabled at the second level regardless of whether the repair signal is activated. It provides a semiconductor memory device having a test control means for outputting the.

In another aspect, the present invention provides a trimming circuit comprising a plurality of unit trimming circuits for activating and outputting a trimming signal, respectively, by blowing each of the provided fuses; A decoder for decoding the trimming signal and outputting a decoding signal for adjusting a level of a driving voltage; And a voltage control unit outputting a driving voltage whose level is adjusted in response to the decoding signal, wherein the unit trimming circuit comprises: a first MOS transistor connected at one side to a power supply voltage terminal and receiving a control signal as a gate; A voltage trimming fuse having one end connected to the other side of the first MOS transistor; A second MOS transistor configured to receive an initialization signal through a gate and connect the other side of the voltage trimming fuse to a ground voltage terminal; An inverter receiving a test mode signal through a gate; A NAND gate receiving a signal applied to the output of the inverter and the other side of the fuse; And an inverter for inverting and outputting the output of the NAND gate.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. do.

3 is a circuit diagram illustrating a semiconductor memory device according to a first embodiment of the present invention.

Referring to FIG. 3, the memory device according to the present embodiment is stored in the repair process in order to access and replace the unit cell in which the error is found with a spare cell in response to the activated repair signal for data access. When the repair address and the address input for data access are matched and matched, the repair address hitting unit 400 which activates and outputs the repair signal hit, and the repair signal when the test mode signal tm is low level hit) is inverted and output as a data access repair signal hitz. When the test mode signal tm is at a high level, the data access repair signal hitz is deactivated regardless of whether the repair signal hit is activated. It includes a test control unit 100 for outputting.

In addition, the test control unit 100 receives the inverter I2 inverting the test mode signal tm and outputs the repair signal hit and the output of the inverter I2 output from the repair address comparison unit 400. And a NAND gate ND1 for outputting as a data access repair signal hitz.

The repair address comparison unit 400 includes a plurality of fuses f23 to f44 selectively blown during the repair process to store the repair address, and an address A <0: to 21 to be input for data access to each gate. >), A plurality of NMOS transistors (MN23 to MN44) connected between one side of the fuse and the ground power terminal (VDD) and the initialization signal ba through the gate, and the power voltage terminal (VDD). And a PMOS transistor MP1 connecting the other side of the plurality of fuses in common, and outputs a repair signal hit to the node N. FIG.

Hereinafter, an operation of the memory device according to the present embodiment will be described with reference to FIG. 3.

The plurality of fuses provided in the repair address comparison unit 400 are selectively blown in response to an address where an error is found in the repair process.

Subsequently, when the test mode signal tm is input at the low level in the test mode, the repair signal hitz, which is an output signal of the repair address comparison unit 400, is inverted and output as a repair signal hit for data access.

In more detail, when the test mode signal tm is input at a low level, the NAND gate ND1 acts as an inverter.

Therefore, when the repair signal hit is activated at a high level, the repair signal hitz for data access is activated at a low level and output. In addition, when the repair signal hit is inactivated at a low level, the repair signal hitz for data access is inactivated and output at a high level.

When the node N maintains the high level due to the low level initialization signal ba, when the input address A0: 21> matches the blown fuse, the level of the node N becomes high. Will be kept at the level. In this case, the repair signal hit is activated and output.

If the input addresses A0: 21> do not coincide with the blown fuses, the level of the node N becomes low, which is a case where the repair signal hit is inactivated and output.

Herein, the address (A0: 21>) inputted coincides with the blown fuse so that the signal input at the '1' high level among the input addresses (A <0:21>) is the gate of the MOS transistor corresponding to the blown fuse. Means that it is only entered.

In the following, when the test mode signal tm is input at a high level, the data access repair signal hit is always deactivated at a high level regardless of the repair signal hit which is the output signal of the repair address comparison unit 400. Output as status.

Here, inputting the test mode signal tm to a high level and outputting the data access repair signal hit to a high level means that the data is accessed to the normal cell in which an error occurs, not to access the repaired spare cell. Say.

Therefore, when the test mode signal tm is input at a low level, the memory device is driven in a repaired state. When the test mode signal tm is input at a high level, driving the memory device to a state before repairing is performed. it means.

According to the present invention, when a failure analysis is performed in a state where the memory device is packaged, the test mode can be appropriately inputted so that the test can be performed while comparing the conditions before and after the repair, thereby facilitating design failure analysis.

4 is a circuit diagram of a semiconductor memory device constructed differently according to the second embodiment of the present invention. In the memory device according to the second exemplary embodiment shown in FIG. 4, the repair address comparison unit 400 has the same configuration, and only the configuration of the test controller 200 has a different configuration.

Referring to FIG. 4, the test control unit 200 inverts and repairs the repair signal hit output from the repair address comparison unit 400, the output of the inverter I3 and the test mode signal ( NOR gate NOR1 receiving tm and an inverter I4 for inverting the output of NOR gate NOR1 and outputting the repair signal hitz for data access are provided.

Since the overall operation of the semiconductor memory device according to the second embodiment is the same as that of the semiconductor memory device according to the first embodiment, a detailed description thereof will be omitted.

In the foregoing description, a circuit for detecting a repair address has been described as an example. However, the present invention can be applied to a semiconductor device capable of changing an internal operating state by selectively blowing a provided fuse.

5 and 6 show an example of applying the idea of the present invention to a trimming circuit for adjusting the voltage level.

Referring to FIG. 5, the voltage trimming circuit for adjusting the voltage includes a plurality of unit trimming circuits 331, 332,..., Activating and outputting the trimming signals trim1 to trimN, respectively, by blowing blown fuses. A trimming unit 330 provided therein, a decoder 340 for outputting a decoding signal dec for decoding the trimming signals trim1 to trimN and adjusting a voltage level of the power supply voltage VDD, and a decoding signal dec. In response to the voltage control unit 350 for outputting a power supply voltage (VDD) is adjusted. In addition, the voltage trimming circuit includes an initial setting unit 310 for initializing the trimming unit 330 and a trimming control unit 320 for controlling trimming.

FIG. 6 is a circuit diagram illustrating a trimming circuit shown in FIG. 5.

Referring to FIG. 6, the unit trimmer 331 is connected to the power supply voltage terminal VDD on one side of the unit trimmer 331, and is provided on the other side of the MOS transistor MP3 and the MOS transistor MNt that receive the control signal cmo as a gate. A voltage transistor fuse (ft) connected to one end connected to the first gate and an initialization signal (fp) to the gate, and a MOS transistor (MNt) connecting the other side of the voltage trimming fuse (ft) to the ground voltage terminal (VSS); Inverter I5 receiving the test mode signal tm2 through the gate, NAND gate ND2 and the NAND gate receiving the signal X applied to the output of the inverter I5 and the other side of the fuse ft An inverter I6 for inverting and outputting the output of ND2 is provided.

FIG. 5 is a circuit for voltage trimming in a semiconductor device. When the trimming signals trim1 to trimN are decoded and output by the decoder 340, the voltage controller 350 outputs the voltage-adjusted power supply voltage VDD. .

After the semiconductor device is manufactured, the desired voltage level is not output due to various variables. The power supply voltage level is adjusted by selectively blowing a fuse included in the wafer level voltage trimming circuit.

In the state in which the test mode signal is input at the low level, the unit trimming unit 331 outputs a low level signal to the NAND gate ND2 when the fuse ft is blown, and at the NAND gate ND2, a high level signal. Is output so that the final trimming signal trim1 is output a deactivation signal that is not trimmed to a low level.

If the fuse ft is not blown, the high level signal is input to the NAND gate ND2, and the output of the NAND gate ND2 is low level, and the final trimming signal trimm is an active signal trimmed to a high level. Is output.

On the other hand, when the test mode signal tm2 is input at the high level, the NAND gate ND2 is always output at the low level, and the final trimming signal trim1 is output at the state where the trimming is not performed at the low level.

According to the present invention, when the test mode tm2 input to each unit trimmer 331 is input at the low level, the trimmed signal is output. When the test mode tm1 is input at the high level, the signal before the voltage trimming is maintained. You can print it out.

Therefore, according to the present invention, it is possible to grasp the state before adjusting the voltage and the state after adjusting the voltage, so that it is easy to analyze the defect in the voltage trimming.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

In the above-described embodiment, the case in which the memory device is maintained by using a fuse or when the internal state of the semiconductor device is changed is described. However, in some cases, the internal state is changed by using an anti-fuse. You can also. Therefore, the idea of the present invention can be applied to a semiconductor memory device equipped with an anti-fuse for a repair process or a semiconductor device for changing an internal state.

According to an embodiment of the present invention, in a semiconductor device that has undergone a repair process using a fuse and is even a package, an access of a spare cell replaced by input of a repair address may be tested, and an unit cell in which an error occurs regardless of input of a repair address Access test can be performed to facilitate defect analysis.

In addition, according to the present invention, in the semiconductor device capable of trimming the internal state by selectively blowing the provided fuse, in the test mode, it is possible to select and operate the state before trimming and the state after trimming, so that the failure analysis Can be facilitated.

Therefore, the present invention can facilitate the failure analysis of the semiconductor device, thereby greatly reducing the test time, thereby reducing the overall development period of the semiconductor device.

1 is a block diagram showing a semiconductor memory device according to the prior art;

FIG. 2 is a circuit diagram showing a repair address comparison unit shown in FIG.

3 is a circuit diagram showing a semiconductor memory device according to the first embodiment of the present invention.

4 is a circuit diagram of another configuration of the semiconductor memory device according to the second embodiment of the present invention.

Fig. 5 is a block diagram showing a semiconductor device according to the third preferred embodiment of the present invention.

FIG. 6 is a circuit diagram showing a trimming circuit shown in FIG.

* Explanation of Signs of Major Parts of Drawings *

MN1 ~ MN22: NMOS Transistor

f1 to f22: fuse

MP0, MP2: Pymotransistor

ND1, ND2: NAND Gate

I1 ~ I7: Inverter

Claims (5)

A semiconductor memory device which accesses by replacing a unit cell in which an error is found with a spare cell in response to an activated repair signal for data access. Repair address comparison means for comparing the repair address stored in the repair process with an address input for data access and activating and outputting a repair signal; And When the test mode signal is at the first level, the repair signal is buffered and output as the repair signal for data access, and at the second level, the test mode signal is deactivated for the data access repair signal regardless of whether the repair signal is activated. Test control means to output A semiconductor memory device having a. The method of claim 1, The test control means An inverter for inverting and outputting the test mode signal; And And a NAND gate configured to receive a repair signal output from the repair address comparison means and an output of the inverter, and output a repair signal for data access. The method of claim 1, A first inverter for inverting and outputting a repair signal output from the repair address comparison means; A nor gate receiving the output of the inverter and the test mode signal; And And a second inverter for inverting the output of the NOR gate and outputting the repair signal for data access. The method of claim 1, The repair address comparison means A plurality of fuses for selectively blowing in the repair process to store the repair address; A plurality of first MOS transistors, each of which receives an address input for data access through each gate and is connected between one side of the fuse and a ground power terminal; And A semiconductor memory device comprising: receiving a initialization signal through a gate; and having a second MOS transistor for connecting a power supply voltage terminal and the other side of the plurality of fuses in common, and outputting the repair signal to a common other end of the fuse. . A trimming circuit having a plurality of unit trimming circuits for activating and outputting trimming signals, respectively, by blowing of each of the provided fuses; A decoder for decoding the trimming signal and outputting a decoding signal for adjusting a level of a driving voltage; And A voltage control unit outputting a driving voltage whose level is adjusted in response to the decoding signal; The unit trimming circuit A first MOS transistor having one side connected to a power supply voltage terminal and receiving a control signal as a gate; A voltage trimming fuse having one end connected to the other side of the first MOS transistor; A second MOS transistor configured to receive an initialization signal through a gate and connect the other side of the voltage trimming fuse to a ground voltage terminal; An inverter receiving a test mode signal through a gate; A NAND gate receiving a signal applied to the output of the inverter and the other side of the fuse; And an inverter for inverting and outputting the output of the NAND gate.