KR100818100B1 - Repair fuse circuit and repair fuse test method - Google Patents

Abstract

A repair fuse circuit and a repair fuse test method are provided to check a failure due to a fuse in advance by stopping latch operation during initial test. A precharge part(10) precharges a node connected to a number of fuses in common when a word line is disabled. A fuse decoding part(20) performs fuse decoding with a number of decoded row addresses when the word line is enabled and then provides the result to the common node. A latch part(30) outputs a fuse decoding signal determining one of a repair path and a normal path through the common node, and latches the determined one. A test part(40,50) disables latch operation of the latch part in order to remedy failure due to the fuses in a test mode.

Description

Repair fuse circuit and repair fuse test method {REPAIR FUSE CIRCUIT AND REPAIR FUSE TEST METHOD}

1 is a circuit diagram showing a repair fuse circuit according to the prior art.

2 is a circuit diagram illustrating a repair fuse circuit according to an exemplary embodiment of the present invention.

3 is a waveform diagram of a fuse decoding signal NRDB appearing in a normal mode and a test mode as the resistances of the fuses F0 to F17 of FIG. 2 increase.

The present invention relates to a repair fuse circuit and a method of testing a repair fuse that selects a repair word line for repairing a defective cell in a semiconductor memory device.

In general, when any one of a large number of memory cells constituting a semiconductor memory device fails, the memory cannot perform its function. Therefore, when a failure occurs in a memory cell, a redundancy method of increasing yield by replacing a defective cell by using a preliminary memory cell installed in the memory in advance is widely used.

In such a redundancy method, a repair for memory cell defect repair of a word line enable path typically uses a repair fuse circuit of a dynamic method as shown in FIG. 1.

That is, the general dynamic repair fuse circuit includes a PMOS transistor P0 connected between a power supply voltage VDD node and a common node COMM and receiving a precharge signal WLCB as a gate, as shown in FIG. 1, A plurality of fuses F0 through F17 connected between the common node COMM and each of the NMOS transistors N0 through N17, and between the fuses F0 through F17 and the ground voltage VSS node, decoded a row address. A number of signals BAX1 <0: 1>, BAX2 <0: 1>, BAX34 <0: 3>, BAX56 <0: 3>, BAX78 <0: 3>, and BAX9 <0: 1> are input to each gate NMOS transistors N0 to N17, an inverter IV0 that inverts the signal of the common node COMM and outputs it to the fuse decoding signal NRDB, and is connected between the power supply voltage VDD node and the common node COMM and is a fuse decoding signal. The PMOS transistor P1 may receive an NRDB as a gate. In this case, the precharge signal WLCB is a signal that is enabled when the word line is inactivated and is disabled when the word line is activated.

The repair fuse circuit having such a configuration precharges the common node COMM to a high level state as the precharge signal WLCB becomes enabled until a command for accessing the memory chip is received. Therefore, the fuse decoding signal NRDB goes low, the normal path is blocked, and the repair path is opened.

On the other hand, when the bank is active, the precharge signal WLCB is disabled and the signals decoded the lower dress BAX1 <0: 1>, BAX2 <0: 1>, BAX34 <0: 3>, BAX56 <0: 3> , BAX78 <0: 3>, or BAX9 <0: 1> is enabled and the common node COMM descends to the low level. Therefore, the fuse decoding signal NRDB goes to a high level so that the repair pass is blocked and the normal pass is opened.

That is, the repair fuse circuit of FIG. 1 determines that the repair fuse is a repair until the word line is activated, and determines that the bank is activated and is a normal operation in the decoding process for the word line activation.

However, when the resistance of the plurality of fuses F0 to F17 increases in a specific situation and the fuse decoding signal NRDB is delayed, a repair word line may be enabled by incorrectly selecting a repair pass instead of the normal pass.

In addition, whether such an error occurs in a fuse error is found only when the resistance of the plurality of fuses F0 to F17 is increased through burn-in. That is, such an error is not found in the initial test of the wafer, which increases the manufacturing time and cost.

Accordingly, an object of the present invention is to check in advance whether the fuse is a failure by stopping the latch operation during the initial test when a failure occurs.

In addition, another object of the present invention is to reduce the gate length of a transistor performing a latch operation connected to a common node to reduce the resistance of the latch transistor to detect in advance the possibility that the operation of the transistor connected to the fuse may be defective. .

According to an aspect of the present invention, a repair fuse circuit includes: a precharge unit configured to precharge a node to which a plurality of fuses are commonly connected when a word line is in an inactive state; A fuse decoding unit configured to fuse-decode the plurality of decoded row addresses to the common node when the word line is in an active state; A latch unit configured to output a fuse decoding signal for determining one of a repair pass and a normal pass through the common node and to latch the same; And a test unit for disabling the latch operation of the latch unit in order to remedy defects caused by the plurality of fuses in the test mode.

The latch unit may include inverting means for inverting a signal of the common node and outputting the inverted signal as the fuse decoding signal; First pull-up means for pulling up the common node to a power supply voltage level by the fuse decoding signal; And switching means for connecting between the first pull-up means and the common node by an output signal of the test unit.

In the latch unit, the first pull-up means preferably includes a first PMOS transistor which is turned on by the fuse decoding signal and supplies the power supply voltage to the switching means, wherein the switching means is an output of the test unit. And a second PMOS transistor which is turned on by a signal and connects between the first pull-up means and the common node.

The test unit receives a test signal enabled in the test mode and a precharge signal enabled when the word line is inactivated, and the latch unit when both the test signal and the precharge signal are enabled. It is preferable to output a signal of the first logic level to disable, and to output a signal of the second logic level to enable the latch unit when at least one of the test signal and the precharge signal is in a disabled state.

The test unit includes a first inverter for inverting the precharge signal; A second inverter for inverting the test signal; And a noah gate for quinoa combining the output signal of the first inverter and the output signal of the second inverter.

In addition, the precharge unit may include second pull-up means for pulling up the common node to a power supply voltage level by a precharge signal enabled when the word line is activated.

In the precharge unit, the second pull-up means preferably includes a third PMOS transistor turned on by the precharge signal to pull up the common node to a power supply voltage level.

The fuse decoding unit may further include: a plurality of pull-down means controlled by the decoded row address signals and connected in parallel between the common node and a ground voltage node; And the plurality of fuses connected between the common node and each pull-down means.

In the fuse decoding unit, each pull-down means may include an NMOS transistor turned on by each decoded low address signal and supplying the ground voltage to each fuse.

According to another aspect of the present invention, a repair fuse circuit includes: a precharge unit configured to precharge a node to which a plurality of fuses are commonly connected when a word line is in an inactive state; A fuse decoding unit configured to fuse-decode the plurality of decoded row addresses to the common node when the word line is in an active state; A latch unit configured to output a fuse decoding signal for determining one of a repair pass and a normal pass through the common node and to latch the same; And a test unit controlling a state of the fuse decoding signal by supplying a driving capability adjustment voltage to the common node in a test mode.

The latch unit may include inverting means for inverting a signal of the common node and outputting the inverted signal as the fuse decoding signal; And first pull-up means for pulling up the common node to a power supply voltage level by the fuse decoding signal.

In the latch unit, the first pull-up means preferably includes a first PMOS transistor that is turned on by the fuse decoding signal and supplies the power supply voltage to the common node.

The test unit may control the fuse decoding signal to select a repair pass by supplying the driving capability adjustment voltage to the common node in the test mode.

The test unit preferably includes second pull-up means for pulling up the common node to a power supply voltage level, which is the driving capability adjustment voltage, by a test signal enabled in a test mode.

In the test unit, the second pull-up means preferably includes a second PMOS transistor turned on by the test signal to pull up the common node to the power supply voltage level.

In addition, the precharge unit may include third pull-up means for pulling up the common node to a power supply voltage level by a precharge signal enabled when the word line is activated.

And wherein, in the precharge unit, the third pull-up means includes a third PMOS transistor turned on by the precharge signal to pull up the common node to a power supply voltage level.

The fuse decoding unit may further include: a plurality of pull-down means controlled by the decoded row address signals and connected in parallel between the common node and a ground voltage node; And the plurality of fuses connected between the common node and each pull-down means.

Wherein in the fuse decoding unit, each pull-down means comprises an NMOS transistor turned on by each decoded row address signal to supply the ground voltage to each fuse.

In the repair fuse test method according to an aspect of the present invention for achieving the above object, a fuse for decoding one of a plurality of decoded row addresses when the word line is active to determine any one of a repair pass and a normal pass Outputting a decoded signal and precharging the fuse decoded signal when the word line is in an inactive state; Latching the fuse decoded signal; Entering a test mode to stop the latch operation; And a fourth step of detecting whether the plurality of fuses are defective by comparing the fuse decode signal output in the second step with the fuse decode signal output in the third step.

The repair fuse test method according to another aspect of the present invention for achieving the above object is to fuse-decode the plurality of decoded row addresses when the word line is active to determine any one of a repair pass and a normal pass. Outputting a fuse decoding signal and precharging the fuse decoding signal when the word line is in an inactive state; Latching the fuse decoded signal; Entering a test mode to supply a driving capability adjustment voltage to the fuse decoded signal, thereby controlling a state of the fuse decoded signal so that the fuse decoded signal selects a repair pass; And a fourth step of detecting whether the plurality of fuses are defective by comparing the fuse decode signal output in the second step with the fuse decode signal output in the third step.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As an exemplary embodiment of the present invention, the structure of FIG. 2 is disclosed, and the exemplary embodiment of the present invention does not latch the fuse decoding signal NRDB by entering the test mode or by supplying a predetermined voltage to the common node COMM so that each fuse ( By checking the pull-down capability of the NMOS transistors N0 to N17 connected to F0 to F17, a tool for early detection of a failure by the fuses F0 to F17 can be provided.

In detail, the embodiment of FIG. 2 includes a precharge unit 10, a fuse decoder unit 20, a latch unit 30, and two test units 40 and 50.

The precharge unit 10 precharges the common node COMM with the precharge signal WLCB when the word line is in an inactive state. The precharge unit 10 may be configured as a PMOS transistor P0 connected between a power supply voltage VDD node and a common node COMM and receiving a precharge signal WLCB as a gate.

The fuse decoder unit 20 decodes the row address signals BAX1 <0: 1>, BAX2 <0: 1>, BAX34 <0: 3>, BAX56 <0: 3>, and BAX78 <when the word line is in an active state. 0: 3> and BAX9 <0: 1> decode the state information of the plurality of fuses F0 to F17 and transfer them to the common node COMM. The fuse decoder 20 includes a plurality of fuses F0 to F17 connected between the common node COMM and each of the NMOS transistors N0 to N17, and each of the fuses F0 to F17 and the ground voltage VSS node. BAX1 <0: 1>, BAX2 <0: 1>, BAX34 <0: 3>, BAX56 <0: 3>, BAX78 <0: 3>, BAX9 <0: 1 It may be composed of a plurality of NMOS transistors (N0 ~ N17) that receives the> to each gate.

The latch unit 30 latches a signal transmitted to the common node COMM and outputs the signal to the fuse decoding signal NRDB. The latch unit 30 includes an inverter IV0 for inverting the signal of the common node COMM and outputting the signal to the fuse decoding signal NRDB, and two PMOS connected in series between the power supply voltage VDD node and the common node COMM. It may be composed of transistors P2 and P3. At this time, the gate of the PMOS transistor P2 receives the fuse decoding signal NRDB, and the gate of the PMOS transistor P3 receives the signal output from the NOR gate NR.

The test unit 40 disables the latch operation of the latch unit 30 in the first test mode. The test unit 40 includes an inverter IV1 that inverts the precharge signal WLCB, an inverter IV2 that inverts the test signal TEST_MODE0 that is enabled when the first test mode is entered, and a signal and an inverter output from the inverter IV1. And a NOR gate NR combining the signals output from IV2).

The test unit 50 provides a high level voltage to the common node COMM in the second test mode. The test unit 50 is connected between an inverter IV3 inverting the test signal TEST_MODE1 enabled when the second test mode is entered, and a node connecting a power supply voltage VDD node and two PMOS transistors P2 and P3. And a PMOS transistor P4 that receives a signal output from the inverter IV3 as a gate.

Hereinafter, an operation of an embodiment of the present invention having the configuration as shown in FIG. 2 will be described in detail with reference to FIG. 3.

First, when both test signals TEST_MODE0 and TEST_MODE1 are in a disabled state, that is, in a normal mode, the embodiment of the present invention is in the address of the defective word line after the pre-test as in the prior art. In operation, the fuses F0 to F17 are cut.

In detail, since the precharge signal WLCB is disabled when the word line is not activated, the PMOS transistor P0 is turned on so that the common node COMM is precharged to a high level, and the inverter IV0 is connected to the inverter IV0. The common node COMM is latched to the high level by the two PMOS transistors P2 and P3.

Thereafter, when the word line is activated, the precharge signal WLCB is enabled to turn off the PMOS transistor P0.

Then, the signals BAX1 <0: 1>, BAX2 <0: 1>, BAX34 <0: 3>, BAX56 <0: 3>, BAX78 <0: 3>, and BAX9 <0: 1> that decode the row address are If the address is the same as that of the defective word line, the fuse decoding signal NRDB goes low and the normal path is blocked and the repair path is opened.

On the other hand, the signals BAX1 <0: 1>, BAX2 <0: 1>, BAX34 <0: 3>, BAX56 <0: 3>, BAX78 <0: 3>, and BAX9 <0: 1>, which decode the row address If is a different address from the defective word line, the fuse decode signal NRDB goes high and the repair pass is blocked and the normal path is left open.

Secondly, when the test signal TEST_MODE0 of the two test signals TEST_MODE0 and TEST_MODE1 is enabled, that is, in the first test mode, the embodiment of the present invention turns off the latch operation of the latch unit 30 to fuse F0 to F17) can be checked for defects.

In detail, when the word line is not activated, the common node COMM maintains a high level. When the word line is activated, the signal BAX1 <0: 1 in which the PMOS transistor P0 is turned off and the row address is decoded >, BAX2 <0: 1>, BAX34 <0: 3>, BAX56 <0: 3>, BAX78 <0: 3>, and BAX9 <0: 1> are input to each of the NMOS transistors N0 to N17.

At this time, since the test signal TEST_MODE0 is enabled, the PMOS transistor P3 of the latch unit 30 may be turned off, so that the state change of the common node COMM by the NMOS transistors N0 to N17 may proceed faster.

That is, even if the resistances of the fuses F0 to F17 increase in some cases, the common node COMM may descend to the low level quickly because there is no latch operation, and thus the resistance increase factor of the fuses F0 to F17 may increase. Will be less affected.

Therefore, in the embodiment of the present invention, even if a failure occurs due to an increase in the fuse resistance, the test signal TEST_MODE0 can be enabled to remedy the failure. By relieving the failure, the failure is caused by the fuses F0 to F17. Can be determined early.

Third, when the test signal TEST_MODE1 of the two test signals TEST_MODE0 and TEST_MODE1 is enabled, that is, in the second test mode, the embodiment of the present invention provides the NMOS transistors according to the driving capability of the two PMOS transistors P2 and P4. The driving capability margins of the N0 to N17 may be determined, and the driving capability margins of the MOS transistors N0 to N17 may be checked to determine whether the fuses are defective due to the fuses F0 to F17.

Looking at this in detail, the signals BAX1 <0: 1>, BAX2 <0: 1>, BAX34 <0: 3>, BAX56 <0: 3>, BAX78 <0: 3>, When the NMOS transistors N0 to N17 are turned on by BAX9 <0: 1>, the common node COMM falls to a low level.

At the same time, when the test signal TEST_MODE1 is enabled, the PMOS transistor P4 is turned on and both PMOS transistors P2 and P3 are turned on, so the common node COMM rises to a high level.

In this case, since the level of the common node COMM is determined according to the driving capabilities of the two PMOS transistors P2 and P4, the NMOS transistors N0 are designed by properly adjusting the driving capability of the two PMOS transistors P2 and P4. The driving capability margin of ˜N17) can be checked.

Therefore, according to an exemplary embodiment of the present invention, when the resistance of the fuses F0 to F17 is increased due to a certain defective element and a failure occurs, the test signal TEST_MODE1 is enabled to determine whether the fuses are early due to the fuses F0 to F17. You can check

FIG. 3 is a waveform diagram illustrating a state of the fuse decoding signal NRDB according to the normal mode and the test mode of the present invention when the resistances of the fuses F0 to F17 are increased. FIG. It indicates that the resistance of the fields F0 to F17 increases.

As can be seen in FIG. 3, in the normal mode, that is, the period <A>, as the resistance of the fuses F0 to F17 increases, a failure occurs in the fuse decoding signal NRDB at about NRDB_CASE13.

In the first test mode, that is, the interval <B>, the fuse decoding signal NRDB is almost normally enabled even when the resistances of the fuses F0 to F17 increase, and the fuses F0 to F17 are compared with the interval <A>. It can be easily determined that the defect by.

In addition, in the second test mode, that is, the interval <C>, as the resistance of the fuses F0 to F17 increases, a failure occurs in the fuse decoding signal NRDB at about NRDB_CASE3, which is compared with the interval <A>. It can be easily determined that the failure by (F0 ~ F17).

As described above, when the failure occurs, the present invention enters the test mode and stops the latch of the common node to which the fuse decoding signal is output, thereby relieving the failure, thereby checking whether the failure is caused by the fuse resistance during the initial test.

In addition, the present invention has an effect of detecting in advance whether a failure occurs in the operation by the transistors connected to the fuse by checking the driving capability margin of the transistors connected to the fuse when the failure enters the test mode.

In addition, the present invention can shorten the development period of the product by detecting a failure due to the fuse resistance in advance as described above, there is an effect that can improve the reliability of the product.

While the invention has been shown and described with reference to specific embodiments, the invention is not limited thereto, and the invention is not limited to the scope of the invention as defined by the following claims. Those skilled in the art will readily appreciate that modifications and variations can be made.

Claims (24)

A precharge unit configured to precharge a node to which a plurality of fuses are commonly connected when the word line is in an inactive state; A fuse decoding unit configured to fuse-decode the plurality of decoded row addresses to the common node when the word line is in an active state; A latch unit configured to output a fuse decoding signal for determining one of a repair pass and a normal pass through the common node and to latch the same; And And a test unit for disabling the latch operation of the latch unit in order to remedy failure caused by the plurality of fuses in a test mode. The method of claim 1, The latch unit, Inverting means for inverting the signal of the common node and outputting the signal as the fuse decoding signal; First pull-up means for pulling up the common node to a power supply voltage level by the fuse decoding signal; And And a switching means for connecting between the first pull-up means and the common node by an output signal of the test unit. The method of claim 2, And said first pull-up means comprises a first PMOS transistor which is turned on by said fuse decoding signal and supplies said power supply voltage to said switching means. The method of claim 2, And said switching means comprises a second PMOS transistor which is turned on by an output signal of said test part and connects between said first pull-up means and said common node. The method of claim 1, The test unit receives a test signal enabled in the test mode and a precharge signal enabled when the word line is inactivated, and disables the latch unit when both the test signal and the precharge signal are enabled. And a second logic level signal for enabling the latch unit when at least one of the test signal and the precharge signal is in a disabled state. . The method of claim 5, wherein The test unit, A first inverter for inverting the precharge signal; A second inverter for inverting the test signal; And The repair fuse circuit of claim 1, further comprising a NOR gate configured to NOR-combine the output signal of the first inverter and the output signal of the second inverter. The method of claim 1, The precharge unit, And second pull-up means for pulling up the common node to a power supply voltage level by a precharge signal enabled when the word line is activated. The method of claim 7, wherein And the second pull-up means comprises a third PMOS transistor turned on by the precharge signal to pull up the common node to a power supply voltage level. The method of claim 1, The fuse decoding unit, A plurality of pull-down means controlled by each decoded row address signal and connected in parallel between the common node and a ground voltage node; And And a plurality of fuses connected between the common node and the respective pull-down means. The method of claim 9, Wherein each pull down means comprises an NMOS transistor turned on by each decoded row address signal to supply the ground voltage to each fuse. A precharge unit configured to precharge a node to which a plurality of fuses are commonly connected when the word line is in an inactive state; A fuse decoding unit configured to fuse-decode the plurality of decoded row addresses to the common node when the word line is in an active state; A latch unit configured to output a fuse decoding signal for determining one of a repair pass and a normal pass through the common node and to latch the same; And And a test unit controlling a state of the fuse decoding signal by supplying a driving capability adjustment voltage to the common node in a test mode. The method of claim 11, The latch unit, Inverting means for inverting the signal of the common node and outputting the signal as the fuse decoding signal; And And a first pull-up means for pulling up the common node to a power supply voltage level by the fuse decoding signal. The method of claim 12, And the first pull-up means includes a first PMOS transistor turned on by the fuse decoding signal to supply the power supply voltage to the common node. delete The method of claim 11, And the test unit controls the fuse decoding signal to select a repair pass by supplying the driving capability adjustment voltage to the common node in the test mode. The method of claim 15, And the test unit includes second pull-up means for pulling up the common node to a power supply voltage level which is the driving capability adjustment voltage by a test signal enabled in a test mode. The method of claim 16, And the second pull-up means includes a second PMOS transistor turned on by the test signal to pull up the common node to the power supply voltage level. delete The method of claim 11, The precharge unit, And a third pull-up means for pulling up the common node to a power supply voltage level by a precharge signal enabled when the word line is activated. The method of claim 19, And the third pull-up means includes a third PMOS transistor turned on by the precharge signal to pull up the common node to a power supply voltage level. The method of claim 11, The fuse decoding unit, A plurality of pull-down means controlled by each decoded row address signal and connected in parallel between the common node and a ground voltage node; And And a plurality of fuses connected between the common node and the respective pull-down means. The method of claim 21, Wherein each pull down means comprises an NMOS transistor turned on by each decoded row address signal to supply the ground voltage to each fuse. When the word line is in an active state, fuse decoding is performed using a plurality of decoded row addresses to output a fuse decoding signal that determines either a repair pass or a normal pass, and precharges the fuse decode signal when the word line is in an inactive state. Making a first step; Latching the fuse decoded signal; Entering a test mode to stop the latch operation; And And a fourth step of detecting whether the plurality of fuses are defective by comparing the fuse decoded signal output in the second step with the fuse decoded signal output in the third step. Way. When the word line is in an active state, fuse decoding is performed using a plurality of decoded row addresses to output a fuse decoding signal that determines either a repair pass or a normal pass, and precharges the fuse decode signal when the word line is in an inactive state. Making a first step; Latching the fuse decoded signal; Entering a test mode to supply a driving capability adjustment voltage to the fuse decoded signal, thereby controlling a state of the fuse decoded signal so that the fuse decoded signal selects a repair pass; And And a fourth step of detecting whether the plurality of fuses are defective by comparing the fuse decoded signal output in the second step with the fuse decoded signal output in the third step. Way.

Images