KR20050065894A - Apparatus for interface pheriperal device with pc using parallel port and method thereof - Google Patents

Abstract

The present invention relates to an interface device with a peripheral device using a PC parallel port and a method thereof. In particular, by distinguishing transmission in sequential and non-sequential modes, and in the case of the sequential transmission, only the start address and the number of transmission information are transmitted to the peripheral device. The present invention relates to an interface device with a peripheral device using a PC parallel port and to a method for eliminating the time due to address transfer in each transmission and consequently improving the performance of the peripheral device.

An interface device with a peripheral device using a PC parallel port of the present invention is an interface device for connecting a PC having an arbitrary parallel port with a peripheral device, and is connected to the PC parallel port to transmit transmission information, start address, and number of transmissions. A command analyzer for receiving a transfer command, storing the result in a corresponding register and analyzing the register to directly generate a destination address in the non-sequential transfer mode, and transmitting the start address and the number of transfers in the sequential transfer mode; A sequential address generator for generating a sequential address for each transmission cycle of each data in the sequential transmission mode and generating an end signal when a predetermined number of transmissions are in progress; A control signal generator for generating a synchronization signal of the command analyzer and the sequential address generator and a read / write and chip enable signal of a final destination; A bus direction switch for controlling a direction of a bidirectional data bus by a read / write signal input from the control signal generator; And selecting a destination address as an output of the sequential address generator in the sequential transfer mode based on the analysis of the transfer command of the bus direction changer and the command analyzer, and in the non-sequential transfer mode, the destination address in the address register of the command parser. And an address selector for performing a function of selecting a value.

Description

Apparatus for interface pheriperal device with PC using parallel port and method example}

The present invention relates to an interface device with a peripheral device using a PC parallel port and a method thereof. In particular, by distinguishing transmission in sequential and non-sequential modes, and in the case of the sequential transmission, only the start address and the number of transmission information are transmitted to the peripheral device. The present invention relates to an interface device with a peripheral device using a PC parallel port and to a method for eliminating the time due to address transfer in each transmission and consequently improving the performance of the peripheral device.

In general, the parallel port of the initial PC (Personal Computer) was used as a printer-only port for transmitting only one-way data from the PC to the printer.

However, the functions and performance of the parallel port have been greatly improved for faster interface with high performance printers with various fonts and graphics support. It is also used as an interface with various peripheral hardware as well as a printer because of its high compatibility between PCs, simple interface circuits, and easy software development for port control.

1 is a block diagram schematically illustrating a peripheral device to which a general interface device is applied.

As shown in FIG. 1, a PC 10 having an IEEE1284 standard parallel port 15 and an interface device 40 in the peripheral device 30 are connected via an IEEE1284 cable 20. As shown in FIG.

The peripheral device 30 connected to the PC 10 includes a controller 50, a data unit 60, and the like, including an interface device 40 for connecting the IEEE1284 standard parallel port 15. The parallel port 15 of the PC 10 performs initialization, command transmission, and state identification for controlling the peripheral device 30 through communication with the controller 50, and inputs and operates data for operation of the peripheral device 30. The output of the result is performed by data transmission with the data unit 60.

The PC 10 software transmits an address and a read / write signal to a register (or memory) to be controlled (or transmitted), and then operates in the order of writing or reading data.

However, the conventional general peripheral device 30 as described above may be mainly represented by the control unit 50 communicated by non-sequential mode transmission and the data unit 60 capable of sequential mode data transmission, and sequentially transmitting the sequential ( Sequential) Since the data transmission / reception time by the addressing approach is relatively longer than the control data transmission / reception time according to the non-sequential address access, the data transmission / reception between the data unit 60 and the PC 10 rather than the control unit 50 is performed. Most of the time.

For example, in the case of the peripheral device 30 including the control unit 50 having j address areas and the largest address value of each area is represented by n, 1 byte data is stored in each component (register or memory). The minimum number of bytes to be transmitted to the parallel port for transmission is as follows:

Number of parallel port accesses for 1 byte transfer

= Number of bytes for address + read / write signal + number of data

= j * n The number of bytes that can represent the address + 1 + 1 --------- (Equation 1)

Number of parallel port accesses for m bytes

= (Equation 1) * m ------------------------------------------- ------- (Equation 2)

As described above, when analyzing the data transmission time of the PC 10 and the peripheral device 30, the sequential of sequentially transmitting data in units of blocks rather than transmitting / receiving control data according to non-sequential address access. This takes most of the time for data transmission and reception of address access.

In particular, when data transmission of more than Mega level is required, there is a problem that can dramatically decrease the performance of the peripheral device 30 and the PC 10.

The present invention has been made to solve the above problems, an object of the present invention is to distinguish the transmission in the sequential and non-sequential mode, and in the case of the sequential transmission by transmitting only the start address and the number of transmission information to the peripheral device, The present invention provides an interface device and a method of connecting to a peripheral device using a PC parallel port, which eliminates time due to address transfer and improves the performance of the peripheral device.

In order to achieve the above object, an interface device with a peripheral device using a PC parallel port of the present invention is an interface device for connecting a peripheral device with a PC having an arbitrary parallel port, and is connected with the PC parallel port to transmit information. A command analyzer for receiving a start command and a transfer command of the number of transfers, storing the result in a corresponding register, analyzing the transfer address, and directly generating a destination address in the non-sequential transfer mode, and transmitting the start address and the transfer number in the sequential transfer mode; A sequential address generator for generating a sequential address for each transmission cycle of each data in the sequential transmission mode and generating an end signal when a predetermined number of transmissions are in progress; A control signal generator for generating a synchronization signal of the command analyzer and the sequential address generator and a read / write and chip enable signal of a final destination; A bus direction switch for controlling a direction of a bidirectional data bus by a read / write signal input from the control signal generator; And selecting a destination address as an output of the sequential address generator in the sequential transfer mode based on the analysis of the transfer command of the bus direction changer and the command analyzer, and in the non-sequential transfer mode, the destination address in the address register of the command parser. And an address selector for performing a function of selecting a value.

In the above configuration, the command analyzer comprises: a command register unit for storing a transfer command including information for distinguishing between sequential / non-sequential transfer mode and transmit / receive mode; An address register section for storing a start address of a transfer destination; A transfer count register unit for receiving and storing the transfer count from a PC only in the sequential transfer mode; And a finite state machine (FSM) _1 unit for controlling the operation of each unit.

Preferably, the sequential address generator comprises: an address generator for inputting a start address from an address register of the command analyzer and generating addresses sequentially in each data transmission cycle; An end signal generator for receiving the number of transfers from the number of transfer registers of the command analyzer and counting them for each data transfer cycle, and determining whether data transfer cycles have progressed by the number of transfers and generating a sequential transfer end signal; And a finite state machine (FSM) _2 unit for controlling the operation of each unit.

And, the interface method for connecting a peripheral device and a PC having any parallel port, comprising: (a) checking the ready state of the peripheral device; (b) delivering a transfer command including information distinguishing between the sequential / non-sequential transfer mode and the transmit / receive mode; (c) delivering an address of a destination to be transmitted; (d) delivering a quantity of data to be transmitted only in the sequential mode of the transmitted transmission commands; (e) a command transfer end checking step for checking whether transfer of the transferred commands is completed and whether data transfer can proceed; (f) When the command transmission is completed in step (e), it is determined whether the transmitted transmission command is a sequential transmission mode or a non-sequential transmission mode. A data transmission / reception step of repeatedly transmitting and receiving data by the number of transmissions in the sequential mode; And (g) checking the transmission completion status.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. This embodiment is not intended to limit the scope of the invention, but is presented by way of example only.

FIG. 2 is a block diagram schematically illustrating an interface device with a peripheral device using a PC parallel port according to an embodiment of the present invention. FIG. 3 is a block diagram illustrating the command analyzer of FIG. 2 in detail. 2 is a block diagram illustrating the sequential address generator in detail.

First, the connection relationship and configuration of the peripheral device 30 and the PC 10 to which the interface device according to the present invention is applied have the same operation as the above-described conventional configuration, and a detailed description thereof will be omitted (FIG. 1). Reference).

2 to 4, the interface device with the peripheral device using the PC parallel port according to the present invention, the command analyzer 200, the sequential address generator 300, the control signal generator 400, the bus direction changer 500 and the address selector 600.

In the above-described configuration, the command analyzer 200 is connected to the parallel port 15 of the PC 10, and receives the transfer information, the start address, and the transfer command of the number of transfers from the PC 10 and stores them in the register. The target address is directly generated in the non-sequential transfer mode, and the start address and the number of transfers are transmitted in the sequential transfer mode.

The command analyzer 200 includes a command register 210 for storing a transfer command including information for distinguishing between sequential / non-sequential transfer mode and transmit / receive mode, and an address register for storing a start address of a transfer destination. A unit 220, a transfer number register unit 230 for receiving and storing the number of transfers from the PC 10 only in the sequential transfer mode, and a finite state machine (FSM_1) unit for controlling the operation of each unit. It consists of 240.

The sequential address generator 300 generates a sequential address for each transmission cycle of each data in the sequential transmission mode, and generates a termination signal when the predetermined number of transmissions is in progress.

The sequential address generator 300 inputs a starting address from the address register unit 220 of the command analyzer 200 and generates an address sequentially for each data transmission cycle, and the command analyzer 200. Receiving the number of transfers from the transfer number register unit 230, counting them for each data transfer cycle, and determining whether the data transfer cycle has been progressed by the number of transfers, and generating a sequential transfer end signal. And a finite state machine (FSM) _2 unit 330 for controlling the operation of each unit.

At this time, the address generator 310 obtains an address necessary for the next data transmission from the current address by increasing or decreasing it, and the termination signal generator 320 counts the number of transmissions up to the present, and transfers as many as the number of transmissions. It checks every transmission cycle if it is lost, and if it completes, it generates an end signal and ends the data transfer cycle.

The control signal generator 400 generates a synchronization signal of the command analyzer 200 and the sequential address generator 300 and a read / write and chip enable signal of the final destination. do.

The bus direction changer 500 controls the direction of the bidirectional data bus by a read / write signal input from the control signal generator 400.

The address selector 600 selects the destination address as the output of the sequential address generator 300 in the sequential transfer mode based on the analysis of the transfer commands of the bus direction changer 500 and the command analyzer 200, and the non-sequential transfer mode. In this case, the target address selects the address register value of the command analyzer 200.

FIG. 5 is a flowchart for describing an operation of the command analyzer 200 of FIG. 3.

As shown in FIG. 5, first, in step S100, various commands transmitted from the PC 10 are input (stored), and the flow proceeds to step S110 to input a start address among the transmitted commands.

Next, in step S120, it is determined which transmission mode the transmitted command is. In case of the non-sequential transmission mode, the flow proceeds to step S130, where non-sequential data, that is, a destination address is generated and transmitted, and returned to step S100.

As a result of the determination in step S120, in the sequential transmission mode, the process proceeds to step S140 to input the number of transmissions, activates the transmission mode, and proceeds to step S150 to determine whether the transmission is completed and the transmission is completed. Is returned to the step S100.

That is, when the information command input from the PC 10 is examined and analyzed in the sequential transfer mode, the command number is continuously received and stored in the transfer number register 230 to generate a command transfer completion flag to start a data transfer cycle. . Otherwise, if the information command is analyzed in non-sequential mode, the command analysis step is completed by omitting the number of transmissions and generating a command completion flag.

On the other hand, the above-described operation flow of the command analyzer 200 is preferably implemented through the FSM_1 unit 240.

Here, the clock signal for transitioning the operation state of the FSM_1 unit 240 uses an Address_Strobe or Data_Strobe signal among the EPP operation signals 100 of the parallel port 15 of the PC 10 as an input. The control signal generator 400 uses a signal manipulated according to the system speed of the peripheral device 30.

FIG. 6 is a flowchart for describing an operation of the sequential address generator 300 of FIG. 4.

As shown in FIG. 6, first, in step S200, it is determined whether the transmission mode is activated in the sequential transmission mode, and when the transmission mode is activated, the process proceeds to step S210 to initialize the address and the end signal, and the process proceeds to step S220. In addition to transmitting data, an address is generated.

Next, in step S230, it is determined whether the generated address is an end address, and if it is an end address, the process proceeds to step S240 to generate an end signal. In addition to transmitting, it generates an address.

On the other hand, as described above, the operation flow of the sequential address generator 300 described above is preferably implemented through the FSM_2 unit 330.

Here, the clock signal for transitioning the operation state of the FSM_2 unit 330 receives a signal not used by the FSM_1 unit 240 among the Address_Strobe and Data_Strobe of the EPP operation signals 100, and the control signal generator ( 400, a signal manipulated according to the system speed of the peripheral device 30 is used.

Hereinafter, the interface method with the peripheral device using the PC parallel port of the present invention having the above-described configuration will be described in detail.

7 is a flowchart illustrating an interface method with a peripheral device using a PC parallel port according to an embodiment of the present invention.

As shown in FIG. 7, first, in step S300, the state of the peripheral device 30 is checked by the PC 10 to prepare the state of the command analyzer 200 and the sequential address generator 300 and the PC of the peripheral device 30. (10) Perform a read operation of the status information to allow access from.

Next, the process proceeds to step S301 to determine whether the read of the state information has been performed (if read) has not been performed, and returns to the step S300, otherwise the read of the state information (Read) has been performed In other words, if the peripheral device 30 is ready to communicate, the process proceeds to steps S302 and S303, where the PC 10 transmits the information command and the start address which is the destination of the transmission to the command analyzer 200 inside the interface device. At this time, the information command and the start address are stored in the corresponding register of the command analyzer 200, respectively.

Thereafter, in step S304, the input information command is examined to determine which transmission mode. In the case of sequential transmission mode, the process proceeds to steps S305 and S306 where the PC 10 transmits the number of transmissions to the command analyzer 200. A read operation of the command analyzer 200 and the sequential address generator 300 and the state information allowing access from the PC 10 of the peripheral device 30 is performed.

On the other hand, when the determination result in step S304, in the non-sequential transmission mode, the process proceeds directly to step S306 without performing the transfer of the transmission number of step S305 to perform a read operation of the peripheral device state.

Next, in step S307, it is determined whether the command transmission between the PC 10 and the command analyzer 200 is completed. If not, the process returns to step S306. Otherwise, if the command transmission is completed, the process proceeds to step S308. It is determined which transmission mode is the information command.

As a result of the determination in step S308, in the sequential transmission mode, the flow proceeds to step S309 to transmit / receive each data, and the flow proceeds to step S310 to determine whether an end address has been generated and until the end address is generated. Is returned to continue sending / receiving each data.

On the other hand, if the end address is generated as a result of the determination in step S310, the process proceeds to step S311 to prepare the state of the command analyzer 200 and the sequential address generator 300 and from the PC 10 of the other peripheral device 30. Read the status information to allow access.

That is, the command transmission completion flag generated by the command analyzer 200 is checked, and the address generator 310 and the end signal generator 320 inside the sequential address generator 300 are started address registers of the command analyzer 200. Initialize with and transfer count register values, respectively. In this case, the initialization synchronization signal used may save a transmission cycle by using a peripheral device read signal generated to check the completion of command transmission in step S307. After the address generator 310 and the end signal generator 320 are initialized, data transmission and reception are performed in synchronization with the data transmission cycle of the PC 10.

On the other hand, in the case of the non-sequential transmission mode, the determination result in step S308 proceeds directly to step S312 without going through the steps S309 and S310, and the data is synchronized in synchronization with the data transmission cycle performed once from the PC 10. After the transmission / reception is completed, the process proceeds to step S311 to perform a read operation of the peripheral device state.

In this case, the destination address directly transfers the contents of the start address of the command analyzer 200 through the address selector 600, and as a result, the sequential address generator 300 does not need to operate.

Next, in step S313 it is determined whether the data transmission is successful, if the data is successfully transmitted to step S314 to confirm the success of the data transmission, otherwise, if the data was not successfully transmitted to step S315 Check the data transmission failure.

That is, in step S307, when the command transmission between the PC 10 and the command analyzer 200 is completed, a data transmission cycle is started. The PC 10 having completed the command transmission including the number of transmissions is in the state of the peripheral device 30. Check again.

At this time, if it is determined that the generated command transmission completion flag is an undesired value, the transmission starts from the beginning, and if there is no problem in the command transmission completion check in step S307, the PC 10 exits the transmission mode. In consideration of the non-sequential transmission mode, the data transmission cycle is performed once. Otherwise, in the sequential transmission mode, the data transmission is repeated as many times as desired. After the data transmission is completed, finally, the status of the peripheral device is checked to confirm whether the transmission is successful. At this time, the end signal output from the sequential address generator 300 is used as a state check element.

As described above, when the interface method according to the present invention is applied to the peripheral device 30, the existing Equation 2 is summarized as the following Equation 3, and when m2 is considerably larger than m1, the time taken for the entire interface is approximately ( Equation 1) can be shortened, and as a result, performance degradation due to data transmission time of mega level or more can be improved.

Number of parallel port accesses for m bytes

= Number of times for non-sequential + number of times for sequential

= {(Equation 1) * m1} + (Command Information + Status Check + m2) ----------------------- (Equation 3)

(However, m = m1 + m2, command information = j * n can represent the number of bytes + m2 can represent the byte status check = 2 ~ 3 byte reads)

Although a preferred embodiment of the interface device and a method using the PC parallel port according to the present invention and the method described above, the present invention is not limited to this, but the claims and the detailed description of the invention and the accompanying drawings It is possible to carry out various modifications within the scope and this also belongs to the present invention.

According to the interface device and the method using the PC parallel port of the present invention as described above, distinguish the transmission in the sequential and non-sequential mode, in the case of the sequential transmission only the start address and the number of information to be transmitted to the peripheral device By eliminating the time required for address transfer in every existing transmission, the time taken for the entire interface can be effectively reduced, resulting in improved performance of peripheral devices by improving performance degradation caused by data transfer time of mega level or more. There is an advantage to this.

1 is a block diagram schematically illustrating a peripheral device to which a general interface device is applied;

Figure 2 is a block diagram showing an overall interface device with a peripheral device using a PC parallel port according to an embodiment of the present invention,

3 is a block diagram illustrating in detail the command analyzer of FIG. 2;

4 is a block diagram illustrating in detail the sequential address generator of FIG.

FIG. 5 is a flowchart illustrating an operation of a command analyzer of FIG. 3;

6 is a flowchart for explaining an operation of the sequential address generator of FIG. 4;

7 is a flowchart illustrating an interface method with a peripheral device using a PC parallel port according to an embodiment of the present invention.

*** Explanation of symbols on main parts of drawing ***

100: EPP operation signal of the parallel port, 200: command analyzer,

210: command register section 220: address register section

230: Transfer count register part, 240: FSM_1 part,

300: sequential address generator, 310: address generator,

320: end signal generator, 330: FSM_2 part,

400: control signal generator, 500: bus direction changer

Claims (7)

In the interface device for connecting a peripheral device and a PC having an arbitrary parallel port, It is connected to the PC parallel port and receives the transfer information, start address and transfer command of the transfer number, and stores and analyzes it in the corresponding register to generate the target address directly in the non-sequential transfer mode.In the sequential transfer mode, the start address and transfer count Command analyzer for transmitting the; A sequential address generator for generating a sequential address for each transmission cycle of each data in the sequential transmission mode and generating an end signal when a predetermined number of transmissions are in progress; A control signal generator for generating a synchronization signal of the command analyzer and the sequential address generator and a read / write and chip enable signal of a final destination; A bus direction switch for controlling a direction of a bidirectional data bus by a read / write signal input from the control signal generator; And In the sequential transfer mode, the target address is selected as the output of the sequential address generator in the sequential transfer mode based on the analysis of the transfer command of the bus direction changer and the command analyzer. Interface device with a peripheral device using a PC parallel port, characterized in that it comprises an address selector for performing a function for selecting. The method of claim 1, wherein the command analyzer, A command register section for storing a transfer command including information for distinguishing between the sequential / non-sequential transfer mode and the transmit / receive mode; An address register section for storing a start address of a transfer destination; A transfer count register unit for receiving and storing the transfer count from a PC only in the sequential transfer mode; And Interface device with a peripheral device using a PC parallel port characterized in that it comprises a finite state machine (FSM) _1 for controlling the operation of each unit. The clock signal of claim 2, wherein the clock signal for transitioning the operation state of the FSM_1 unit is used as an input of Address_Strobe or Data_Strobe signal among the EPP operation signals of the PC parallel port, and the control signal generator is manipulated according to the system speed of the peripheral device. Interface device with a peripheral device using a PC parallel port, characterized in that made to use a signal. The sequential address generator of claim 1, wherein the sequential address generator comprises: An address generator for inputting a start address from the address register of the command analyzer and generating addresses sequentially in each data transfer cycle; An end signal generator for receiving the number of transfers from the number of transfer registers of the command analyzer and counting them for each data transfer cycle, and determining whether data transfer cycles have progressed by the number of transfers and generating a sequential transfer end signal; And Interface device with a peripheral device using a PC parallel port characterized in that it comprises a finite state machine (FSM) _2 for controlling the operation of each part. The peripheral signal system of claim 4, wherein the clock signal for transitioning the operation state of the FSM_2 unit receives a signal not used in the FSM_1 unit among Address_Strobe and Data_Strobe of the EPP operation signal of the PC parallel port. Interface device with a peripheral device using a PC parallel port, characterized in that to use a signal manipulated according to the speed. In the interface method for connecting a peripheral device and a PC having an arbitrary parallel port, (a) checking a ready state of the peripheral device; (b) delivering a transfer command including information distinguishing between the sequential / non-sequential transfer mode and the transmit / receive mode; (c) delivering an address of a destination to be transmitted; (d) delivering a quantity of data to be transmitted only in the sequential mode of the transmitted transmission commands; (e) a command transfer end checking step for checking whether transfer of the transferred commands is completed and whether data transfer can proceed; (f) When the command transmission is completed in step (e), it is determined whether the transmitted transmission command is a sequential transmission mode or a non-sequential transmission mode. A data transmission / reception step of repeatedly transmitting and receiving data by the number of transmissions in the sequential mode; And (g) A method for interfacing with a peripheral device using a PC parallel port, comprising the step of checking a transmission completion state. The method according to claim 6, wherein when checking the ready state of the peripheral device in the step (a), when checking the completion of the command transfer in the step (e), and when checking the transmission completion state in the step (g), Peripheral device using the PC parallel port characterized in that the status flag value generated by the command analyzer and the sequential address generator and other peripheral device status information are directly read by using an input signal from the parallel port signal to the PC. How to interface with.