KR20050065874A - Apparatus and method for ctc decoder - Google Patents

Abstract

The present invention relates to an apparatus and method for CTC decoding, and more particularly, to an apparatus and method for implementing a CTC decoder with VLSI.

The CTC decoding apparatus arranges CTC decoders including one MAP decoder in parallel. The MAP decoder simultaneously performs the forward state metric operation and the reverse state metric operation to decode 2 bits per unit time. To this end, the reverse operation unit that calculates the forward state metric and the forward operation unit that calculates the reverse state metric are arranged in a vertically symmetrical structure. The state metric calculation unit uses all determined state metric values by adding one more than necessary bits, and after completion of the state metric operation, inspects the most significant bit of each metric value and resets it when overflow occurs, thereby minimizing operation delay.

In this way, the decoding speed can be increased.

Description

CT decoding apparatus and method {APPARATUS AND METHOD FOR CTC DECODER}

The present invention relates to a CTC decoder device and method for improving the decoding speed and minimizing the area consumption in hardware implementation.

In general, in a wired / wireless digital communication system, an additional bit is added to an information bit at a transmitter to correct an error on a transmission path, and an error is corrected using an error correction algorithm at a receiver. As one of these error correction algorithms, Turbo Code is used. In general turbo code, the encoder receives and processes one bit input every clock, while in Convolutional Turbo Code (CTC) code, two bits are input and processed every clock. Therefore, the processing speed in the CTC decoder is about twice that of binary turbo code.

The CTC code has been adopted as the 802.16a channel codec, which is being studied recently, and has also been adopted in a high speed personal Internet (HPi) wireless communication system.

The turbo decoder is implemented using existing binary turbo codes and algorithms. However, it has a structure partially accommodating the characteristics of the CTC. The decoding algorithm is largely divided into Maximum A Posteriori (MAP) and Soft Out Viterbi Alogorithm (SOVA), and the maximum post algorithm is pure pure MAP and log maximum post-mortem. (LOG-MAP), the maximum log maximum post (MAX-LOG-MAP or MIN-LOG-MAP) method. For the hardware implementation, the log max post method or the max log max post method which are somewhat inferior in error correction capability but low in implementation complexity are mainly used.

In a typical turbo decoder, two MAP decoders are used, and an interleaver exists to match the order of bit strings between the MAP decoders. Each MAP decoder contains the received symbol and the surplus information value that is the result of the MAP decoder of the previous stage, calculates the current probabilistic weight, and uses this value and the input value to generate new surplus information to be used as the input value of the next stage MAP decoder. do. This surplus information is combined with the received symbol to help calculate more reliable probabilistic weights in the next stage MAP decoder. By repeating the decoding process, the reliability of the soft decision result value of the decoder is gradually increased, thereby improving the error correction capability.

The general operation of the MAP decoder, which is the core operation unit of the CTC decoder, is as follows. Important elements of the MAP decoder include branch metric operation, forward state metric operation, reverse state metric operation, and stochastic weight operation.

The branch metric may be obtained using the received symbol and the surplus information calculated in the front end MAP decoder as a probabilistic weight to be shifted from the current time to the next time on the trellis.

The forward state metric calculates the forward state metric at the present time by using the previous forward state metric and the current branch metric as probabilistic weights for all states starting from time 0 and time N.

The reverse state metric calculates the current reverse state metric by using the previous reverse state metric and the branch metric of the current time as probabilistic weights for all states starting from the time point N until time 0.

Probabilistic weights are obtained using the branch metric, forward state metric, and reverse state metric calculated above.

However, such a CTC decoder has a limitation in processing the high speed data required in the personal portable Internet.

The present invention is to solve the above problems, the technical problem to be achieved by the present invention is to provide a CTC decoder device and method that can reduce the decoding execution time.

In order to solve this problem, the present invention provides a CTC decoding apparatus for decoding a transmission symbol encoded and transmitted by a CTC code from a transmitter.

According to an aspect of the present invention, there is provided a CTC decoder, including: a MAP decoder configured to simultaneously perform operations on a forward state metric and a reverse state metric to decode 2 bits per unit time for the symbol; A multiplexer for adjusting inputs and outputs when decoding the MAP decoder; An interleaver / deinterleaver that matches the value output from the demultiplexer with the order of symbols applied in the next decoding; A deinterleaver for deinterleaving the calculated likelihood ratio after decoding from the MAP decoder; And a hard determiner that estimates the final decoding bit based on the value output from the deinterleaver.

The MAP decoder performs a forward state metric and a reverse state metric operation on four probabilities in parallel for the current decoded bit value and stores the result in each memory to time N / 2. And a forward calculating unit and a reverse calculating unit performing a stochastic weighting operation, wherein the forward calculating unit and the reverse calculating unit have a vertically symmetrical structure.

The forward calculation unit may further include: an upper branch metric calculation unit configured to perform branch metrics on four probabilities of bit values to be decoded for sequentially received reception symbols; A forward state metric calculator for calculating a current state metric using a result value of the upper branch metric calculator and a previous state metric value; A first memory configured to store a state metric value calculated from the forward state metric calculator; An upper probabilistic weight calculator for calculating probabilistic weights using the previous state metric value, the branch metric value, and the current state metric value; And an upper surplus information calculating unit configured to generate surplus information based on the probabilistic weights output from the upper probabilistic weight calculating unit, wherein the reverse calculating unit has four probabilities that the bit values to be decoded for the received symbol are input in reverse order. A lower branch metric calculator for performing branch metrics on the branch; A reverse state metric calculator for calculating a current state metric using a result value of the lower branch metric calculator and a previous state metric value; A second memory for storing a state metric value calculated from the reverse state metric calculation unit; A bottom probabilistic weight calculation unit configured to calculate probabilistic weights using the previous state metric value, the bottom branch metric value, and the current state metric value; And a lower surplus information calculating unit generating surplus information based on the probabilistic weights output from the lower probabilistic weight calculating unit, and simultaneously performing the forward state metric and the reverse state metric.

The state metric calculator comprises: first and second adders for outputting a minimum value by a specific operation from a value obtained by adding a previous state metric value and a branch metric value for the four probabilities; A combiner to which the output bits are input based on the specific operation; And a multiplexer for outputting a minimum value based on a value output from the combiner, a previous state metric value for the four probabilities, and a branch metric value. In this case, the forward state metric calculation unit or the reverse state metric calculation unit adds the output state metric value more than the required number of bits, and after completion of the state metric operation, checks and normalizes the most significant bit of each metric value. The overflow is determined based on the most significant bit check result of all state metrics, and when the overflow occurs, the operation delay is minimized by resetting all the most significant bit values.

The surplus information calculating unit may normalize by reducing the size of the value obtained by subtracting the input prior probability value APP from the calculated probabilistic weight by half.

The interleaver may further include a counter that counts up to 1/2 of the size of the CTC code block while sequentially increasing; A first multiplexer receiving a least two bits of the count value as a control value and outputting a constant value; First and second adders that receive a specific value and add an operation by a specific operation; A first comparator configured to generate an output value based on a comparison result between the value output from the second adder and a reference value; A second multiplexer which receives an output value from the first comparator and an output value from the first and second adders and selects one output value; Third and fourth adders for adding the constant value and an output value from a second multiplexer; A second comparator for generating an output value based on a result of comparing the output value from the fourth adder with a reference value; A third multiplexer which receives an output value from the second comparator and output values from the third and fourth adders and selects one output value, wherein the values output from the first and second multiplexers are respectively D; And is stored in a flip-flop.

The interleaver may further include: a fifth adder configured to add and receive a specific value by an output value and a specific operation from the third multiplexer; A third comparator configured to generate an output value based on a result of comparing the output value of the fifth adder with a reference value; And a fourth multiplexer which receives an input / output value of the fifth adder and an output value from the third comparator and selects one output value, wherein the fourth multiplexer outputs an interleaving address.

The CTC decoder further includes first and second memory units for storing the output from the MAP decoder. During the first decoding, a value obtained by adding a received symbol and a value stored in the second memory unit is input. When performing the first decoding, a value stored in the first memory is input. And the multiplexer comprises: first and second multiplexers for adjusting the input of the MAP decoder; And a third multiplexer for adjusting the output of the MAP decoder, wherein the MAP decoder receives a value input from the first and second multiplexers, outputs a logarithmic likelihood ratio, and a probabilistic weight output from the MAP decoder. Is input to the third multiplexer. A first adder for adjusting an input to a first multiplexer located in front of the MAP decoder; And second and third adders for adjusting the probabilistic weight input to the third multiplexer.

According to the present invention, there is provided a CTC decoding method for decoding a transmission symbol encoded and transmitted by a CTC code from a transmitter.

According to another aspect of the present invention, there is provided a CTC decoding method comprising the steps of: a) multiplexing and receiving a transmission symbol encoded and received by the CTC code; b) a first demodulation step of calculating first probabilistic weights for four probabilities of bit values to be decoded for a symbol received from step a); c) a second demodulation step of receiving surplus information output from the first probabilistic weights and a value obtained by adjusting the calculated first probabilistic weights, and calculating and outputting a second probabilistic weight; And d) hard determining from the probabilistic weights output after the second decoding to determine a final decoding bit, wherein the input and output are adjusted for each decoding step.

And the step b) comprises: i) outputting a first probabilistic weight according to the first order decoding based on the symbol value received from the step a); Ii) adjusting and multiplexing the output value of the first probabilistic weights to output a specific value; And iv) interleaving and storing the specific value output from step ii).

And the step c) comprises: i) outputting a second probabilistic weight according to the second decoding based on the symbol value received from the step a); Iii) adjusting and multiplexing the output value of the second probabilistic weights to output a specific value; And iv) interleaving and storing the specific value output from the step iii).

The probabilistic weight calculation step may include a branch metric calculation step of performing a branch metric operation on four probability paths of a received symbol in sequential or reverse order; A state metric calculation step of determining a minimum value as a current state metric value by a specific operation from a value obtained by adding previous state metric values and branch metric values respectively inputted for the four probability paths for the sequentially input received symbols; A probabilistic weight calculation step of determining respective probabilistic weights using the previous state metric value, the branch metric value, and the current state metric value; And a redundancy information calculating step of generating surplus information based on the probabilistic weights, wherein the four states of the forward state metric values for the four probabilistic paths of the received symbols sequentially input and the four probabilities of the received symbols input in the reverse order Simultaneously calculating the reverse state metric value for the path, it is characterized by decoding two bits per unit time.

And the state metric calculation step includes: adding one more all the determined state metric values than the number of required bits; Checking the most significant bit of each metric value after completion of the state metric operation; And resetting the values of all the most significant bits to a second value if the most significant bit of all the state metrics for the four probability paths of the received symbol has the first value as a result of the check. If the bit has a first value, the overflow is considered to have occurred.

The surplus information calculating step may include generating surplus information by subtracting a prior information value inputted from the calculated probabilistic weights; And normalizing by multiplying the generated surplus information value by 1/2.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

Hereinafter, the configuration and operation of the present invention will be described by taking a CTC code having a code rate 1/2 adopted in the 802.16a standard as an example.

First, a turbo encoder having a code rate 1/2 adopted in the 802.16a standard will be described with reference to FIG.

1 is a diagram illustrating a general turbo encoder having a code rate of 1/2.

As shown in FIG. 1, the turbo coder 10 having a code rate of 1/2 adopted in the 802.16a standard has a parity bit surplus through the first convolutional encoder 2 from an information bit string to which A and B are input. Bit) Y1 is generated and output. In addition, after the inputs A and B are rearranged by the interleaver 1, the parity bits Y2 are generated and output through the second convolutional encoder 3 connected in parallel with the first convolutional encoder 2. The inputs A and B output C1 and C2 which are not encoded as they are. The generated parity bits and uncoded symbols are serially converted by the parallel / serial converter 4 to generate one output symbol.

The turbo encoder 10 configured as described above allows repeated decoding by generating independent parity through the first and second convolutional encoders 2 and 3.

Next, a description will be given taking a CTC code having a code rate of 1/2 adopted in the 802.16a standard as an example for a general turbo coder having a code rate of 1/2.

2 is a structural diagram of a fast CTC decoder in which four CTC decoders are arranged in parallel according to an embodiment of the present invention.

As shown in FIG. 2, the CTC decoder 100 according to the embodiment of the present invention arranges four CTC decoders 101, 102, 103, and 104 in a parallel structure. Since each of the CTC decoders 101, 102, 103, and 104 have the same function and the internal structure thereof is the same, the following describes one CTC decoder in detail with reference to FIG.

3 is a structural diagram of a CTC decoder using a MAP decoder according to an embodiment of the present invention.

As shown in FIG. 3, the turbo decoder 101 according to the embodiment of the present invention shares and uses one MAP decoder 110.

Turbo encoder 101 according to an embodiment of the present invention is MAP decoder 110, adders 112, 134, 136, multiplexers 114, 116, 118, 128, interleaver / deinterleaver 120, demultiplexer Reference numeral 122, memories 124 and 126, deinterleaver 130, and hard determiner 132.

The MAP decoder 110 performs the forward state metric operation and the reverse state metric operation in parallel, stores the result in each memory, and performs decoding by calculating probabilistic weights from the time N / 2.

The adder 112 adds an input value and outputs it.

The multiplexer 114, 116, 118, 128 selects one of a number of inputs and connects it to the output. In this way, the input and output of the MAP decoder are adjusted.

The interleaver / deinterleaver 120 rearranges the order of the inputted information.

Demultiplexer 122 connects one input to multiple outputs.

The memories 124 and 126 store values output from the demultiplexer 122.

The deinterleaver 130 rearranges the information rearranged by the interleaver in the same order as the original information.

The hard determiner 132 determines the final decoded value output.

Next, the operation of the CTC decoder will be described in detail.

Let's look at the definition of probabilistic weights to determine the input and output values according to the decoding order. In the CTC decoder, there are four types of probability values occurring in the stage: "00", "01", "10", and "11". Since it cannot be expressed as a value as a ratio, the final decoding bit is determined while storing and using probability values for each.

When the first MAP decoding is performed in one iterative decoding process, there are two input values of the MAP decoder 110. One of them is the output of the multiplexer 114. The lower input of the multiplexer 114 is a value obtained by adding an uncoded symbol at the transmitting end encoder, and the other is the upper input of the multiplexer 116 as a parity symbol of the first convolutional encoder 2 among the received symbols.

The MAP decoder 110 receives these two values and outputs probabilistic weights. The excess information is obtained by subtracting the prior information value APP input to the current MAP decoder from the probabilistic weights.

The probabilistic weights are processed in two forms and input to the multiplexer 118. The lower input value contains the surplus information value obtained by subtracting the sum of the prior information and the received symbol from the logarithmic likelihood ratio, and the upper input value receives the dictionary information from the probabilistic weights. The subtracted value, that is, the surplus information plus the received symbol is included.

In the first MAP decoding process, the upper value is selected and output by the multiplexer 118 and interleaved in the interleaver / deinterleaver 120 to match the order of symbols applied in the next decoding.

The second MAP decoding process corresponds to the second convolutional encoder 3 of the transmitter encoder. Similarly to the decoding process described above, when the second MAP decoding is performed, there are two inputs of the MAP decoder 110, one of which is an interleaving process after adding a preliminary information and a reception symbol after the previous MAP decoding (first MAP decoding). Value), and the other is the lower input value of the multiplexer 116 as a surplus symbol of the second convolutional encoder 3 among the received symbols. The MAP decoder 110 receives these two inputs and performs decoding corresponding to the second convolutional encoder 3 to output probabilistic weights.

The MAP decoder 110 input (preliminary information plus a received symbol) is subtracted from the logarithmic likelihood ratio in order to generate surplus information to be used for subsequent decoding, and then deinterleaved and stored in the second memory 124.

Finally, in order to obtain a hard decision decoding value, after deinterleaving the soft decision probabilistic weights generated after the second MAP decoding, the hard decision unit 130 is passed.

In summary, the output of the MAP decoder 110 outputs each of the stochastic weights by 2 bits, regardless of whether the first MAP decoding and the second MAP decoding are performed, and the input is received when the first MAP decoding is performed. The symbol is added to the value stored in the second memory 126, and is the value stored only in the first memory 126 when the second MAP decoding is performed.

The method of storing the MAP decoder output in the memory through some operations is that when the first MAP decoding is performed, the MAP decoder 110 is subtracted from the probabilistic weights, interleaved and stored in the first memory 126, and the second MAP decoding. When is performed, the upper input value of the multiplexer 114 in front of the MAP decoder is subtracted from the logarithmic likelihood ratio and then deinterleaved and stored in the second memory 126.

Next, the MAC decoder 110 will be described in detail with reference to FIG. 4.

4 is a diagram showing the structure of a MAP decoder according to an embodiment of the present invention.

As shown in FIG. 4, the MAP decoder 110 is a core part of the CTC decoder, and includes a forward operator and a backward operator.

The forward operator 200 includes an upper branch metric operator 210, a forward state metric operator 220, a memory 230, an upper probability weighted operator 240, and an upper surplus information generator 250. The reverse operator 300 includes a lower branch metric operator 310, a reverse state metric operator 320, a memory 330, a lower probabilistic weight calculator 340, and a lower surplus information generator 250.

The forward operation unit 200 performs calculations sequentially from the 0 th to the N th reception symbols, and the backward operation unit 300 performs the calculation in the reverse order from the N th to 0 th operations on the received symbols. Since the forward operation unit 200 and the reverse operation unit 300 have the same calculation process, only the forward operation unit 200 will be described.

Unlike the binary turbo code, the upper branch metric calculation unit 210 performs four metric operations in the CTC code, that is, the branch metric operation for “00”, “01”, “10”, or “11” in which the bit values to be decoded at the present time point are executed. Perform. The branch metric is obtained by equation (1).

here, Is a branch metric whose coding bit a is among the branches output from state s at time k, Is a surplus information value generated in the front end MAP decoder (in the CTC, four values are "00", "01", "10", and "11" by the index "a"). And Is the first received systematic symbol, where A is distorted as it passes through the noise channel. Is the second information symbol received, and A is distorted while passing through the noise channel.

And Denotes a distorted signal while passing through the noise channel, a (1) denotes the first systematic bit of the encoder output bit, and a (0) denotes the second systematic bit of the encoder output bit. C denotes a parity bit among the encoder output bits.

That is, in each branch, the sign bits (most significant bits) of the received symbol (represented by two's complement) and the encoder output bits are compared, and if they are equal to each other, 0 is taken, and if they are different, the absolute value of the corresponding received symbol is added and all of them correspond to the transition. Determined by two metric values.

The top branch metric calculation unit 210 needs two systematic symbols and one parity symbol in one metric operation, receives surplus information values generated in the previous MAP decoder, and calculates the received metric values using the received symbol values. Add it.

The forward state metric calculator 220 calculates the current state metric using the previous state metric value and the branch metric value. Then, for each of the four probability paths, "00", "01", "10", and "11", the state metric and the branch metric value are added together, and the smallest of them is set as the current state metric value. In addition, the state metric and the branch metric values for the four probability paths “00”, “01”, “10”, and “11” are added to each other and stored in the memory 230.

The upper probability weight calculator 240 determines each of the probabilistic weights using three values such as a previous state metric, a branch metric, and a current state metric. That is, the sum of the previous state metric, the branch metric, and the current metric for each of the eight paths having a probability of "00" is determined, and the minimum value of these is determined as the probability weight for "00". Probability weights for the remaining “01”, “10” and “11” are also calculated in the same way. The values thus obtained are determined as the final decoded bits when they act as inputs to the next redundant information operation unit or when hard decision is made.

The upper surplus information calculating unit 250 generates surplus information which acts as an APP value at the next iterative decoding. The surplus information is obtained by subtracting the APP value input to the current MAP decoder from the probabilistic weights and reducing the size to 1/2 again for normalization. The value thus obtained is stored in memory and used as the input for the next iterative decoding.

As described above, operations are sequentially performed from the 0th to the Nth with respect to the received symbol, and the operations are performed in the reverse order from the Nth to the 0th. By doing this, the decoding speed can be doubled. That is, in general, the CTC decoder can decode 2 bits every unit time, but as shown in FIG. Decoded values can be obtained from the upper probability weight calculator and the lower probability weight calculator, respectively, so that 4 bits can be decoded every unit time. In addition, this method does not require additional memory compared to the conventional method.

Next, a hardware configuration of the state metric calculation units 220 and 320 to be suitable for high speed operation will be described in detail with reference to FIGS. 5 to 6.

5 is a diagram illustrating a state metric operation unit having a minimum delay in a MAP decoder according to an embodiment of the present invention, and FIG. 6 is a diagram illustrating a state metric normalization unit having a minimum delay in a MAP decoder according to an embodiment of the present invention.

In FIG. 5, the state metric calculators 220 and 320 include adders 211 and 212, an AND gate 213, a combiner 214, and a multiplexer 215. The state metric calculators 220 and 320 select the smallest value among a, b, c, and d, which are the sum of the input previous state metric and the branch metric, respectively.

In the present invention, in the state metric calculation, an algorithm such as Equation 2 is used.

As such, when the same algorithm is used in Equation 2 to obtain the minimum value among a, b, c, and d, the critical path can calculate the state metric with two adders 211 and 212. Values output from the two adders 211 and 212 are output to the combiner 214 by outputting the corresponding bit through the AND gate 213. The combiner 214 combines the three input bits and outputs them to the multiplexer 215. The multiplexer 215 outputs the minimum value according to these three bit strings.

On the other hand, the 1/2 CTC code has a total of eight states, and the eight state metric values must be normalized to prevent overflow at each time point.

Accordingly, the CTC decoder according to the embodiment of the present invention configures the normalization unit through the AND gates 216 and 217 as shown in FIG. 6. To do this, use all the state metric values plus one more than the required number of bits, and after completion of the state metric operation, examine the most significant bit of each metric value so that an overflow occurs if the most significant bit of all the state metrics has a value of '1'. The most significant bit is reset to '0'. This simplifies implementation without additional adders and greatly reduces processing time.

Next, in the CTC decoder according to the embodiment of the present invention, the CTC internal interleaving algorithm is represented by Equation 3 at 802 and 16a.

In Equation 3, all processes are performed only by the addition operation. Therefore, hardware implementation according to the interleaving algorithm is easy. The structure and operation of the interleaver will be described with reference to FIG. 7.

7 is a structural diagram of an interleaver according to an embodiment of the present invention. Here, the interleaver address generation is divided into two stages as in Equation 3. 7 relates to the second of these two steps (Step 2).

As shown in FIG. 7, the interleaver 120 includes a counter 21, multiplexers 22, 26, 31, 35, adders 23, 24, 28, 29, 33, and comparators 25, 30, 34. And D flip-flops 27 and 32.

First, the counter 21 is counted up to 1/2 of the code block size (N-1) in increments of 0 to 1. The multiplexer 22 receives the least significant two bits of the counter value as a control value and outputs a constant value const. The operation of the interleaver performs the operation of part B of Equation 3.

Then, it is input to the D flip-flop 27 through the adders 23 and 24, the comparator 25, and the multiplexer 26 to perform a modulo operation with N for D + P ₀ . The operation of the interleaver performs the A part operation of Equation 3. That is, after subtracting N from D + P ₀ , if this value is greater than 0, '1' is generated to the comparator output. If it is small, '0' is generated, and if the output of the comparator 25 is '1', (D + P ₀ ) -N and '0' to output D + P ₀ to store in the D flip-flop 27.

Next, the output value of the D flip-flop 27 and the output value of the multiplexer 35 are received as inputs to the D flip-flop 39 through the adders 28 and 29, the comparator 30, and the multiplexer 31. Perform C part operation of Equation 3. As described above, the operation of the interleaver is the same as the operation of the interleaver for the A-part operation. However, the value input to the adder 28 is the output value of the D flip-flop 27 and the output value of the multiplexer 35, and the output value of the multiplexer 31 is Y.

Thereafter, the interleaving address is output through the adder 33, the comparator 34, and the multiplexer 35. At this time, the input value of the adder 33 is the output value of the D flip-flop 32. This operation process is also the same as the operation process for the A part operation. However, the input value of the adder 33 is the output value of the D flip-flop 32 and the output value of the multiplexer 35 is the final interleaving address.

In this way, a modulo operation is performed on the input value of the adder 28, but the input value of the adder 28 may be larger than 2 * N in some specific cases. In this case, since an error occurs in the modulo operation, in order to prevent this, in the embodiment of the present invention, the same parts 33 to 35 are continuously placed.

The above embodiments are intended to illustrate the present invention, the scope of the present invention is not limited to the embodiments, it can be modified or modified by those skilled in the art within the scope of the invention defined by the appended claims. .

According to the present invention, there is an effect that the decoding speed can be improved by configuring the forward computing unit and the reverse computing unit, respectively, and designing for high-speed processing.

1 is a diagram illustrating a general turbo encoder having a code rate of 1/2.

2 is a structural diagram of a fast CTC decoder in which four CTC decoders are arranged in parallel according to an embodiment of the present invention.

3 is a structural diagram of a CTC decoder using one MAP decoder in FIG. 2.

4 is a structural diagram of a MAP decoder in FIG. 3.

5 is a diagram illustrating a state metric calculation unit having a minimum delay in a MAP decoder according to an embodiment of the present invention.

6 is a diagram illustrating a state metric normalizer having a minimum delay in a MAP decoder according to an embodiment of the present invention.

7 is a structural diagram of an interleaver.

Claims (22)

In the CTC decoding apparatus for decoding a transmission symbol coded by a Convolutional Turbo Code (CTC) code transmitted from a transmitting end, A MAP decoder for performing operations on a forward state metric and a reverse state metric simultaneously to decode 2 bits per unit time for the symbol; A multiplexer for adjusting inputs and outputs when decoding the MAP decoder; An interleaver / deinterleaver that matches a value output from the multiplexer with a sequence of symbols applied at the next decoding; A deinterleaver for deinterleaving the calculated likelihood ratio after decoding from the MAP decoder; And And a hard determiner for estimating the final decoded bit based on a value output from the deinterleaver. The method of claim 1, The MAP decoder, The current decoded bit value for the symbol performs the forward state metric and the reverse state metric operation for four probabilities in parallel, and stores the result in each memory to perform a probabilistic weight operation from the time N / 2. A forward computing unit and a backward computing unit to perform, And the forward computing unit and the reverse computing unit have a vertically symmetrical structure. The method of claim 2, The forward operation unit, A top branch metric calculation unit configured to perform branch metrics on four probabilities of bit values to be decoded for sequentially received reception symbols; A forward state metric calculator for calculating a current state metric using a result value of the upper branch metric calculator and a previous state metric value; A first memory configured to store a state metric value calculated from the forward state metric calculator; An upper probabilistic weight calculator for calculating probabilistic weights using the previous state metric value, the branch metric value, and the current state metric value; And And an upper surplus information calculating unit generating surplus information based on the probabilistic weights output from the upper probabilistic weight calculating unit. The method of claim 3, wherein The reverse operation unit, A lower branch metric calculation unit configured to perform branch metrics on four probabilities of the bit values to be decoded for the received symbols input in the reverse order; A reverse state metric calculator for calculating a current state metric using a result value of the lower branch metric calculator and a previous state metric value; A second memory for storing a state metric value calculated from the reverse state metric calculation unit; A bottom probabilistic weight calculation unit configured to calculate probabilistic weights using the previous state metric value, the bottom branch metric value, and the current state metric value; And A lower surplus information calculating unit generating surplus information based on the probabilistic weights output from the lower probabilistic weight calculating unit; And performing the forward state metric and the reverse state metric at the same time. The method according to claim 3 or 4, The branch metric calculation unit obtains a branch metric based on the following calculation formula. here, Is a branch metric whose coding bit a is among the branches output from state s at time k, Is the surplus information value generated by the shear map decoder, Is the first information symbol received, Is the second information symbol received, Is a surplus symbol received. The method according to claim 3 or 4, The state metric calculation unit, First and second adders for outputting a minimum value by a specific operation from a sum of previous state metric values and branch metric values for the four probabilities; A combiner to which the output bits are input based on the specific operation; And And a second multiplexer for outputting a minimum value based on a value output from the combiner, a previous state metric value for the four probabilities, and a branch metric value. The method according to claim 3 or 4, The forward state metric operation unit or the reverse state metric operation unit adds the output state metric value more than the required number of bits and checks and normalizes the most significant bit of each metric value after completion of the state metric operation. The method of claim 7, wherein The forward state metric operation unit or the reverse state metric operation unit determines an overflow based on a result of checking the most significant bit of all state metrics, and if the overflow occurs, resets all the most significant bit values to a specific value. Decryption device.  The method according to claim 3 or 4, The surplus information calculating unit may reduce the size of a value obtained by subtracting an input prior probability value (APP) from the calculated probabilistic weight to 1/2. The method of claim 1, The interleaver, A counter that counts up to 1/2 of the CTC code block size while sequentially increasing; A first multiplexer receiving a least two bits of the count value as a control value and outputting a constant value; First and second adders that receive a specific value and add an operation by a specific operation; A first comparator configured to generate an output value based on a comparison result between the value output from the second adder and a reference value; A second multiplexer which receives an output value from the first comparator and an output value from the first and second adders and selects one output value; Third and fourth adders for adding the constant value and an output value from a second multiplexer; A second comparator for generating an output value based on a result of comparing the output value from the fourth adder with a reference value; And A third multiplexer which receives an output value from the second comparator and output values from the third and fourth adders and selects one output value, And the values output from the first and second multiplexers are stored in respective D flip-flops. The method of claim 10, The interleaver, A fifth adder which adds and receives a specific value by an output value and a specific operation from the third multiplexer; A third comparator configured to generate an output value based on a result of comparing the output value of the fifth adder with a reference value; And And a fourth multiplexer which receives an input / output value of the fifth adder and an output value from the third comparator and selects one output value. And the fourth multiplexer outputs an interleaving address. The method of claim 1, Further comprising a first and a second memory unit for storing the output from the MAP decoder, And a value obtained by adding a received symbol and a value stored in the second memory unit when the first decoding is performed, and a value stored in the first memory is input when performing the second decoding. The method of claim 1, The multiplexer, First and second multiplexers for adjusting the input of the MAP decoder; And A third multiplexer for adjusting the output of the MAP decoder, And the MAP decoder receives values input from the first and second multiplexers, outputs a logarithmic likelihood ratio, and a probabilistic weight output from the MAP decoder is input to the third multiplexer. The method of claim 1, A first adder for adjusting an input to a first multiplexer located in front of the MAP decoder; And And second and third adders for adjusting the probabilistic weight input to the third multiplexer. In the CTC decoding method for decoding a transmission symbol coded by a Convolutional Turbo Code (CTC) code transmitted from a transmitting end, a) multiplexing and receiving a transmission symbol encoded and received by the CTC code; b) a first demodulation step of calculating first probabilistic weights for four probabilities of bit values to be decoded for a symbol received from step a); c) a second demodulation step of receiving surplus information output from the first probabilistic weights and a value obtained by adjusting the calculated first probabilistic weights, and calculating and outputting a second probabilistic weight; And d) hard decision from the probabilistic weights output after the second decoding to determine a final decoding bit, CTC decoding method characterized in that the input and output is adjusted for each decoding step. The method of claim 15, Step b), Iii) outputting a first probabilistic weight according to the first decoding based on the symbol value received from step a); Ii) adjusting and multiplexing the output value of the first probabilistic weights to output a specific value; And Iv) interleaving and storing the specific value output from step ii). The method of claim 15, Step c) is Iii) outputting a second probabilistic weight according to the second decoding based on the symbol value received from step a); Iii) adjusting and multiplexing the output value of the second probabilistic weights to output a specific value; And Iv) interleaving and storing the specific value output from step iii). The method of claim 15, In step a), the CTC decoding method is characterized in that the input values for the first decoding and the second decoding are input differently. The method according to any one of claims 15 to 18, The probabilistic weight calculation step, A branch metric calculation step of performing a branch metric operation on four probability paths of a received symbol in sequential or reverse order, respectively; A state metric calculation step of determining a minimum value as a current state metric value by a specific operation from a value obtained by adding previous state metric values and branch metric values respectively inputted for the four probability paths for the sequentially input received symbols; A probabilistic weight calculation step of determining respective probabilistic weights using the previous state metric value, the branch metric value, and the current state metric value; And A redundant information calculating step of generating redundant information based on the probabilistic weights, Decoding two bits per unit time by simultaneously calculating the forward state metric values for the four probability paths of the received symbols sequentially input and the reverse state metric values for the four probability paths of the received symbols inputted in the reverse order. CTC decoding method characterized in that. The method of claim 19, In the state metric calculation step, Adding all the determined state metric values one more than the required number of bits; Checking the most significant bit of each metric value after completion of the state metric operation; And And resetting the values of all the most significant bits to the second value when the most significant bit of all the state metrics for the four probability paths of the received symbol has the first value. The method of claim 20, And if the most significant bit of all the state metrics has a first value, it is assumed that an overflow has occurred. The method of claim 19, wherein the step of calculating surplus information, Generating surplus information by subtracting a prior information value inputted from the calculated probabilistic weights; And And multiplying the generated surplus information value by 1/2 to normalize the generated surplus information value.