KR20050065857A - Method of manufacturing transistor for semiconductor device - Google Patents
Method of manufacturing transistor for semiconductor device Download PDFInfo
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- KR20050065857A KR20050065857A KR1020030096751A KR20030096751A KR20050065857A KR 20050065857 A KR20050065857 A KR 20050065857A KR 1020030096751 A KR1020030096751 A KR 1020030096751A KR 20030096751 A KR20030096751 A KR 20030096751A KR 20050065857 A KR20050065857 A KR 20050065857A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Abstract
본 발명은 NMOS 트랜지스터 뿐만 아니라 PMOS 트랜지스터에서도 균일한 접합 콘택 저항을 확보하여 콘택 패일을 최소화할 수 있는 반도체 소자의 트랜지스터 제조방법을 제공한다.The present invention provides a method of fabricating a transistor of a semiconductor device capable of minimizing contact fail by securing uniform junction contact resistance in PMOS transistors as well as NMOS transistors.
본 발명은 제 1 도전형 MOS 트랜지스터가 형성되는 제 1 영역과 제 2 도전형 MOS 트랜지스터가 형성되는 제 2 영역이 정의되고, 제 1 및 제 2 영역에 제 1 및 제 2 게이트가 각각 형성된 반도체 기판을 준비하는 단계; 기판 전면 상에 제 1 절연막을 증착하는 단계; 제 1 절연막 상부에 제 1 영역만 오픈시키는 제 1 마스크 패턴을 형성하는 단계; 제 1 영역에 제 1 절연막으로 이루어진 제 1 게이트 스페이서를 형성하고, 제 1 도전형 불순물을 이온주입하는 단계; 제 1 마스크 패턴을 제거하는 단계; 기판 전면 상에 제 2 절연막을 증착하는 단계; 제 2 절연막 상부에 제 2 영역만 오픈시키는 제 2 마스크 패턴을 형성하는 단계; 오픈된 제 2 영역에 제 1 및 제 2 절연막으로 이루어진 제 2 게이트 스페이서를 형성하고, 제 2 도전형 불순물을 이온주입하는 단계; 및 제 2 마스크 패턴을 제거하는 단계를 포함하는 반도체 소자의 트랜지스터 제조방법에 의해 달성될 수 있다.The present invention defines a first region in which a first conductivity type MOS transistor is formed and a second region in which a second conductivity type MOS transistor is formed, and a semiconductor substrate having first and second gates formed in the first and second regions, respectively. Preparing a; Depositing a first insulating film on the front surface of the substrate; Forming a first mask pattern on the first insulating layer to open only the first region; Forming a first gate spacer made of a first insulating film in the first region, and ion implanting a first conductivity type impurity; Removing the first mask pattern; Depositing a second insulating film on the front surface of the substrate; Forming a second mask pattern on the second insulating layer to open only the second region; Forming a second gate spacer including first and second insulating layers in the open second region, and ion implanting a second conductivity type impurity; And it may be achieved by a transistor manufacturing method of a semiconductor device comprising the step of removing the second mask pattern.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 PMOS 트랜지스터 및 NMOS 트랜지스터를 구비한 반도체 소자의 트랜지스터 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a transistor of a semiconductor device having a PMOS transistor and an NMOS transistor.
일반적으로, 디램(DRAM)과 같은 메모리 소자에서는 셀영역(cell region)에는 주로 NMOS 트랜지스터가 형성되고, 주변영역(periphery region)에는 NMOS 트랜지스터와 PMOS 트랜지스터가 모두 형성된다.In general, in a memory device such as a DRAM, an NMOS transistor is mainly formed in a cell region, and both an NMOS transistor and a PMOS transistor are formed in a peripheral region.
종래 주변영역의 트랜지스터 제조공정은 PMOS 트랜지스터 및 NMOS 트랜지스터 영역이 정의된 반도체 기판 상에 NMOS 및 PMOS 게이트를 각각 형성하고, 기판 전면 상에 스페이서용 절연막을 증착한 후, PMOS 트랜지스터 영역만을 오픈시키는 제 1 포토레지스트 패턴을 형성하여 PMOS 트랜지스터 영역에만 PMOS 게이트 스페이서 및 P＋ 접합영역을 순차적으로 형성하고 제 1 포토레지스트 패턴을 제거한 다음, NMOS 트랜지스터 영역만을 오픈시키는 제 2 포토레지스트 패턴을 형성하여 NMOS 게이트 스페이서 및 N＋ 접합영역을 형성하고 제 2 포토레지스트 패턴을 제거하는 과정으로 이루어진다.In a conventional transistor manufacturing process of a peripheral region, a first NMOS and a PMOS gate are formed on a semiconductor substrate on which a PMOS transistor and an NMOS transistor region are defined, a spacer insulating film is deposited on the entire surface of the substrate, and the first PMOS transistor region is opened. Forming a photoresist pattern to sequentially form a PMOS gate spacer and a P + junction region only in the PMOS transistor region, removing the first photoresist pattern, and then forming a second photoresist pattern that opens only the NMOS transistor region to form an NMOS gate spacer; Forming a N + junction region and removing the second photoresist pattern.
그러나, NMOS 트랜지스터 영역은 스페이서용 절연막에 의해 덮여진 상태에서 제 1 포토레지스트 패턴 제거가 이루어지고 제 2 포토레지스트 패턴 제거시에만 오픈되지만, PMOS 트랜지스터 영역은 완전히 오픈된 상태에서 제 1 및 제 2 포토레지스트 패턴의 제거가 모두 이루어지기 때문에, P＋ 접합영역에서의 손상이 N＋ 접합영역에 비해 커지게 된다. 이에 따라, 예컨대 비트라인콘택(Bit Line Contact; BLC)과의 접합 콘택 형성시 N＋ 접합영역에서는 콘택 저항이 비교적 균일하게 나타나지만, P＋ 접합영역에서는 도 1과 같이 콘택저항이 900 내지 1350 Ω까지 불균일하게 나타남으로써, 결국 콘택 패일(fail)을 증가시키게 된다.However, while the NMOS transistor region is covered by the spacer insulating film, the first photoresist pattern is removed and is opened only when the second photoresist pattern is removed, but the PMOS transistor region is completely open and the first and second photo ports are removed. Since all of the resist patterns are removed, damage in the P + junction region becomes larger than that in the N + junction region. Thus, for example, when forming a contact contact with a bit line contact (BLC), the contact resistance is relatively uniform in the N + junction region, but the contact resistance is 900 to 1350 kPa as shown in FIG. 1 in the P + junction region. By appearing non-uniformly, this leads to an increase in the contact fail.
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, NMOS 트랜지스터 뿐만 아니라 PMOS 트랜지스터에서도 균일한 접합 콘택 저항을 확보하여 콘택 패일을 최소화할 수 있는 반도체 소자의 트랜지스터 제조방법을 제공하는데 그 목적이 있다. The present invention has been proposed to solve the above problems of the prior art, and provides a transistor manufacturing method of a semiconductor device capable of minimizing contact fail by securing a uniform junction contact resistance in not only NMOS transistors but also PMOS transistors. There is a purpose.
상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 상기의 본 발명의 목적은 제 1 도전형 MOS 트랜지스터가 형성되는 제 1 영역과 제 2 도전형 MOS 트랜지스터가 형성되는 제 2 영역이 정의되고, 제 1 및 제 2 영역에 제 1 및 제 2 게이트가 각각 형성된 반도체 기판을 준비하는 단계; 기판 전면 상에 제 1 절연막을 증착하는 단계; 제 1 절연막 상부에 제 1 영역만 오픈시키는 제 1 마스크 패턴을 형성하는 단계; 제 1 영역에 제 1 절연막으로 이루어진 제 1 게이트 스페이서를 형성하고, 제 1 도전형 불순물을 이온주입하는 단계; 제 1 마스크 패턴을 제거하는 단계; 기판 전면 상에 제 2 절연막을 증착하는 단계; 제 2 절연막 상부에 제 2 영역만 오픈시키는 제 2 마스크 패턴을 형성하는 단계; 오픈된 제 2 영역에 제 1 및 제 2 절연막으로 이루어진 제 2 게이트 스페이서를 형성하고, 제 2 도전형 불순물을 이온주입하는 단계; 및 제 2 마스크 패턴을 제거하는 단계를 포함하는 반도체 소자의 트랜지스터 제조방법에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, the above object of the present invention is defined by the first region where the first conductivity type MOS transistor is formed and the second region where the second conductivity type MOS transistor is formed. Preparing a semiconductor substrate having first and second gates formed in first and second regions, respectively; Depositing a first insulating film on the front surface of the substrate; Forming a first mask pattern on the first insulating layer to open only the first region; Forming a first gate spacer made of a first insulating film in the first region, and ion implanting a first conductivity type impurity; Removing the first mask pattern; Depositing a second insulating film on the front surface of the substrate; Forming a second mask pattern on the second insulating layer to open only the second region; Forming a second gate spacer including first and second insulating layers in the open second region, and ion implanting a second conductivity type impurity; And it may be achieved by a transistor manufacturing method of a semiconductor device comprising the step of removing the second mask pattern.
바람직하게, 제 1 절연막은 제 1 HLD 산화막, 질화막 및 제 2 HLD 산화막이 순차적으로 적층된 막으로 이루어지고, 제 2 절연막은 HLD 산화막으로 이루어진다.Preferably, the first insulating film is composed of a film in which a first HLD oxide film, a nitride film, and a second HLD oxide film are sequentially stacked, and the second insulating film is an HLD oxide film.
또한, 제 1 도전형 불순물로서 BF2, B 등을 사용하고, 제 2 도전형 불순물로서 As, P 등을 사용한다.In addition, the use of BF 2, B, etc. as a first conductivity type impurity, and the second uses the As, P or the like as a second conductivity type impurity.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
도 2a 내지 도 2f를 참조하여 본 발명의 바람직한 실시예에 따른 반도체 소자의 트랜지스터 제조방법을 설명한다.A transistor manufacturing method of a semiconductor device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 2A to 2F.
도 2a에 도시된 바와 같이, PMOS 트랜지스터가 형성되는 제 1 영역(PMOS)과 NMOS 트랜지스터가 형성되는 제 2 영역(NMOS)이 정의되고, 필드 산화막(11)에 의해 액티브 영역이 정의된 반도체 기판(10)을 준비한다. 그 다음, 제 1 및 제 2 영역(PMOS, NMOS) 상부에 게이트 절연막(미도시)이 개재된 제 1 및 제 2 게이트(12a, 12b)를 각각 형성한다. As shown in FIG. 2A, a semiconductor substrate in which a first region PMOS in which a PMOS transistor is formed and a second region NMOS in which an NMOS transistor are formed are defined, and an active region is defined by the field oxide film 11. 10) Prepare. Next, first and second gates 12a and 12b having gate insulating layers (not shown) are formed on the first and second regions PMOS and NMOS, respectively.
도 2b에 도시된 바와 같이, 제 1 및 제 2 게이트(12a, 12b)를 덮도록 기판 전면 상에 게이트 스페이서용 제 1 절연막으로서 제 1 HLD(High temperature Low Deposition) 산화막(13), 질화막(14) 및 제 2 HLD 산화막(15)을 순차적으로 증착한다. As shown in FIG. 2B, a first high temperature low deposition (HLD) oxide film 13 and a nitride film 14 as a first insulating film for a gate spacer on the entire surface of the substrate to cover the first and second gates 12a and 12b. ) And the second HLD oxide film 15 are sequentially deposited.
도 2c에 도시된 바와 같이, 포토리소그라피 공정에 의해 제 2 HLD 산화막(15) 상부에 제 1 영역(PMOS)만 오픈시키는 제 1 포토레지스트 패턴(16)을 형성한다. 그 다음, 제 1 포토레지스트 패턴(16)을 마스크로하여 오픈된 제 1 영역(PMOS)의 제 2 HLD 산화막(15), 질화막(14) 및 제 1 HLD 산화막(13)을 식각하여 제 1 게이트(12a) 측벽에 제 1 게이트 스페이서(100a)를 형성하고, 기판(10)으로 P＋ 불순물, 바람직하게 BF2, B 등을 이온주입(17)하여 제 1 게이트(12a)를 도핑시킴과 동시에 기판(10) 표면에 P＋ 접합영역(미도시)을 형성한다.As shown in FIG. 2C, a first photoresist pattern 16 is formed on the second HLD oxide layer 15 to open only the first region PMOS by a photolithography process. Next, the second HLD oxide film 15, the nitride film 14, and the first HLD oxide film 13 in the first region PMOS opened using the first photoresist pattern 16 as a mask are etched to form a first gate. (12a) The first gate spacer 100a is formed on the sidewall, and the substrate 10 is ion implanted with P + impurities, preferably BF 2 , B or the like, to dope the first gate 12a and at the same time P + junction regions (not shown) are formed on the substrate 10 surface.
도 2d에 도시된 바와 같이, 공지된 방법에 의해 제 1 포토레지스트 패턴(16)을 제거한다. 이때, 제 2 영역(NMOS)의 제 2 HLD 산화막(15), 질화막(14) 및 제 1 HLD 산화막(13)이 배리어(barrier)로서 작용하기 때문에 기판 손상이 발생되지 않는다. 그 후, 기판 전체 표면에 스페이서용 제 2 절연막으로서 제 3 HLD 산화막(18)을 비교적 얇은 두께로 증착한다. As shown in Fig. 2D, the first photoresist pattern 16 is removed by a known method. At this time, since the second HLD oxide film 15, the nitride film 14, and the first HLD oxide film 13 in the second region NMOS act as a barrier, no substrate damage occurs. Thereafter, the third HLD oxide film 18 is deposited to a relatively thin thickness on the entire surface of the substrate as the second insulating film for the spacer.
도 2e에 도시된 바와 같이, 포토리소그라피 공정에 의해 제 3 HLD 산화막(18) 상부에 제 2 영역(NMOS)만 오픈시키는 제 2 포토레지스트 패턴(19)을 형성한다. 그 다음, 제 2 포토레지스트 패턴(19)을 마스크로하여 오프된 제 2 영역(NMOS)의 제 3 HLD 산화막(18), 제 2 HLD 산화막(15), 질화막(14) 및 제 1 HLD 산화막(13)을 식각하여 제 2 게이트(12b) 측벽에 제 2 게이트 스페이서(100b)를 형성하고, 기판(10)으로 N＋ 불순물, 바람직하게 As, P 등을 이온주입(20)하여 제 2 게이트(12b)를 도핑시킴과 동시에 기판(10) 표면에 N＋ 접합영역(미도시)을 형성한다.As shown in FIG. 2E, a second photoresist pattern 19 is formed on the third HLD oxide layer 18 to open only the second region NMOS by a photolithography process. Next, the third HLD oxide film 18, the second HLD oxide film 15, the nitride film 14, and the first HLD oxide film of the second region NMOS off using the second photoresist pattern 19 as a mask. 13 is etched to form a second gate spacer 100b on the sidewall of the second gate 12b, and ion implantation 20 of N + impurities, preferably As and P, into the substrate 10 to form the second gate ( At the same time as doping 12b), an N + junction region (not shown) is formed on the surface of the substrate 10.
도 2f에 도시된 바와 같이, 공지된 방법에 의해 제 2 포토레지스트 패턴(19)을 제거한다. 이때, 제 1 영역(PMOS)의 제 3 HLD 산화막(18)이 배리어로서 작용하기 때문에 P＋ 접합영역의 손상이 발생되지 않는다.As shown in Fig. 2F, the second photoresist pattern 19 is removed by a known method. At this time, since the third HLD oxide film 18 of the first region PMOS acts as a barrier, damage to the P + junction region does not occur.
상기 실시예에 의하면, NMOS 트랜지스터 영역을 오픈시키는 포토레지스트 패턴을 형성하기 전에 비교적 얇은 두께로 스페이서 절연막을 더 형성하여 포토레지스트 패턴 제거시 PMOS 트랜지스터 영역을 보호하는 배리어로서 작용하도록 함으로써, PMOS 트랜지스터 영역의 P＋ 접합영역 손상을 최소화할 수 있게 된다.According to the above embodiment, before forming the photoresist pattern for opening the NMOS transistor region, a spacer insulating film is formed to a relatively thin thickness so as to act as a barrier to protect the PMOS transistor region when the photoresist pattern is removed. P + junction area damage can be minimized.
이에 따라, 이후 BLC와의 접합 콘택 형성시, N＋ 접합영역과 마찬가지로 P＋ 접합영역에서도 균일한 콘택 저항을 얻을 수 있으므로, 패일을 감소시킬 수 있게 된다.As a result, when forming a junction contact with the BLC, a uniform contact resistance can be obtained in the P + junction region as in the N + junction region, thereby reducing the fail.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
전술한 본 발명은 NMOS 트랜지스터 뿐만 아니라 PMOS 트랜지스터에서도 균일한 접합 콘택 저항을 확보하여 콘택 패일을 최소화할 수 있으므로, 트랜지스터의 특성 및 신뢰성을 향상시킬 수 있다.As described above, in the PMOS transistor as well as the NMOS transistor, the present invention can secure a uniform contact contact resistance, thereby minimizing the contact fail, thereby improving the characteristics and reliability of the transistor.
도 1은 종래의 PMOS 트랜지스터의 접합 콘택저항을 나타낸 도면.1 illustrates a junction contact resistance of a conventional PMOS transistor.
도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자의 트랜지스터 제조방법을 설명하기 위한 단면도.2A to 2F are cross-sectional views illustrating a method of manufacturing a transistor in a semiconductor device according to an embodiment of the present invention.
※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing
10 : 반도체 기판 11 : 필드 산화막10 semiconductor substrate 11 field oxide film
12a, 12b : 제 1 및 제 2 게이트12a, 12b: first and second gates
13, 15, 18 : HLD 산화막 14 : 질화막13, 15, and 18: HLD oxide film 14: nitride film
16, 19 : 제 1 및 제 2 포토레지스트 패턴16, 19: first and second photoresist pattern
17, 20 : 이온주입 17, 20: ion implantation
100a, 100b : 제 1 및 제 2 게이트 스페이서100a and 100b: first and second gate spacers
PMOS : PMOS 트랜지스터 영역PMOS: PMOS transistor region
NMOS : NMOS 트랜지스터 영역 NMOS: NMOS transistor area
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100772890B1 (en) * | 2006-05-03 | 2007-11-05 | 삼성전자주식회사 | Method of fabricating semiconductor integrated circuit device and semiconductor integrated circuit device by the same |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100772890B1 (en) * | 2006-05-03 | 2007-11-05 | 삼성전자주식회사 | Method of fabricating semiconductor integrated circuit device and semiconductor integrated circuit device by the same |
| US7618868B2 (en) | 2006-05-03 | 2009-11-17 | Samsung Electronics Co., Ltd. | Method of manufacturing field effect transistors using sacrificial blocking layers |
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