KR20050065122A - 10gigabit ethernet line interface board using frame multiplexing/demulmtiplexing device - Google Patents

Abstract

A 10 Gigabit Ethernet Line Interface Board is disclosed. The 10 Gigabit Ethernet line interface board of the present invention multiplexes a 10-port 1 Gigabit Ethernet frame received from a plurality of unit network processor means among the line interface boards of a switch and a router system into a 10-port 10 Gigabit Ethernet frame. And outputs to a plurality of unit network processor means by demultiplexing one port of 10 Gigabit Ethernet frame received from the physical layer interface means into 10 ports of 1 Gigabit Ethernet frame. .

Description

10 Gigabit ethernet line interface board using frame multiplexing / demulmtiplexing device

The present invention relates to a line interface board, and more particularly to a 10 Gigabit Ethernet line interface board.

10 Gigabit Ethernet is a high-speed local area network technology that was standardized in June 2002 by the 802.3 Ethernet group of the Institute of Electrical and Electronics Engineers. 10 Gigabit Ethernet not only improves the speed of the 1 Gbps local area network, but it is also the next generation to build a metro area network or wide area network without going through optical transmission equipment. It is a term net technology. With the advent of 1 Gigabit Ethernet, Ethernet is expanding its area from existing local area networks to metro networks. The reason is that Ethernet has already succeeded in the market, and in the process, it is much cheaper than other technologies, almost all local area networks are Ethernet, and about 95% of Internet traffic is Ethernet, metro or telecommunication network. This is because the configuration based on Ethernet also does not require protocol conversion.

10 Gigabit Ethernet aims to provide 10 times the performance at 3 to 5 times per port compared to 1 Gigabit Ethernet in current switch and router systems, but conventionally ports 10 Gigabit Ethernet line interface boards. The use of expensive 10 Gbps network processor means, which cannot support 10 Gbps throughput at 8 to 10 times per price, was very inefficient in terms of system price competitiveness.

Accordingly, the technical problem to be achieved by the present invention is a line processor means for driving a plurality of network processor means and a frame multiplexing demultiplexing means, a plurality of network processor means for supporting up to four ports of 1 Gigabit Ethernet MAC, and one of 10 ports. It provides a 10 Gigabit Ethernet interface board that supports low-cost 10 Gigabit Ethernet using a frame multiplexing demultiplexing means that multiplexes or demultiplexes Gigabit Ethernet frames into 1-port 10 Gigabit Ethernet frames.

According to the present invention, in the 10 Gigabit Ethernet line interface board of the switch and router system, receiving the 10.3125Gbps optical signal from the external network to convert to a 1-bit electrical signal and parallelized into a 16-bit signal 66B / 64B decoding 1 port of 10 Gigabit Ethernet Media Independent Interface signal group consisting of 156.25 MHz clock, 32-bit data, and 4-bit control signals extracted through -8B / 10B encoding-serialization-parallelization-10B / 8B decoding It outputs to the following frame multiplexing demultiplexing means, and on the other hand, receives a 10 Gigabit Ethernet media independent interface signal group consisting of a 156.25 MHz clock, 32-bit data, and 4-bit control signals from the following frame multiplexing demultiplexing means. / 10B Encoding-Serialization-Parallelization-10B / 8B Decoding-64B / 66B Encoding 16-Bit Signals to 1-Bit Electrical A physical layer interface means for serializing the signal and converting the signal into a 10.3125 Gbps optical signal and outputting it to an external network; Receive one port of the 10 Gigabit Ethernet media independent interface signal group consisting of 156.25 MHz clock, 32 bit data, and 4 bit control signals from the physical layer interface means and store it in the demultiplexed memory, and store it in 125 MHz clock, 8 bit data, 2 bits 1 Gigabit Ethernet Media Independent Interface (Gigabit Ethernet Media Independent Interface) signal group consisting of control signals 1:10 demultiplexed and output to the following network processor means, and 125MHz clock, 8 from the following network processor means Receives 10 ports of 1 Gigabit Ethernet Media Independent Interface signal group consisting of bit data and 2-bit control signals, stores them in multiplexed memory, and stores them in multiplexed memory. 10 Gigabit Ethernet Media Independent Interface consists of 156.25 MHz clock, 32-bit data, and 4-bit control signals. 10: 1 multiplexing to 1 port of signal group Frame multiplexing demultiplexing means for outputting to the face means; From the frame multiplexing demultiplexing means, a 1 Gigabit Ethernet medium independent interface signal group consisting of a 125 MHz clock, 8 bit data, and 2 bit control signals is received, the Ethernet frame is extracted, and the frame is extracted with the following line processor means. A switch fabric interface consisting of 500 Mbps, 8-bit differential signals that performs traffic management such as analysis, classification, lookup and forwarding, network processing and modification, polishing, and queuing for Layer 2/3/4 switching and routing. Data-Aligned Synchronous Link) is configured to duplicate the output to the switch fabric board in the system and reconfigure to the switch fabric interface.The switch fabric interface consists of 500Mbps, 8-bit differential signals from the redundant switch fabric board in the system. Receives signal family and encapsulates into Ethernet frame A 1 Gigabit Ethernet media independent interface signal group composed of a 125 MHz clock, 8 bit data, and 2 bit control signals is output to the frame multiplexing demultiplexing means, and the 33 MHz clock, 32 bit data, Guide frame handler, guide table handler and application code for initializing and operating the unit network processor means through the peripheral component interconnect interface group composed of control signals. Network processor means for downloading in a guide frame format together with a (Guide Command), performing a memory management function, and setting a unique application data structure such as a free list, a tree, a counter, and a table; And inter-processor communication with the redundant main processor boards in the system to exchange management information for 10 Gigabit Ethernet line interface boards, initialize board addresses at boot time, and download diagnostic software After performing a board test, initializing the dispatcher port configuration table, enabling hardware and timer interrupts, guide frame handlers, guide table handlers, and application picocodes for initializing and operating the above network processor means along with the guide instructions. Download in guide frame format and perform memory management to update unique application data structures such as free lists, trees, counters, and tables, and to manage other devices on board Characterized in that consisting of the end is achieved by the 10 Gigabit Ethernet line interface board.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a functional block diagram schematically illustrating the present invention, in which 1 is a physical layer interface means, 2 is a frame multiplexing demultiplexing means, 3 is a network processor means, 4 is a line processor means, and 31, 32, and 33 are each The first, second and third unit network processor means are shown, respectively.

In FIG. 1, the physical layer interface means 1 receives a 10.3125 Gbps optical signal from an external network through an optical fiber (850/1310/1550 nm Optical Fiber), converts it into a 1-bit electrical signal, parallelizes it into a 16-bit signal, and 66B / 64B decoding. Gigabit Ethernet Media Independent Interface consisting of 156.25 MHz clock, 32-bit data, and 4-bit control signals extracted from 8B / 10B encoded-serialized-parallel-10B / 8B decoded for physical expansion of the interface. A signal group 1 port is output to the following frame multiplexing demultiplexing means (2), and 10 Gigabit Ethernet media independence composed of a 156.25 MHz clock, 32-bit data, and 4-bit control signals from the frame multiplexing demultiplexing means (2). Receives 1 port of the interface signal group, performs 8B / 10B encoding-serialization-parallelization-10B / 8B decoding, and encodes 64B / 66B to 1-bit 16-bit signal Serialized into an electrical signal and converted into 10.3125Gbps optical signal and outputs to the external network.

At this time, an external device composed of a serial management interface signal group consisting of a 2.5 MHz clock and 1 bit data among the functions of the physical interface means and a 26 MHz clock, 32 bit data, and a control signal of the following line processor means 4 External Peripheral Interface A function of bridging or matching a group of signals to provide internal management information to the line processor means is implemented using a Field Programmable Gate Array.

The frame multiplexing demultiplexing means (2) receives one port of the 10 Gigabit Ethernet media independent interface signal group consisting of 156.25 MHz, 32-bit data, and 4-bit control signals from the physical layer interface means (1) and stores it in the demultiplexing memory. The 10 Gigabit Ethernet Media Independent Interface (Gigabit Ethernet Media Independent Interface) signal group consisting of a 125 MHz clock, 8-bit data, and 2-bit control signals is demultiplexed 1:10 into 10 ports and the following first unit network processor means 31 3, 4, and 3 ports are distributed to the second unit network processor unit 32 and the third unit network processor unit 33, respectively, and conversely, the first unit network processor unit 31 and the second unit network are output. 1 Gigabit Ethernet composed of a 125 MHz clock, 8-bit data, 2-bit control signal from processor means 32, third network processor means 33 Physical port interface means by receiving 10 ports of independent channel signal group and storing them in multiplexed memory and multiplexing 10: 1 to 1 port of 10 Gigabit Ethernet media independent interface signal group consisting of 156.25 MHz clock, 32-bit data, and 4-bit control signals Output to (1).

In this case, the 1 Gigabit Ethernet media independent interface signal group received from the network processor means 3 is sequentially stored in 10 multiplexed memories according to the 2-bit control signal indicating the start and end of the frame, and the frames are stored in the order in which the storage is completed. The 10 Gigabit Ethernet media independent interface signal group, which is converted to the Gigabit Ethernet media independent interface signal group and output to the physical layer interface means 1, and conversely received from the physical layer interface means 1, has 10 demultiplexed signals according to the 4-bit control signal. The data is sequentially stored in the memory and converted into a 1 Gigabit Ethernet media independent interface signal group in the order in which the frame storage is completed and output to the unit network processor means 31, 32, and 33 of the corresponding port.

 In addition, the 8-bit data of the 1 Gigabit Ethernet media independent interface signal group x8 = 64-bit data of the 10 Gigabit Ethernet media independent interface signal family, so that the Gigabit Ethernet media independent signal family is 64-bit data and 8-bit control every 8 cycles of the 125 MHz clock. The signal and the 1-bit frame end signal are converted into a 10 Gigabit Ethernet media independent signal group to compensate for the speed between the Gigabit Ethernet Media Independent Interface signal group and the 10 Gigabit Ethernet Media Independent signal group. The frame multiplexing demultiplexing means is implemented using a field programmable gate array in consideration of low development cost, ease of design, and short development time.

The network processor means 3 is composed of a first unit network processor means 31, a second unit network processor means 32, a third unit network processor means 33, and each unit network processor means 31, 32, 33) receives up to four ports of the 1 Gigabit Ethernet media independent interface signal group consisting of a 125 MHz clock, 8-bit data, and 2-bit control signals from the frame multiplexing demultiplexing means 2, and extracts Ethernet frames. Performs traffic management such as network processing and modification, polishing, queuing, etc. for analysis, classification, lookup, and forwarding for layer 2/3/4 switching and routing on the extracted frames with the line processor means 4 of Switches inside the system by reconfiguring into a family of data-aligned synchronous links signals consisting of 8-bit differential signals It performs the function of redundancy to the fabric board, and receives the switch fabric interface signal group consisting of 500 Mbps, 8-bit differential signal from the redundant switch fabric board inside the system, encapsulates the Ethernet frame, and encapsulates the Ethernet frame. A 1 Gigabit Ethernet medium independent interface signal group consisting of 8-bit data and 2-bit control signals is output to the frame multiplexing demultiplexing means 2 described above.

The network processor means (3) is a unit network processor means (31, 32, 33) through a peripheral component interconnect (PSI) interface signal group consisting of 33 MHz clock, 32-bit data, control signals of the line processor means 4 described below. Guide Frame Handler, Guide Table Handler, and Application Code are downloaded in the Guide Frame format along with the Guide Command for initialization and operation. Perform memory management and set up your own application data structures such as free lists, trees, counters, and tables.

The unit network processor is implemented in the form of a daughter board (Daughter Board) in consideration of implementation, scalability and testability.

The line processor means (4) performs inter-processor communication with the redundant main processor board in the system to exchange management information of the 10 Gigabit Ethernet line interface board, and EIA-232c 1 for an external console. Port, supports 10/100 Mbps Ethernet, initializes board address at board boot from external server, downloads diagnostic software to perform self-board test, initializes dispatcher port configuration table, enables hardware and timer interrupt Thereafter, each unit network processor (31, 32, 33) in the network processor means (3) is initialized and operated through the PEI interface signal group consisting of a 33 MHz clock, 32 data, and a control signal. Guide frame handlers, guide table handlers, and applications Download the pico code guide frame format with a guide, and instructions, to perform the memory management function to update the data structure of the specific application, such as a free list, the tree, and the counter table.

The line processor means also manages other devices on the board through an External Peripheral Interface signal group consisting of a 26 MHz clock, 32 bits of data and control signals. The line processor means is implemented in the form of a daughter board in consideration of the implementability, scalability and testability.

The invention can also be embodied as computer readable code on a computer readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage, and the like, and may also be implemented in the form of a carrier wave (for example, transmission over the Internet). Include. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

So far I looked at the center of the preferred embodiment for the present invention. Those skilled in the art will appreciate that the present invention can be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in descriptive sense only and not for purposes of limitation. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope will be construed as being included in the present invention.

As described above, according to the present invention, the following effects are obtained.

First, by using the frame multiplexing demultiplexing means developed through the Field Programmable Gate Array, the cost per 10 Gigabit Ethernet port can be lowered along with low development cost, ease of design, and short development time.

Second, by implementing the main parts such as unit network processor means and line processor means that handles up to 4 ports of 1 Gigabit Ethernet in the form of daughter boards, the number of board stacks is reduced to improve implementation and testability, and system cost is reduced. Can be lowered.

Third, the implementation in the form of daughter boards enables the common use and parallel development of the main parts of the board, thereby shortening the system development schedule and facilitating system operation in the event of a failure.

Fourth, the line processor means can manage the operation of up to three unit network processor means to increase the integration degree of the system and lower the system cost.

1 is a block diagram of a 10 Gigabit Ethernet line interface board using frame multiplexing demultiplexing means according to the present invention.

Claims (6)

A 10 Gigabit Ethernet line interface board for switch and router systems, Receives 10.3125 Gbps optical signals from external networks, converts them into 1-bit electrical signals, parallelizes them into 16-bit signals, and extracts them via 66B / 64B decoding-8B / 10B encoding-serialization-parallelization-10B / 8B decoding and 32-bit One port of the 10 Gigabit Ethernet Media Independent Interface signal group consisting of data and 4-bit control signals is output to the following frame multiplexing demultiplexing means, and 156.25 MHz from the following frame multiplexing demultiplexing means. Receives one port of the 10 Gigabit Ethernet Media Independent Interface Signal Family, consisting of clock, 32-bit data, and 4-bit control signals, and encodes 16-bit signals by 8B / 10B Encoding-Serialization-Parallelization-10B / 8B Decoding-64B / 66B. A physical layer interface means for serializing a bit electrical signal, converting the optical signal into a 10.3125 Gbps optical signal, and outputting the optical signal to an external network; Receive one port of the 10 Gigabit Ethernet media independent interface signal group consisting of 156.25 MHz clock, 32 bit data, and 4 bit control signals from the physical layer interface means and store it in the demultiplexed memory, and store it in 125 MHz clock, 8 bit data, 2 bits 1 Gigabit Ethernet Media Independent Interface (Gigabit Ethernet Media Independent Interface) signal group consisting of control signals 1:10 demultiplexed and output to the following network processor means, and 125MHz clock, 8 from the following network processor means Receives 10 ports of 1 Gigabit Ethernet Media Independent Interface signal group consisting of bit data and 2-bit control signals, stores them in multiplexed memory, and stores them in multiplexed memory. 10 Gigabit Ethernet Media Independent Interface consists of 156.25 MHz clock, 32-bit data, and 4-bit control signals. 10: 1 multiplexing to 1 port of signal group Frame multiplexing demultiplexing means for outputting a face means; From the frame multiplexing demultiplexing means, a 1 Gigabit Ethernet medium independent interface signal group consisting of a 125 MHz clock, 8 bit data, and 2 bit control signals is received, the Ethernet frame is extracted, and the frame is extracted with the following line processor means. A switch fabric interface consisting of 500 Mbps, 8-bit differential signals that performs traffic management such as analysis, classification, lookup and forwarding, network processing and modification, polishing, and queuing for Layer 2/3/4 switching and routing. Data-Aligned Synchronous Link) is configured to duplicate the output to the switch fabric board in the system and reconfigure to the switch fabric interface.The switch fabric interface consists of 500Mbps, 8-bit differential signals from the redundant switch fabric board in the system. Receives signal family and encapsulates into Ethernet frame A 1 Gigabit Ethernet media independent interface signal group composed of a 125 MHz clock, 8 bit data, and 2 bit control signals is output to the frame multiplexing demultiplexing means, and the 33 MHz clock, 32 bit data, Guide frame handler, guide table handler and application code for initializing and operating the unit network processor means through the peripheral component interconnect interface group composed of control signals. Network processor means for downloading in a guide frame format together with a (Guide Command), performing a memory management function, and setting a unique application data structure such as a free list, a tree, a counter, and a table; And Performs inter-processor communication with redundant main processor boards inside the system to exchange management information for 10 Gigabit Ethernet line interface boards, initialize board addresses at boot time, and download diagnostic software Perform a test, initialize the dispatcher port configuration table, enable hardware and timer interrupts, and guide the guide frame handlers, guide table handlers, and application picocodes with guide instructions to initialize and operate the network processor means. Line processor means to download in frame format, perform memory management functions to update unique application data structures such as free lists, trees, counters, and tables, and manage other elements on board 10 Gigabit Ethernet line interface board, characterized in that consisting of. The method of claim 1, wherein the physical layer interface means Field programmable gates for bridging or matching a 2.5 MHz serial management interface signal with a 26 MHz External Peripheral Interface signal of the line processor means to provide internal management information to the line processor means. 10 Gigabit Ethernet line interface board, characterized in that implemented in the form of an array (Field Programmable Gate Array). The apparatus of claim 1, wherein the frame multiplexing demultiplexing means Multiplexing or demultiplexing a 10-port Gigabit Ethernet frame into a 1-port 10 Gigabit Ethernet frame and compensating for the speed between two interface signal groups in a form of a Programmable Gate Array Gigabit Ethernet Line Interface Board. The method of claim 1, wherein the network processor means A first unit network processor means, a second unit network processor means, and a third unit network processor means, wherein all the unit network processor means correspond to the frame multiplexing demultiplexing means of claim 3, wherein the unit network processor means comprises a daughter board ( 10 Gigabit Ethernet line interface board, characterized in that implemented in the form of Daughter Board). The method of claim 1, wherein the line processor means Inter-Processor Communication via 2 ports of 10 / 100Mbps Ethernet, support EIA-232c, 1 port of 10 / 100Mbps Ethernet for external console, external server or internal via 10 / 100Mbps Ethernet A 10 Gigabit Ethernet line interface board that boots from the memory boot image. The method of claim 1, wherein the line processor means Manages the initialization and operation of up to three unit network processor means in the network processor means, and includes a Peripheral Component Interconnect comprising 33 MHz clock, 32 bit data, and control signals for communication between the network processor means and the line processor means. 10 Gigabit Ethernet line interface board, characterized in that the interface signal group.