KR20050064005A - A array substrate for lcd and the method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device having a built-in heater so as to be driven at a low temperature, and a manufacturing method thereof.

In the array substrate of a top gate type polycrystalline silicon liquid crystal display device using a high brightness backlight, a metal layer used as a light shield layer is extended to a lower layer of a wiring and a thin film transistor to be used as a heat generating layer. This improves image quality defects caused by light leakage and improves product reliability by enabling operation in cryogenic environments.

Description

Array substrate for LCD and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device having a built-in heater so as to be driven at a low temperature, and a manufacturing method thereof.

Recently, with the rapid development of the information society, there is a need for a flat panel display having excellent characteristics such as thinning, light weight, and low power consumption. Among them, a liquid crystal display having excellent color reproducibility, etc. displays are actively being developed.

In general, a liquid crystal display device is formed by arranging two substrates having electrodes formed on one surface thereof so that the surfaces on which the two electrodes are formed face each other, injecting a liquid crystal material between the two substrates, and then applying a voltage to the two electrodes. By moving the liquid crystal molecules by an electric field, the device expresses an image by the transmittance of light that varies accordingly.

Liquid crystal displays may be formed in various forms. Currently, an active matrix LCD (AM-LCD) having a thin film transistor and pixel electrodes connected to the thin film transistors arranged in a matrix manner has excellent resolution and video performance. It is most noticed.

The liquid crystal display has a structure in which a pixel electrode is formed on a lower array substrate and a common electrode is formed on a color filter substrate, which is an upper substrate, and drives liquid crystal molecules by an electric field in a direction perpendicular to an up and down substrate. to be. This is excellent in characteristics such as transmittance and aperture ratio, and the common electrode of the upper plate serves as a ground, thereby preventing the destruction of the liquid crystal cell due to static electricity.

In general, amorphous silicon (a-Si: H) is mainly used for active layers used in thin film transistors. This is because a large area is easy to manufacture, high productivity, and can be deposited at a low substrate temperature of 350 ° C. or lower, so that an inexpensive insulating substrate can be used.

However, because hydrogenated amorphous silicon has a disordered atomic arrangement, weak Si-Si bonds and dangling bonds exist, and thus, the Si-Si is changed into a quasi-stable state when irradiated with light or applied with an electric field to be used as a thin film transistor device. Stability is a problem.

In particular, the amorphous silicon has a problem of deterioration in characteristics due to light irradiation, and writes in a driving circuit due to electrical characteristics (low field effect mobility: 0.1 to 1.0 cm 2 / V · s) and reliability of the display pixel driving element. it's difficult.

In addition, when the resolution of the liquid crystal panel for a liquid crystal display device is increased, the pad pitch outside the substrate connecting the gate wiring and the data wiring of the thin film transistor substrate with the TCP becomes short, and the TCP bonding itself becomes difficult.

However, since polycrystalline silicon has a greater field effect mobility than amorphous silicon, a driving circuit can be made on a substrate. If the driving circuit is directly made on the substrate, the IC cost can be reduced and the mounting can be simplified.

In addition, since the polycrystalline silicon has a field effect mobility of about 100 to 200 times greater than that of amorphous silicon, the response speed is fast and the stability to temperature and light is excellent. In addition, there is an advantage that the driving circuit can be formed on the same substrate.

When the polycrystalline liquid crystal display device configured as described above is driven at cryogenic temperatures, the image quality is poor because it is out of the driving range of the liquid crystal.

As described above, a transparent electrode is formed on the entire surface of the substrate as a built-in heater so as to be driven at a low temperature.

1 is a schematic cross-sectional view of a liquid crystal display device having a conventional built-in heater.

As shown in FIG. 1, the liquid crystal 133 is formed between the upper plate 150 and the lower plate 100, and a heating layer 110 is formed on the lower plate 100 using a transparent conductive electrode. .

The transparent conductive electrode may include indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), and the like.

In addition, a buffer layer 111 having excellent thermal conductivity is formed on the heat generating layer 110, and a TFT array 120 is sequentially formed on the buffer layer 111.

As such, the heat generating layer 110 formed on the lowermost layer on the lower plate 100 is made of a transparent conductive electrode, and when current is applied from the outside, current flows to the transparent conductive electrode to generate heat.

However, in the case of a polycrystalline silicon liquid crystal display device, a high temperature process is essential in the process of forming a thin film transistor array like a crystallization process.

The transparent conductive electrode pre-formed with the heat generating layer has a problem in that damage occurs in a high temperature crystallization process which is performed in a subsequent process.

The present invention provides an array substrate for a liquid crystal display device capable of improving image quality defect due to light leakage and driving in a cryogenic environment by using a light shield layer as a heat generating layer in a polycrystalline silicon liquid crystal display device using a high brightness backlight and its It is an object to provide a manufacturing method.

In order to achieve the above object, an array substrate for a liquid crystal display device according to the present invention comprises: an array having a gate wiring, a data wiring, and a polycrystalline silicon thin film transistor formed at the crossing points, crossing each other horizontally and horizontally on the substrate to define pixels; The substrate may include a heating layer under the gate wiring, the data wiring and the thin film transistor.

The polycrystalline silicon thin film transistor includes: a buffer layer formed on the substrate;

An active layer made of polycrystalline silicon on the buffer layer and doped with impurities on both sides to form source and drain regions; A gate insulating film formed over the active layer; A gate wiring and a gate electrode formed on the gate insulating film; An interlayer insulating layer covering the gate electrode and having first and second contact holes respectively exposing the source and drain regions; A source electrode extending from the data line in contact with the source region through the first contact hole on the interlayer insulating layer, and a drain electrode in contact with the drain region through the second contact hole; A protective layer covering the source electrode and the drain electrode and forming a drain contact hole; And a pixel electrode formed on the passivation layer and connected to the drain electrode through the drain contact hole.

The heat generating layer is characterized in that the metal material.

The heat generating layer is characterized in that it is smaller than the line width of the metal wiring.

The heating layer formed under the thin film transistor and the heating layer formed under the gate and the data line may be separated.

The heat generating layer is formed under the buffer layer.

The buffer layer is characterized in that excellent thermal conductivity.

In addition, in order to achieve the above object, a method of manufacturing an array substrate for a liquid crystal display device according to the present invention includes a gate wiring, a data wiring, and a polycrystalline silicon formed at the intersection with a gate wiring and a data wiring crossing the substrate horizontally and horizontally to define a pixel. In an array substrate having a thin film transistor, forming a heating layer prior to forming the polycrystalline silicon thin film transistor.

The method may further include forming a buffer layer having excellent thermal conductivity on the heat generating layer.

The heat generating layer is formed under the gate wiring, the data wiring and the thin film transistor.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a schematic plan view of an array substrate including a top gate polycrystalline silicon thin film transistor according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view taken along line AA ′ of FIG. 2. It is a cross section.

As shown in FIG. 2, a plurality of gate lines 211 arranged in parallel on a transparent substrate and a plurality of parallel data lines 212 perpendicular to each other form a matrix and define a pixel area. A thin film transistor including a semiconductor layer 216, a gate electrode 220, a source electrode and a drain electrode 226 and 228 at an intersection point of the two wires, and a pixel electrode 234 electrically connected to the thin film transistor. This is located.

A heating layer 260 is formed on the gate wiring 211, the data wiring 212, and the gate electrode 220.

In this case, the semiconductor layer 216 is electrically connected to the source and drain electrodes 226 and 228 by first and second contact holes 222a and 222b, and the drain electrode by the second contact hole 222a. The 228 and the pixel electrode 234 are electrically connected to each other.

Here, the semiconductor layer 216 is made of polycrystalline silicon (p-si) that is coated on the substrate with amorphous silicon (a-si) and then polycrystallized by laser annealing or the like.

3 is a cross-sectional view taken along line AA ′ of FIG. 2 and schematically illustrates a portion of a pixel area of an array substrate having a top gate thin film transistor according to the present invention.

As shown in FIG. 3, when a cross section is taken along the line A-A 'of FIG. 2, a heating layer 260 is formed on the transparent substrate 200.

The heat generating layer 260 is formed under the gate line 211 and the data line 212 and is formed in the channel region under the semiconductor layer 216.

In this case, the heating layer 260 formed under the gate electrode 220 serves as a light shield layer that prevents light leakage due to the high brightness backlight.

A buffer layer 214 having excellent thermal conductivity is formed on the heat generating layer 260 over the entire substrate, and a semiconductor layer 216 is formed on the buffer layer 214.

A gate insulating layer 218 including first and second contact holes 222a and 222b is formed on the semiconductor layer 216, and a gate electrode 220 is formed in the center of the semiconductor layer 216 on the gate insulating layer 218. ) Is formed.

Using the gate electrode 220 as a mask, a highly doped source region and a drain region are formed in the semiconductor layer 216.

In addition, an interlayer insulating layer 224 including first and second contact holes 222a and 222b exposing the source and drain regions is formed on the gate electrode 220, and the first and second contacts are formed. Source and drain electrodes 226 and 228 connected to the holes 222a and 222b, respectively, are formed to be spaced apart from each other by a predetermined interval.

In addition, a passivation layer 232 including a second contact hole 222a exposing the drain electrode 228 is formed on the source and drain electrodes 226 and 228, and above the passivation layer 232. The pixel electrode 234 connected to the drain electrode 228 through the second contact hole 222a is formed.

Here, the heat generating layer 260 is made of a metal material, and the heat generating layer 260 formed under the gate wiring 211 and the data wiring 212 has a heat generating layer formed in the channel region ( Separated from the 260, the heat generating layer 260 formed under the channel region also serves as a light blocking layer for blocking light leakage.

In addition, since the heat generating layer 260 formed under the gate wiring 211 and the data wiring 212 is formed with a line width smaller than the width of the gate wiring 211 and the data wiring 212, the opening ratio affects the opening ratio. In addition, no damage occurs to the heat generating layer 260 even in a high temperature environment such as a subsequent crystallization process.

In addition, since the metal layer is not formed in the opening of the heating layer 260 having the above structure, there is no decrease in transmittance.

In the liquid crystal display device configured as described above, when the heating layer is operated in an extremely low temperature environment, a current applied from the outside is applied to the heating layer so that heat is conducted to the array substrate by a buffer layer having excellent thermal conductivity. Even in this case, the liquid crystal is driven well.

4 is a schematic plan view of an array substrate including a top gate polycrystalline silicon thin film transistor according to another embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along line BB ′ of FIG. 4. It is a cross section.

As shown in FIG. 4, a plurality of gate lines 311 arranged in parallel on a transparent substrate and a plurality of parallel data lines 312 orthogonal to each other form a matrix and define pixel regions. The thin film transistor including the semiconductor layer 316, the gate electrode 320, the source electrode and the drain electrode 326 and 328 is positioned at the intersection point of the wiring, and the pixel electrode 334 electrically connected to the thin film transistor is disposed. .

A heating layer 360 is formed under the gate wiring 311, the data wiring 312, and the thin film transistor TFT.

In this case, the semiconductor layer 316 is electrically connected to the source electrode and the drain electrodes 326 and 328 by first and second contact holes 322a and 322b, and the drain electrode by the second contact hole 322a. The 328 and the pixel electrode 334 are electrically connected to each other.

Here, the semiconductor layer 316 is made of polycrystalline silicon (p-si) that is coated on the substrate with amorphous silicon (a-si) and then polycrystallized by laser annealing or the like.

FIG. 5 is a cross-sectional view taken along line BB ′ of FIG. 4 and schematically illustrates a portion of a pixel region of an array substrate having a top gate type thin film transistor according to the present invention.

As shown in FIG. 5, when a cross section is taken along the line BB ′ of FIG. 4, a heating layer 360 is formed on the transparent substrate 300.

The heat generating layer 360 is formed under the gate line 311 and the data line 312 and is formed in a channel region under the thin film transistor.

In this case, the heat generating layer 360 formed under the thin film transistor serves as a light shield layer that prevents light leakage due to the high brightness backlight.

A buffer layer 314 having excellent thermal conductivity is formed on the heat generating layer 360 over the entire surface of the substrate, and a semiconductor layer 316 is formed on the buffer layer 314.

A gate insulating layer 318 including first and second contact holes 322a and 322b is formed on the semiconductor layer 316, and a gate electrode 320 is formed on the gate insulating layer 318 in the center of the semiconductor layer 316. ) Is formed.

Using the gate electrode 320 as a mask, a highly doped source region and a drain region are formed in the semiconductor layer 316.

In addition, an interlayer insulating layer 324 including first and second contact holes 322a and 322b exposing the source and drain regions is formed on the gate electrode 320, and the first and second contacts are formed. Source and drain electrodes 326 and 328 respectively connected to the holes 322a and 322b are formed to be spaced apart from each other by a predetermined interval.

In addition, a passivation layer 332 including a second contact hole 322a exposing the drain electrode 328 is formed on the source and drain electrodes 326 and 328, and above the passivation layer 332. The pixel electrode 334 is formed to be connected to the drain electrode 328 through the second contact hole 322a.

Here, the heat generating layer 360 is made of a metal material.

In addition, since the heating layer formed under the gate wiring 311 and the data wiring 312 has a line width smaller than the width of the gate wiring 311 and the data wiring 312, the opening ratio does not affect the opening ratio. Even in a high temperature environment such as a subsequent crystallization process, no damage occurs to the heating layer.

In addition, in the heat generating layer having the above structure, since no metallic material is formed in the opening, there is no decrease in transmittance.

In the liquid crystal display device configured as described above, when the heating layer is operated in an extremely low temperature environment, a current applied from the outside is applied to the heating layer so that heat is conducted to the array substrate by a buffer layer having excellent thermal conductivity. Even in this case, the liquid crystal is driven well.

Although the present invention has been described in detail with reference to specific examples, this is for describing the present invention in detail, and the array substrate for a liquid crystal display device and a method of manufacturing the same according to the present invention are not limited thereto, and the technical concept of the present invention is defined. It will be apparent to those skilled in the art that modifications and variations are possible.

The present invention improves image quality defects due to light leakage by forming a heat generating layer using a metal layer on a lower layer of a wiring and a thin film transistor in an array substrate of a top gate type polycrystalline silicon liquid crystal display device. It can be driven to improve the reliability of the product.

In addition, the liquid crystal display device having the built-in heater as in the present invention can use the liquid crystal display device well even in an extremely low temperature environment, thereby improving the user's use environment.

1 is a schematic cross-sectional view of a liquid crystal display device having a conventional built-in heater.

FIG. 2 is a schematic plan view of an array substrate including a polycrystalline silicon thin film transistor having a top gate structure as one embodiment according to the present invention. FIG.

3 is a cross-sectional view taken along the line AA ′ of FIG. 2.

4 is a schematic plan view of an array substrate including a polycrystalline silicon thin film transistor having a top gate structure as another embodiment according to the present invention.

5 is a cross-sectional view taken along line BB ′ of FIG. 4.

<Description of Signs of Major Parts of Drawings>

200, 300: substrate 211, 311: gate wiring

212 and 312: Data line 214 and 314: Buffer layer

216 and 316: semiconductor layers 218 and 318: gate insulating film

220 and 320: gate electrodes 222a and 222b: first and second contact holes

224, 324: interlayer insulating film 226, 326: source electrode

228 and 328 Drain electrodes 232 and 332 Protective layer

234 and 334: pixel electrodes 260 and 360: heating layer

Claims (14)

In an array substrate having a gate wiring, a data wiring, and a polycrystalline silicon thin film transistor formed at the crossing point, crossing the vertical and horizontal on the substrate to define the pixel, And a heating layer beneath the gate wiring, the data wiring and the thin film transistor. The method of claim 1, The polycrystalline silicon thin film transistor includes: a buffer layer formed on the substrate; An active layer made of polycrystalline silicon on the buffer layer and doped with impurities on both sides to form source and drain regions; A gate insulating film formed over the active layer; A gate wiring and a gate electrode formed on the gate insulating film; An interlayer insulating layer covering the gate electrode and having first and second contact holes respectively exposing the source and drain regions; A source electrode extending from the data line in contact with the source region through the first contact hole on the interlayer insulating layer, and a drain electrode in contact with the drain region through the second contact hole; A protective layer covering the source electrode and the drain electrode and forming a drain contact hole; And a pixel electrode formed on the passivation layer and connected to the drain electrode through the drain contact hole. The method of claim 1, The heat generating layer is a liquid crystal display array substrate, characterized in that the metal material. The method of claim 1, And the heat generating layer is smaller than the line width of the metal wiring. The method of claim 1, And a heat generating layer formed under the thin film transistor and a heat generating layer formed under a gate and a data line. The method according to claim 1 or 2, And the heat generating layer is formed under the buffer layer. The method of claim 2, The buffer layer is an array substrate for a liquid crystal display device, characterized in that excellent thermal conductivity. In an array substrate having a gate wiring, a data wiring, and a polycrystalline silicon thin film transistor formed at the crossing point, crossing the vertical and horizontal on the substrate to define the pixel, And forming a heating layer prior to forming the polycrystalline silicon thin film transistor. The method of claim 8, And forming a buffer layer having excellent thermal conductivity on the heat generating layer. The method of claim 8, The polycrystalline silicon thin film transistor, Forming an active layer made of polycrystalline silicon on the substrate and doped with impurities on both sides to have a source and a drain region; Forming a gate insulating film on the active layer; Forming a gate wiring and a gate electrode on the gate insulating film; Forming an interlayer insulating film covering the gate electrode and having first and second contact holes respectively exposing the source and drain regions; Forming a source electrode extending from a data line in contact with the source region through the first contact hole and a drain electrode in contact with the drain region through the second contact hole on the interlayer insulating layer; Forming a protective layer covering the source electrode and the drain electrode and forming a drain contact hole; And forming a pixel electrode formed on the passivation layer and connected to the drain electrode through the drain contact hole. The method of claim 8, The heat generating layer is formed under a gate wiring, a data wiring and a thin film transistor. The method of claim 8, And the heat generating layer is formed smaller than the line width of the gate wiring and the data wiring. The method of claim 8, The heating layer is a manufacturing method of an array substrate for a liquid crystal display device, characterized in that the metal material. The method of claim 8, And a heat generating layer formed under the thin film transistor and a heat generating layer formed under a gate and a data line are separated from each other.