KR20050063708A - Method and apparatus for reducing soft errors - Google Patents

Abstract

A method and apparatus for reducing soft errors are disclosed. In some embodiments, the method includes allocating a plurality of nodes in the storage circuit 2 to a predetermined state, evaluating the plurality of signals coupled to the storage circuit so that the first node Node_A changes from the predetermined state. To make the second node Node_B more susceptible to disturbances, and to keep the second node Node_B in a predetermined state for a predetermined time, thereby reducing the sensitivity of the storage circuit to soft errors. Steps.

Description

METHOD AND APPARATUS FOR REDUCING SOFT ERRORS}

Most users of electronic devices are accustomed to glitches, that is, events that are not random cataclysm that does not destroy electronic devices. The term "soft error" refers to glitches in a semiconductor device such as an integrated circuit, which affects the data contained in the semiconductor device. In general, soft errors can occur when ion radiation (eg, neutrons, alpha particles, and electromagnetic radiation) interacts with the atoms of the semiconductor compounds that make up the semiconductor device. In particular, the interaction of ion emission with the semiconductor generates charged particles of the semiconductor material. These charged particles are generally referred to as electron-hole pairs. Electron-hole pairs can be collected by nodes in the circuit that are particularly sensitive to the injection of electron-hole pairs. For example, integrated circuit memory devices may vary from 1 to 0 or from 0 to 1 due to the injection of electron-hole pairs. Ion radiation can be generated from radioactive material and / or cosmic ray. For example, high-energy cosmic radiation and solar particles react with the Earth's ultra-high atmosphere to generate high-energy protons that pour on the Earth's surface, affecting semiconductor devices. Another known cause of soft error is alpha particles present in the package material of the integrated circuit, ie particles emitted by the trace amount of the radioisotope. For example, flip-chip packaging technology uses lead bumps that have been found to contain alpha particles. In addition, as semiconductor devices are increasingly made smaller, the current speed at which soft errors occur will become unacceptable.

A method and apparatus for reducing soft errors are disclosed. In some embodiments, the method includes allocating a plurality of nodes in a storage circuit to a predetermined state, and evaluating a plurality of signals coupled to the storage circuit-evaluating the plurality of signals, thereby bringing the first node into a predetermined state. Can be solved and the second node can solve the problem of perturbation-and keep the second node in a predetermined state for a predetermined time-thereby reducing the sensitivity of the storage circuit to soft errors by maintaining the predetermined state. Contains-

For a more detailed description of embodiments of the present invention, reference is made to the accompanying drawings.

Specific terms are used throughout the following description, which refers to specific system components. Those skilled in the art will appreciate that computer companies call one component under a different name. The specification is not intended to distinguish between components that differ in name but not function. In the following detailed description and claims, the terms "comprising" and "constituting" are used in a variety of ways possible, and therefore, are to be construed in a sense of "including but not limited to." The term "bond" also means a direct or indirect electrical connection. Thus, when the first device is coupled to the second device, the connection may be a direct electrical connection, or an indirect electrical connection via a connection with another device. The term “charge event” refers to ion emission (eg, neutron or alpha particles) that disturbs several nodes in a circuit. The terms “active pull up” and “active pull down” refer to techniques used to directly assign high and low voltage values to nodes, respectively, using deliberate conducting paths. For example, turning on a transistor will couple the node to V _dd or ground through the transistor to actively pull up or pull down the node as opposed to passive by providing a deliberate conductive path to V _dd or ground. .

1 shows a circuit configuration 2 according to an embodiment of the present invention. The circuit configuration operates between the positive power supply V _dd and the negative power supply V _ss . In some embodiments, V _dd is a voltage of less than approximately 2 volts, and V _ss is a voltage of approximately zero. The trend in the semiconductor industry is to make transistors that operate at lower voltages smaller. However, as the operating voltage and the dimensions of the transistors decrease, circuits fabricated using such transistors become more sensitive to the adverse effects of radiation described above. In implementing integrated circuits, there is a need for techniques that reduce their sensitivity to radiation effects.

Circuit 2 represents a memory structure capable of holding data. Circuit 2 includes complementary outputs C_L and C_H. In order to understand the operation of the circuit 2, in the case where the device on the left side of the line X has a corresponding device of symmetry on the right side of the line X, it is necessary to observe the symmetry around the line X. It helps. The outputs C_L and C_H are provided by symmetrical inverters 4, 5, and NODE_A and NODE_B provide further inputs to these inverters. Using inverters 4 and 5 configured in this way, outputs C_L and C_H produce the opposite values present in NODE_A and NODE_B, respectively. (In the course of describing the operation of the circuit 2, this specification focuses on NODE_A and NODE_B and refers to the outputs C_L and C_H where necessary.) NODE_A and NODE_B are two separate states, ie V _dd. And V _ss are reached. Tail current transistor (7) is coupled and their connection to source V _ss, the transistor will be connected to all of the system to V _ss. The gate connection of transistor 7 is coupled to clock line CLK, which is described in more detail below. As described, the transistor 7 is an N-type complementary metal oxide semiconductor ("CMOS") device. In this way, upon application of a high voltage, i.e., V _dd to the gate, the transistor 7 is conductive the current or is in the "ON" state. Similarly, if transistor 7 is an N-type CMOS device as described, by applying a low voltage, i.e., V _ss, to the gate, the transistor is not conducting current, i.

The drain connection of the transistor 7 is connected to the source connection of the two symmetrical N-type CMOS transistors 13 and 14. In this way, the transistors 13, 14 form a differential input pair and their gates are coupled to the complementary signals IN_H and IN_L described. For example, when V _dd is applied to the gate of the transistor 13 and V _ss is applied to the gate of the transistor 14, the transistor 13 is turned on and the transistor 14 is turned off. When the transistor 13 is turned on, another transistor and a circuit node coupled to the transistor can obtain a voltage of V _ss .

As shown in FIG. 1, transistor 13 is coupled to NODE_A through transistor 17, the source of transistor 17 is coupled to transistor 13, and the drain of transistor 17 is coupled to NODE_A. . (It should be noted that transistor 17 is shown as an N-type CMOS element.) Also, the gate of transistor 17 is coupled to NODE_B as shown. Thus, when NODE_B is set to a voltage of V _dd , transistor 17 is in the ON state and couples NODE_A to transistor 13. Similarly, transistor 14 is coupled to NODE_B through transistor 21 (which is an N-type CMOS device), the source of transistor 21 is coupled to transistor 14, and the drain of transistor 21 is connected to NODE_B. Combined. As shown, the gate of transistor 21 is coupled to NODE_A. Therefore, when NODE_A is set to a voltage of V _dd , the transistor 21 is turned ON and couples NODE_B to the transistor 14. With transistors 13 and 17 and 14 and 21 configured in this manner, NODE_A and NODE_B can obtain the value of V _ss . For example, if IN_L is V _dd and NODE_B is V _dd , the transistors 13 and 17 are turned on, assuming that CLK is V _dd (ie, the " evaluation " state described below). drain, or NODE_A of 17 obtains the value of the V _sS to V _ss through the transistors (17, 13, 7) path. NODE_B also obtains the value of V _dd described below. Alternatively, if IN_H is V _dd , NODE_A is V _dd , and CLK is V _dd , the drain of transistor 21, or NODE_B, obtains the value of V _ss through the transistors 21, 14, 7 path, NODE_A _Obtains the value of V _dd as described below.

In addition to obtaining the voltage value of V _ss through the path described above, alternatively, NODE_A and NODE_B can achieve the voltage value of V _ss by using "keeper" transistors 18 and 19, both of which are N-type CMOS elements. have. Transistors 18 and 19 are referred to as " keeper " transistors because they help circuit 2 sustain or maintain its value when they are reached by providing different conductive paths. For example, if the gate (output C_H) of transistor 19 is coupled to V _dd such that transistor 19 is ON, and if CLK is V _dd , the combination of transistors 19 and 7 is coupled to NODE_B. _Or the drain of transistor 19 is coupled to V _ss . Similarly, when the gate connection (output C_L) of transistor 18 is coupled to V _dd and CLK is V _dd , transistors 18 and 7 provide a path of NODE_A to V _ss , or the drain of transistor 18. .

In addition to obtaining a voltage value of V _ss , NODE_A and NODE_B can also obtain a voltage value of V _dd . Transistors 20, 22, 30, 31 (shown as P-type CMOS elements) include transistor group 28, which provides multiple paths of NODE_B to obtain a voltage value of V _dd . P-type devices operate in a manner complementary to N-type devices, and in general, when a high voltage is provided to their gate terminals, the P-type devices are turned off; when a low voltage is provided to their gate terminals, the P-type devices are turned on It becomes Similar to group 28, transistors 16, 23, 32, 33 (also shown as P-type CMOS devices) provide group 29, which provides multiple paths of NODE_A to obtain a voltage value of V _dd . Include.

Referring to group 28, NODE_B is coupled to the drain terminal of transistors 20, 22 and 31, and V _dd is coupled to the source terminal of transistors 20, 22 and 30. If the gate of transistor 20 is at a low voltage, ie V _ss , transistor 20 provides a path of NODE_B to obtain a voltage value of V _dd . If the gate of transistor 22 is controlled by clock signal CLK (described in more detail below), transistor 22 also provides a path of NODE_B to V _dd . For example, if CLK is V _SS (ie, the "precharge" phase described below), NODE_B obtains the voltage value of V _dd through transistor 22. With respect to transistors 30 and 31, the drain of transistor 31 is coupled to NODE_B, the source of transistor 31 is coupled to the drain of transistor 30, and the source of transistor 30 is coupled to V _dd . do. In addition, the gate of transistor 31 is coupled to C_H, and the gate of transistor 30 is coupled to IN_H. In this way, the transistors 30 and 31 provide the path of NODE_B to obtain the voltage value of V _dd as well (which can help reduce the soft error described below). For example, if C_H (inversion of NODE_B) is V _ss and IN_H is V _ss , the transistors 30 and 31 provide the path of NODE_B to obtain the voltage value of V _dd . Similar to group 28, group 29 provides a similar function to NODE_B to obtain a voltage value of V _dd through a combination of transistor 16, transistor 23, or transistors 32, 33. Thus, NODE_A and NODE_B will obtain voltage values of V _dd and V _ss , and as a result, outputs C_H and C_L will also obtain voltage values of V _dd and V _ss .

Since the circuit 2 can maintain the states of C_H and C_L, the circuit 2 can be used as a memory storage component, for example, the circuit 2 can be used for a large-capacity integrated circuit comprising an array of memory components. It will be part. The circuit 2 has two separate states, a precharge phase and an evaluation phase. 2 shows the relationship between the various signals. As shown in Fig. 2, the CLK node of the circuit 2 is affected by the precharge phase and the evaluation phase. The precharge phase is associated with assigning predetermined values to NODE_A and NODE_B before storing data in the circuit 20. During the precharge phase, CLK is a low voltage, such as V _ss, and consequently, the transistor 7 OFF state, transistors 16 and 22 are ON state, since NODE_A is coupled to the drain of transistor 16 and V _dd is coupled to the source of transistor 16, NODE_A is shown in FIG. Is precharged to V _dd Similarly, NODE_B is precharged to V _dd due to the connection of transistor 22. In this way, NODE_A and NODE_B are taken of V _dd before circuit 2 is in the evaluation phase. Can be assigned a voltage value, because the transistor 16 alone can precharge NODE_A to V _dd, and since the transistor 22 alone can precharge NODE_B to V _dd , another signal during the precharge phase. (example For example, it should be noted that the states of IN_H and IN_L are meaningless In addition, since transistor 7 is OFF during the precharge phase, NODE_A and NODE_B are not connected to V _ss , and the voltage states of IN_H and IN_L Is irrelevant.

Referring to FIG. 2, the evaluation phase of CLK is related to setting a desired storage value in circuit 2 and to setting up a storage node during the evaluation phase. During the evaluation phase, CLK is high and if IN_H is high during the evaluation phase, transistor 14 is turned on. Since NODE_A is high, the transistor 21 is in an ON state. In addition, when CLK is high in the evaluation phase, transistor 7 is also in an ON state, and NODE_B (i.e., the drain terminal of transistor 21) is turned off of transistors 7, 14, and 21, as shown in FIG. The combination results in a voltage value of V _ss . It should be noted that when NODE_B is low, C_H is high and the keeper transistor 19 is turned on, forming a parallel path of NODE_B to obtain a voltage value of V _ss . In addition, when NODE_B obtains the voltage value of V _ss , the transistor 23 is turned on to maintain the precharge state of NODE_A at V _dd . If circuit 2 is configured in this manner, subsequent changes of IN_H or IN_L will not affect the value of NODE_A or NODE_B until circuit 2 is again precharged as shown.

During the charging event, the digital states of the various nodes in the circuit 2 can be disturbed. Although each node of the circuit 2 affects the overall operation, some nodes can greatly affect the overall state. For example, since NODE_A and NODE_B are coupled to outputs C_H and C_L through inverters 4 and 5, disturbing the digital state of NODE_A or NODE_B can directly affect the output of circuit 2. . Thus, NODE_A and NODE_B have a great influence depending on how soft error state the sensitive circuit 2 is in.

Threshold charge Q _critical is the threshold amount of charge that needs to be injected during a charge event to energize the digital state of the node. If the amount of charge injected into a particular node exceeds the node's critical charge Q _critical , the node changes the digital state. In circuit 2, the amount of charge required to energize their precharge state on NODE_A and NODE_B changes as CLK changes phase. (The following example is related to NODE_A, but note that the same principle applies to NODE_B.) For example, while CLK is changing the phase from precharge phase to evaluation phase, NODE_A is final in the precharge value. To change the value, the critical charge (Q _critical ) required to change the digital state of NODE_A is reduced. However, the amount of critical charge Q _critical required for the value of NODE_A to change the digital state of NODE_A increases. In practice, NODE_A will be more sensitive to ion radiation at the beginning of the evaluation phase.

Embodiments of the invention, such as circuit 2, help to reduce the occurrence of soft errors. For example, referring back to FIG. 1, transistors 32 and 33 provide a path for NODE_A to maintain a precharge value of V _dd while NODE_B is in a changed state. As shown in circuit 2, the gate of transistor 32 is coupled to IN_L, and the gate of transistor 33 is coupled to output C_L, which is the inversion of NODE_A. As shown in Fig. 2, when NODE_B is in the changed state, the value of IN_L goes low and the transistor 32 is turned on. Similarly, since NODE_A is precharged to V _dd , output C_L is low and transistor 33 is on. In this way, while NODE_B is in the change state, NODE_A (coupled to the drain of transistor 30) is held at V _dd by the combination of transistors 32, 33. Thus, the number of soft errors that may occur at the beginning of the evaluation phase can be reduced because NODE_A is maintained at the precharge level of V _dd and NODE_B is low and in the changed state. Without alternative paths provided by transistors 32 and 33, NODE_A will be more sensitive to upsets by ion radiation.

Similarly, if NODE_A is a node that is in the change state and actively goes low, NODE_B becomes more sensitive to the change state as a result of the charge event, and transistors 30 and 31 have similar functions to transistors 32 and 33. To provide. That is, NODE_B is held at the precharge level of V _dd, NODE_A is changing states. In addition to actively maintaining the precharge phases of NODE_A and NODE_B, transistors 30, 31, 32, 33 provide other features that help reduce the number of soft errors. For example, the gate of transistor 33 is coupled to output C_L, which adds additional capacitance, delaying the rate at which output C_L gets its final value. Thus, transistor 18 coupled to output C_L is delayed when turned on, and as a result, NODE_A (coupled to the drain of transistor 18) exhibits a response of the delay to the injected charge. This delayed response is achieved in other ways. Additional inverters can be added before and after inverters 4 and 5, where outputs C_L and C_H represent the final outputs of the final inverter, and the speed at which C_H and C_L obtain their final values can be delayed. The sensitivity to soft errors is best when CLK proceeds from the precharge phase to the evaluation phase, and the delay to these edges makes the circuit "insensitive" (i.e., less sensitive to chaotic conditions caused by ion radiation). Therefore, delaying the other path of V _ss through the transistor 18 in NODE_A and the other path to V _ss through the transistor 19 in NODE_B will lower the soft error rate.

Storage circuits similar to circuit 2 may be duplicated multiple times on a single integrated circuit. Thus, the individual transistors in the circuit 2 are kept as small as possible to conserve space. In this way, the size of transistors 30, 31, 32, 33 can be optimized for reducing the desired level of soft error rate. For example, the number of soft errors can be reduced by making transistors 30, 31, 32, 33 larger than the minimum size enabled by the process. Thus, the circuit designer may choose between increasing the circuit area and reducing the soft error rate, or between reducing the circuit area and increasing the soft error rate.

The storage circuits described herein and methods for reducing the soft error rate can be used in computer systems. 3 illustrates an example computer system 100. The computer system of FIG. 3 includes a CPU 102 coupled to a bridge logic element 106 via a CPU bus. Bridge logic element 106 is also referred to as a "North bridge". The north bridge 106 is coupled to the main memory array 104 by a memory bus and may also be coupled to the graphics controller 108 via a high graphics processor (“AGP”). The north bridge 106 may be connected to other peripherals in the system via a primary expansion bus (“BUS A”), such as, for example, a peripheral component interconnect (“PCI”) bus or an extended industry standard architecture (“EISA”) bus. The CPU 102, the memory 104, and the graphics controller 108 are connected to the device. Various components operating using the bus protocol of BUS A may reside on this bus, such as the audio device 114, the IEEE 1394 interface device 116, and the network interface card (“NIC”) 118. . These components may be integrated on the motherboard, as shown in FIG. 3, or may be plugged into an expansion slot 110 connected to BUS A.

If another secondary expansion bus is provided to the computer system, another bridge logic element 112 may be used to electrically connect the primary expansion bus ("BUS A") to the secondary expansion bus ("BUS B"). This bridge logic 112 is also referred to as the "South bridge". Several components operating using the bus protocol of BUS B include a hard disk controller 112, a system read only memory (“ROM”) 124, and a super input-output (“I / O”) controller 126. As such, it may reside on such a bus. Slot 120 may also be provided for a plug-in component that conforms to the protocol of BUS B. Components of computer system 100 may implement the storage circuits described herein. For example, main memory array 104 may include a storage circuit similar to circuit 2 for reducing the soft error rate. In this way, the recovery of glitches in the system is kept to a minimum.

Once the above-described specification is fully understood, those skilled in the art will recognize that various modifications and changes can be made. For example, other ways of maintaining the precharge value of NODE_A while NODE_B is in a change state (or other method of maintaining NODE_B while NODE_A is in change state) may be implemented. In addition, the voltage levels described herein are arbitrary so that the same functionality can be achieved using negative logic, such that the evaluation phase can be made during the low value CLK, for example.

According to the present invention, the soft error can be reduced.

1 is a diagram showing a circuit configuration according to an embodiment of the present invention;

2 is an exemplary timing diagram for several nodes;

3 is an exemplary computer system.

Explanation of symbols for the main parts of the drawings

100: computer system 102: CPU

104: memory 106: North Bridge

108: graphics controller 110: slot

112: South Bridge 114: Audio

122: hard disk 124: ROM

126: Super I / O

Claims (10)

Allocating a plurality of nodes in the storage circuit 2 to a predetermined state; Evaluating a plurality of signals coupled to the storage circuit to allow the first node Node_A to change from a predetermined state and to make the second node Node_B more sensitive to disturbances; Maintaining the second node Node_B for a predetermined time to reduce the sensitivity of the storage circuit to soft errors. How to include. The method of claim 1, Disabling a clock signal (CLK) in the plurality of signals during a precharge phase. The method of claim 2, Constructing input signals in the plurality of signals during the precharge phase of the clock signal (CLK). The method of claim 1, Enabling the clock signal CLK during the evaluation phase. The method of claim 4, wherein Correlating the predetermined time to the start of the evaluation phase of the clock signal (CLK). The method of claim 1, Delaying signal propagation between the first and second nodes using a plurality of inverters (4, 5). In the storage circuit 2, A plurality of nodes including a first node Node_A and a second node Node_B coupled to each other, A plurality of signals coupled to the storage circuitry to allow the first node Node_A to change from a predetermined state; A circuit component 20 coupled to the second node to hold the second node in a predetermined state for a predetermined time Storage circuit comprising a. The method of claim 7, wherein The circuit component includes a metal oxide semiconductor field effect transistor (" MOSFET "), wherein the size of the transistor is changed to change a time period during which the second node Node_B remains in the predetermined state. The method of claim 7, wherein At least one inverter (4, 5) is coupled between the first node (Node_A) and the second node (Node_B). The method of claim 7, wherein The timing signal comprises a precharge phase and an evaluation phase, wherein the nodes are set to a high state during the precharge phase and the nodes are set to a final state during the evaluation phase.