KR20050062921A - Method for forming three-layered photoresist pattern of semiconductor device - Google Patents
Method for forming three-layered photoresist pattern of semiconductor device Download PDFInfo
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- KR20050062921A KR20050062921A KR1020030093922A KR20030093922A KR20050062921A KR 20050062921 A KR20050062921 A KR 20050062921A KR 1020030093922 A KR1020030093922 A KR 1020030093922A KR 20030093922 A KR20030093922 A KR 20030093922A KR 20050062921 A KR20050062921 A KR 20050062921A
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 title 1
- 239000000203 mixture Substances 0.000 claims abstract description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 239000010703 silicon Substances 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 18
- 238000009832 plasma treatment Methods 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 238000010894 electron beam technology Methods 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 2
- 230000007261 regionalization Effects 0.000 claims description 2
- 239000003795 chemical substances by application Substances 0.000 abstract 1
- 229920005989 resin Polymers 0.000 description 8
- 239000011347 resin Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- NIXOWILDQLNWCW-UHFFFAOYSA-M Acrylate Chemical compound [O-]C(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-M 0.000 description 4
- PPBRXRYQALVLMV-UHFFFAOYSA-N Styrene Chemical compound C=CC1=CC=CC=C1 PPBRXRYQALVLMV-UHFFFAOYSA-N 0.000 description 4
- 238000004090 dissolution Methods 0.000 description 4
- 230000002401 inhibitory effect Effects 0.000 description 4
- 229920003986 novolac Polymers 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000003667 anti-reflective effect Effects 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000003079 width control Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/095—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having more than one photosensitive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
본 발명은 반도체소자의 3층 레지스트 패턴 형성방법에 관한 것으로, 피식각층 상부에 하부 레지스트 조성물을 도포한 후 베이크하여 하부 레지스트막을 형성하는 단계와, 상기 하부 레지스트막 상부에 실리콘을 함유하는 레지스트 조성물을 도포한 후 베이크하여 실리콘 함유 레지스트막을 형성하는 단계와, 상기 실리콘 함유 레지스트막을 O2 플라즈마로 처리하여 산화막으로 형성하는 단계와, 상기 산화막 상부에 상부 레지스트 조성물을 도포한 후 베이크하여 상부 레지스트막을 형성하는 단계와, 상기 상부 레지스트막을 선택적으로 노광 및 현상하여 상부 레지스트막 패턴을 형성하는 단계와, 상기 상부 레지스트막 패턴을 식각마스크로 상기 산화막을 식각하여 산화막 패턴을 형성하는 단계와, 상기 산화막 패턴을 식각마스크로 상기 하부 레지스트막을 식각하여 하부 레지스트막 패턴을 형성하는 단계를 포함하는 반도체소자의 3층 레지스트 패턴 형성방법을 개시한다.The present invention relates to a method of forming a three-layer resist pattern of a semiconductor device, comprising: applying a lower resist composition on an etched layer and baking the same to form a lower resist film; and forming a resist composition containing silicon on the lower resist film. Applying and baking to form a silicon-containing resist film; treating the silicon-containing resist film with an O 2 plasma to form an oxide film; applying and baking an upper resist composition on the oxide film to form an upper resist film Selectively exposing and developing the upper resist layer to form an upper resist layer pattern, etching the oxide layer using the upper resist layer pattern as an etch mask to form an oxide layer pattern, and etching the oxide layer pattern The lower ledge as a mask Agent by etching a film discloses a three-layer resist pattern forming method of the semiconductor device including the step of forming a lower resist film pattern.
Description
본 발명은 반도체소자의 3층 레지스트 패턴 형성방법에 관한 것으로, 더욱 상세하게는 상부 레지스트막과 하부 레지스트막 사이에 플라즈마 인핸스드 방법을 이용하여 산화막을 증착하는 대신 실리콘을 함유하는 레지스트막을 형성시킨 후 O2 플라즈마 처리하여 산화막으로 형성하는 단계를 포함하는 것을 특징으로 하는 반도체소자의 3층 레지스트 패턴 형성방법에 관한 것이다.The present invention relates to a method of forming a three-layer resist pattern of a semiconductor device, and more particularly, after forming a resist film containing silicon instead of depositing an oxide film using a plasma enhanced method between an upper resist film and a lower resist film. It relates to a three-layer resist pattern forming method of a semiconductor device comprising the step of forming an oxide film by O 2 plasma treatment.
최근, 0.13㎛ 이하의 초미세 패턴 형성에 있어서, 종래의 레지스트막 두께에서는 아스펙트 비(aspect ratio)가 높아 패턴이 쓰러지는 문제가 발생하고 있으나, 이를 위해 레지스트막의 두께를 낮추면 에칭시 내성이 없어져 후속 공정이 불가능하다.Recently, in the formation of ultra fine patterns of 0.13 μm or less, there is a problem in that a pattern collapses due to a high aspect ratio in the conventional resist film thickness. The process is impossible.
이에 따라, 초미세 패턴 형성시 레지스트막의 두께는 낮추되 에칭시 내성을 갖도록 하기 위하여 상부 레지스트막과 하부 레지스트막을 형성시키고, 이들의 중간에 산화막을 개재하는 방법을 사용하는 3층 레지스트(three-layered resist) 패턴 형성공정이 대두되고 있다.Accordingly, in order to reduce the thickness of the resist film when forming an ultrafine pattern, but to resist the etching, a three-layered resist is formed by forming an upper resist film and a lower resist film and interposing an oxide film therebetween. resist) Pattern forming process is emerging.
도 1a 내지 도 1g는 종래 기술에 따른 반도체소자의 3층 레지스트 패턴 형성방법을 도시한 공정 단면도이다.1A to 1G are cross-sectional views illustrating a method of forming a three-layer resist pattern of a semiconductor device according to the prior art.
도 1a를 참조하면, 피식각층(10) 상부에 하부 레지스트 조성물을 0.5∼0.7㎛의 두께로 도포한 다음, 150∼170℃의 온도에서 60∼120초동안 베이크하여 하부 레지스트막(12)을 형성한다.Referring to FIG. 1A, a lower resist composition is coated on the etched layer 10 to a thickness of 0.5 to 0.7 μm, and then baked at a temperature of 150 to 170 ° C. for 60 to 120 seconds to form a lower resist film 12. do.
상기 하부 레지스트 조성물은 g-line(436nm), i-line(365nm), KrF(248nm), ArF(193nm), F2(157nm) 또는 EUV(13nm) 등의 파장에서 사용되는 모든 레지스트 수지를 포함할 뿐만 아니라, 유기 반사방지용 물질을 사용할 수도 있으며, 상기 모든 레지스트에 대해 비용을 줄이기 위해서 감광성 물질(photoactive compound)을 포함하지 않아도 된다. 바람직하게는 i-line 레지스트 및 g-line 레지스트에 사용되는 노볼락(novolac) 수지, KrF 레지스트에 사용되는 폴리히드록시스티렌, ArF 및 F2 레지스트에 사용되는 아크릴레이트계 수지를 사용할 수 있다.The lower resist composition includes all resist resins used at wavelengths such as g-line (436 nm), i-line (365 nm), KrF (248 nm), ArF (193 nm), F 2 (157 nm) or EUV (13 nm). In addition, an organic antireflective material may be used, and it is not necessary to include a photoactive compound to reduce the cost for all the resists. Preferably, novolac resins used for i-line resists and g-line resists, polyhydroxystyrenes used for KrF resists, and acrylate resins used for ArF and F 2 resists may be used.
도 1b를 참조하면, 하부 레지스트막(12) 상부에 플라즈마 인핸스드 화학기상증착(plasma enhanced chemical vapor deposition, 이하 "PECVD"라 칭함) 방법을 이용하여 150∼200℃의 온도에서 500∼1500Å의 두께로 PE-TEOS(Plasma Enhanced-tetraethyl ortho silicate)막을 증착하여 산화막(14)을 형성한다.Referring to FIG. 1B, a thickness of 500 to 1500 kPa is performed at a temperature of 150 to 200 ° C. by using plasma enhanced chemical vapor deposition (hereinafter referred to as “PECVD”) on the lower resist layer 12. PE-TEOS (Plasma Enhanced-tetraethyl ortho silicate) film is deposited to form an oxide film 14.
도 1c를 참조하면, 산화막(14) 상부에 상부 레지스트 조성물을 0.1∼0.3㎛의 두께로 도포한 다음, 110∼130℃의 온도에서 60∼120초동안 베이크하여 상부 레지스트막(16)을 형성한다.Referring to FIG. 1C, the upper resist composition is coated on the oxide film 14 to a thickness of 0.1 to 0.3 μm, and then baked at a temperature of 110 to 130 ° C. for 60 to 120 seconds to form the upper resist film 16. .
상기 상부 레지스트 조성물은 감광성 물질을 포함하는 용해억제형 레지스트 (Dissolution Inhibition Resist) 또는 화학증폭형 레지스트(Chemically Amplified Resist)로서, 보다 상세하게는 g-line(436nm) 또는 i-line(365nm)의 파장에서 사용되는 용해억제형 레지스트의 경우 노볼락 수지와 감광성 물질을 함께 포함하는 것이고, KrF(248nm), ArF(193nm), F2(157nm) 또는 EUV(13nm)의 파장에서 사용되는 화학증폭형 레지스트의 경우 폴리히드록시스티렌 또는 아크릴레이트계 수지와 함께 광산발생제를 포함하는 것이다.The upper resist composition is a dissolution inhibiting resist or a chemically amplified resist including a photosensitive material, and more specifically, a wavelength of g-line (436 nm) or i-line (365 nm). In the case of the dissolution inhibiting resist used in the present invention, a novolak resin and a photosensitive material are included together, and a chemically amplified resist used at a wavelength of KrF (248 nm), ArF (193 nm), F 2 (157 nm) or EUV (13 nm) In the case of a polyhydroxy styrene or acrylate-based resin is to include a photoacid generator.
도 1d를 참조하면, 노광마스크(30)를 이용하여 상부 레지스트막(16)을 5∼50 mJ/㎠의 노광에너지로 선택 노광하여 노광영역(22) 및 비노광영역(20)을 형성한다. 이때, g-line(436nm), i-line(365nm), KrF(248nm), ArF (193nm), F2(157nm), EUV (13nm) 또는 전자빔을 노광원으로 사용한다.Referring to FIG. 1D, the exposure mask 30 is used to selectively expose the upper resist film 16 with exposure energy of 5 to 50 mJ / cm 2 to form the exposure area 22 and the non-exposure area 20. In this case, g-line (436 nm), i-line (365 nm), KrF (248 nm), ArF (193 nm), F 2 (157 nm), EUV (13 nm) or an electron beam is used as the exposure source.
도 1e를 참조하면, 노광영역(22)을 2.38wt% 농도의 TMAH 수용액으로 30∼40초간 현상하여 제거함으로써, 상부 레지스트막 패턴(24)을 형성한다.Referring to FIG. 1E, the upper resist film pattern 24 is formed by developing and removing the exposed area 22 in a TMAH aqueous solution having a concentration of 2.38 wt% for 30 to 40 seconds.
도 1f를 참조하면, 상부 레지스트막 패턴(24)을 식각마스크로 하고, 플라즈마를 사용하여 하부의 산화막(16)을 식각하여 산화막 패턴(26)을 형성한 다음, 상부 레지스트막 패턴(24)을 제거한다.Referring to FIG. 1F, the upper resist film pattern 24 is used as an etch mask, the lower oxide film 16 is etched using plasma to form an oxide film pattern 26, and then the upper resist film pattern 24 is formed. Remove
도 1g를 참조하면, 산화막 패턴(26)을 식각마스크로 하고 플라즈마를 사용하여 하부의 하부 레지스트막(12)을 식각하여 하부 레지스트막 패턴(28)을 형성함으로써 피식각층(10) 식각시 마스크 역할을 하는 레지스트 패턴을 얻을 수 있다.Referring to FIG. 1G, the oxide pattern 26 is used as an etch mask and the lower resist layer 12 is etched using plasma to form the lower resist layer pattern 28 to form a mask when etching the etched layer 10. A resist pattern can be obtained.
상기한 바와 같이, 종래에는 하부 레지스트막(12)과 상부 레지스트막(18) 사이에 산화막(16)을 형성하기 위하여 PECVD 장비가 필요했고, 또한 산화막(16) 증착시 하부 레지스트막(12)의 온도가 200℃ 이상으로 올라감에 따라 하부 레지스트막 (12)에 데미지(damage)가 발생하는 문제점이 있었다.As described above, conventionally, PECVD equipment was required to form the oxide film 16 between the lower resist film 12 and the upper resist film 18. Also, when the oxide film 16 is deposited, the lower resist film 12 is formed. As the temperature is raised to 200 ° C. or more, there is a problem in that damage occurs in the lower resist film 12.
아울러, 하부 레지스트막(12)과 산화막(14) 간의 접착력이 불량하기 때문에 하부 레지스트막(12)을 건식 식각할 때에 산화막(14) 하부에서 언더컷(undercut)이 발생되어 패턴의 선폭 제어가 어려운 문제점이 있었다.In addition, since the adhesion between the lower resist film 12 and the oxide film 14 is poor, an undercut occurs under the oxide film 14 when dry etching the lower resist film 12, thereby making it difficult to control the line width of the pattern. There was this.
본 발명은 상기 종래기술의 문제점을 해결하기 위하여 안출된 것으로, 종래와 같이 PECVD 산화막을 증착하는 대신, 실리콘을 함유하는 레지스트막을 형성시킨 후 O2 플라즈마 처리하여 산화막으로 형성하는 반도체소자의 3층 레지스트 패턴 형성방법을 제공하는 것을 목적으로 한다.The present invention has been made to solve the problems of the prior art, and instead of depositing a PECVD oxide film as in the prior art, a three-layer resist of a semiconductor device formed by forming an oxide film by O 2 plasma treatment after forming a resist film containing silicon. It is an object to provide a pattern formation method.
상기 목적을 달성하기 위한 본 발명의 반도체소자의 3층 레지스트 패턴 형성방법은 Method of forming a three-layer resist pattern of the semiconductor device of the present invention for achieving the above object
(a) 피식각층 상부에 하부 레지스트 조성물을 도포한 후 베이크하여 하부 레지스트막을 형성하는 단계;(a) applying a lower resist composition on the etched layer and baking the same to form a lower resist film;
(b) 상기 하부 레지스트막 상부에 실리콘을 함유하는 레지스트 조성물을 도포한 후 베이크하여 실리콘 함유 레지스트막을 형성하는 단계;(b) applying a silicon-containing resist composition on the lower resist film and baking it to form a silicon-containing resist film;
(c) 상기 실리콘 함유 레지스트막을 O2 플라즈마로 처리하여 산화막으로 형성하는 단계;(c) treating the silicon-containing resist film with an O 2 plasma to form an oxide film;
(d) 상기 산화막 상부에 상부 레지스트 조성물을 도포한 후 베이크하여 상부 레지스트막을 형성하는 단계;(d) applying an upper resist composition on the oxide film and baking the same to form an upper resist film;
(e) 상기 상부 레지스트막을 선택적으로 노광 및 현상하여 상부 레지스트막 패턴을 형성하는 단계;(e) selectively exposing and developing the upper resist film to form an upper resist film pattern;
(f) 상기 상부 레지스트막 패턴을 식각마스크로 상기 산화막을 식각하여 산화막 패턴을 형성하는 단계; 및(f) forming the oxide layer pattern by etching the oxide layer using the upper resist layer pattern as an etch mask; And
(g) 상기 산화막 패턴을 식각마스크로 상기 하부 레지스트막을 식각하여 하부 레지스트막 패턴을 형성하는 단계를 포함한다.(g) etching the lower resist layer using the oxide pattern as an etching mask to form a lower resist layer pattern.
이하, 첨부된 도면을 참고로 하여 본 발명의 실시예를 상세히 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2h는 본 발명에 따른 반도체소자의 3층 레지스트 패턴 형성방법을 도시한 공정 단면도이다.2A to 2H are cross-sectional views illustrating a method of forming a three-layer resist pattern of a semiconductor device according to the present invention.
도 2a를 참조하면, 금속층, 절연막 또는 도전막인 피식각층(110) 상부에 하부 레지스트 조성물을 0.5∼0.7㎛의 두께로 도포한 다음, 150∼170℃의 온도에서 60∼120초, 바람직하게는 90초동안 베이크하여 하부 레지스트막(112)을 형성한다.Referring to FIG. 2A, a lower resist composition is applied on the etched layer 110, which is a metal layer, an insulating film, or a conductive film, to a thickness of 0.5 to 0.7 μm, and then 60 to 120 seconds at a temperature of 150 to 170 ° C., preferably Bake for 90 seconds to form the lower resist film 112.
상기 하부 레지스트 조성물은 g-line(436nm), i-line(365nm), KrF(248nm), ArF(193nm), F2(157nm) 또는 EUV(13nm) 등의 파장에서 사용되는 모든 레지스트 수지를 포함할 뿐만 아니라, 유기 반사방지용 물질을 사용할 수도 있으며, 상기 모든 레지스트에 대해 비용을 줄이기 위해서 감광성 물질(photoactive compound)을 포함하지 않아도 된다. 바람직하게는 i-line 레지스트 및 g-line 레지스트에 사용되는 노볼락(novolac) 수지, KrF 레지스트에 사용되는 폴리히드록시스티렌, ArF 및 F2 레지스트에 사용되는 아크릴레이트계 수지를 사용할 수 있다.The lower resist composition includes all resist resins used at wavelengths such as g-line (436 nm), i-line (365 nm), KrF (248 nm), ArF (193 nm), F 2 (157 nm) or EUV (13 nm). In addition, an organic antireflective material may be used, and it is not necessary to include a photoactive compound to reduce the cost for all the resists. Preferably, novolac resins used for i-line resists and g-line resists, polyhydroxystyrenes used for KrF resists, and acrylate resins used for ArF and F 2 resists may be used.
도 2b를 참조하면, 하부 레지스트막(112)의 상부에 실리콘(Si)을 함유하는 레지스트 조성물을 0.1∼0.2㎛의 두께로 도포한 다음, 100∼130℃의 온도에서 60 내지 120초, 바람직하게는 90초동안 베이크하여 실리콘 함유 레지스트막(114)을 형성한다.Referring to FIG. 2B, a resist composition containing silicon (Si) is applied on the upper portion of the lower resist film 112 to a thickness of 0.1 to 0.2 μm, and then 60 to 120 seconds at a temperature of 100 to 130 ° C., preferably Bake for 90 seconds to form a silicon-containing resist film 114.
상기 실리콘을 함유하는 레지스트 조성물로는 본 출원인에 의해 기출원된 공개특허 제1999-57356호, 제2001-11768호, 제2001-81753호 및 제2002-59호에 개시되어 있는 조성물을 사용할 수 있고, 그 외 실리콘을 함유하는 통상의 레지스트 조성물이라면 어느 것을 사용하여도 무방하다.As the silicone-containing resist composition, the compositions disclosed in Japanese Patent Application Nos. 1999-57356, 2001-11768, 2001-81753, and 2002-59, filed by the present applicant, can be used. As long as it is a normal resist composition containing other silicone, you may use it.
도 2c를 참조하면, 실리콘 함유 레지스트막(114)을 O2 플라즈마로 처리하여 산화막(116)으로 형성한다. 이는 실리콘 함유 레지스트막(114) 내부의 실리콘과 산소가 반응하여 SiO2 산화막이 형성되는 것이다.Referring to FIG. 2C, the silicon-containing resist film 114 is treated with an O 2 plasma to form an oxide film 116. This is because the silicon in the silicon-containing resist film 114 and oxygen react to form an SiO 2 oxide film.
상기 O2 플라즈마 처리공정의 조건은 식각장비에 따라 다르기는 하나, 30∼60mT의 압력, 500∼1000W의 파워(power) 및 5∼10MHz의 RF 전력 조건하에서 산소의 유량을 20∼30sccm으로 하는 것이 바람직하다.Although the conditions of the O 2 plasma treatment process vary depending on the etching equipment, the flow rate of oxygen is 20 to 30 sccm under a pressure of 30 to 60 mT, a power of 500 to 1000 W, and an RF power of 5 to 10 MHz. desirable.
도 2d를 참조하면, 산화막(116) 상부에 상부 레지스트 조성물을 0.1∼0.3㎛의 두께로 도포한 다음, 110∼130℃의 온도에서 60∼120초, 바람직하게는 90초동안 베이크하여 상부 레지스트막(118)을 형성한다.Referring to FIG. 2D, the upper resist composition is applied on the oxide film 116 to a thickness of 0.1 to 0.3 μm, and then baked at a temperature of 110 to 130 ° C. for 60 to 120 seconds, preferably 90 seconds, to form the upper resist film. Form 118.
상기 상부 레지스트 조성물은 감광성 물질을 포함하는 용해억제형 레지스트 (Dissolution Inhibition Resist) 또는 화학증폭형 레지스트(Chemically Amplified Resist)로서, 보다 상세하게는 g-line(436nm) 또는 i-line(365nm)의 파장에서 사용되는 용해억제형 레지스트의 경우 노볼락 수지와 감광성 물질을 함께 포함하는 것이고, KrF(248nm), ArF(193nm), F2(157nm) 또는 EUV(13nm)의 파장에서 사용되는 화학증폭형 레지스트의 경우 폴리히드록시스티렌 또는 아크릴레이트계 수지와 함께 광산발생제를 포함하는 것이다.The upper resist composition is a dissolution inhibiting resist or a chemically amplified resist including a photosensitive material, and more specifically, a wavelength of g-line (436 nm) or i-line (365 nm). In the case of the dissolution inhibiting resist used in the present invention, a novolak resin and a photosensitive material are included together, and a chemically amplified resist used at a wavelength of KrF (248 nm), ArF (193 nm), F 2 (157 nm) or EUV (13 nm) In the case of a polyhydroxy styrene or acrylate-based resin is to include a photoacid generator.
도 2e를 참조하면, 노광마스크(130)를 이용하여 상부 레지스트막(118)을 5∼50mJ/㎠의 노광에너지로 선택 노광한 다음, 100∼130℃의 온도에서 60∼120초, 바람직하게는 90초동안 포스트 베이크하여 노광영역(122) 및 비노광영역(120)을 형성한다. 이때, 노광원으로는 g-line(436nm), i-line(365nm), KrF(248nm), ArF (193nm), F2(157nm), EUV(13nm) 또는 전자빔을 사용한다.Referring to FIG. 2E, the upper resist film 118 is selectively exposed to an exposure energy of 5 to 50 mJ / cm 2 using the exposure mask 130, and then 60 to 120 seconds at a temperature of 100 to 130 ° C., preferably Post-baking for 90 seconds to form the exposure area 122 and the non-exposure area 120. In this case, g-line (436 nm), i-line (365 nm), KrF (248 nm), ArF (193 nm), F 2 (157 nm), EUV (13 nm) or an electron beam is used as the exposure source.
도 2f를 참조하면, 노광영역(122)을 0.1∼10wt%, 바람직하게는 2.38wt% 농도의 TMAH 수용액으로 30∼40초간 현상하여 제거함으로써, 상부 레지스트막 패턴 (124)을 형성한다.Referring to FIG. 2F, the upper resist film pattern 124 is formed by developing and removing the exposed area 122 in a TMAH aqueous solution having a concentration of 0.1 to 10 wt%, preferably 2.38 wt% for 30 to 40 seconds.
도 2g를 참조하면, 상부 레지스트막 패턴(124)을 식각마스크로 하고, C4F8 플라즈마, C4F6 플라즈마 또는 C5F8 플라즈마를 사용하여 하부의 산화막(116)을 식각하여 산화막 패턴(126)을 형성한 다음, 상부 레지스트막 패턴(124)을 제거한다.Referring to FIG. 2G, the upper resist layer pattern 124 is used as an etch mask, and an oxide layer pattern is etched by etching the lower oxide layer 116 using C 4 F 8 plasma, C 4 F 6 plasma, or C 5 F 8 plasma. 126 is formed, and then the upper resist film pattern 124 is removed.
도 2h를 참조하면, 산화막 패턴(126)을 식각마스크로 하고 O2 플라즈마 및 SO2 플라즈마를 동시에 사용하여 하부의 하부 레지스트막(112)을 식각하여 하부 레지스트막 패턴(128)을 형성함으로써, 피식각층(110) 식각시 마스크 역할을 하는 레지스트 패턴을 얻을 수 있다.Referring to FIG. 2H, the lower resist layer 112 is etched using the oxide pattern 126 as an etch mask and the O 2 plasma and the SO 2 plasma are simultaneously used to form the lower resist layer pattern 128. A resist pattern serving as a mask when etching each layer 110 may be obtained.
이때, 상기 O2 플라즈마는 하부 레지스트막(112)을 식각하는 역할을 하고, SO2 플라즈마는 식각된 하부 레지스트막(112)의 측벽에 폴리머를 형성시켜 하부 레지스트막 패턴(128)이 수직한 모양으로 형성되도록 도와주는 역할을 한다. 또한, 상기 식각공정시 불활성 가스인 N2 가스를 넣어줌으로써 식각반응에는 영향을 주지 않으나 플라즈마의 밀도가 높아지도록 할 수 있다.In this case, the O 2 plasma serves to etch the lower resist layer 112, and the SO 2 plasma forms a polymer on the sidewall of the etched lower resist layer 112 so that the lower resist layer pattern 128 is vertical. It helps to be formed into. In addition, the N 2 gas, which is an inert gas, may be added to the etching process to increase the plasma density without affecting the etching reaction.
이상에서 설명한 바와 같이, 본 발명에서는 실리콘을 함유하는 레지스트막을 형성시킨 후 O2 플라즈마 처리하여 산화막으로 형성함으로써, 고가의 PECVD 장비를 사용하여 산화막을 증착하지 않아도 되고, 실리콘을 함유하는 레지스트막 형성시 증착온도를 130℃ 이하로 할 수 있어, 하부 레지스트막에 변형을 유발시키지 않으므로 하부 레지스트막을 건식 식각할 때에 패턴 선폭 제어에 불량이 발생하는 비율 및 디펙트 발생이 감소한다. 또한, 산화막과 하부 레지스트막간의 접착력이 우수하기 때문에 언더컷이 발생하지 않는다.As described above, in the present invention, by forming a resist film containing silicon and then forming an oxide film by O 2 plasma treatment, it is not necessary to deposit an oxide film using expensive PECVD equipment, and at the time of forming a resist film containing silicon Since the deposition temperature can be 130 ° C. or lower and no deformation is caused in the lower resist film, the rate and defect occurrence of defects in the pattern line width control when dry etching the lower resist film are reduced. In addition, undercut does not occur because the adhesion between the oxide film and the lower resist film is excellent.
도 1a 내지 도 1g는 종래기술에 따른 반도체소자의 3층 레지스트 패턴 형성방법을 도시한 공정 단면도.1A to 1G are cross-sectional views illustrating a method of forming a three-layer resist pattern of a semiconductor device according to the prior art.
도 2a 내지 도 2h는 본 발명에 따른 반도체소자의 3층 레지스트 패턴 형성방법을 도시한 공정 단면도.2A to 2H are cross-sectional views illustrating a method of forming a three-layer resist pattern of a semiconductor device according to the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
10, 110 : 피식각층 12, 112 : 하부 레지스트막10, 110: etched layer 12, 112: lower resist film
114 : 실리콘 함유 레지스트막 16, 116 : 산화막114: silicon-containing resist film 16, 116 oxide film
18, 118 : 상부 레지스트막 20, 120 : 노광영역18, 118: upper resist film 20, 120: exposure area
22, 122 : 비노광영역 24, 124 : 상부 레지스트막 패턴22, 122: non-exposed areas 24, 124: upper resist film pattern
26, 126 : 산화막 패턴 28, 128 : 하부 레지스트막 패턴26, 126: oxide film pattern 28, 128: lower resist film pattern
30, 130 : 노광마스크30, 130: exposure mask
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