KR20050062837A - 어드레스 핀을 테스트 모드 설정 입력 핀으로 활용하는집적회로 - Google Patents
어드레스 핀을 테스트 모드 설정 입력 핀으로 활용하는집적회로 Download PDFInfo
- Publication number
- KR20050062837A KR20050062837A KR1020030093161A KR20030093161A KR20050062837A KR 20050062837 A KR20050062837 A KR 20050062837A KR 1020030093161 A KR1020030093161 A KR 1020030093161A KR 20030093161 A KR20030093161 A KR 20030093161A KR 20050062837 A KR20050062837 A KR 20050062837A
- Authority
- KR
- South Korea
- Prior art keywords
- integrated circuit
- pin
- test mode
- mode setting
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31713—Input or output interfaces for test, e.g. test pins, buffers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (4)
- 테스트 모드의 설정을 필요로 하는 집적회로에 있어서,상기 집적회로의 어드레스 핀에 공통으로 연결되는 입력 버퍼와 출력 버퍼;상기 어드레스 핀을 상기 집적회로의 리셋(reset) 구간 동안에는 테스트 모드 설정 입력 핀으로 이용하고, 그 이외의 정상 기능 동작 구간에서는 어드레스 핀으로 이용하기 위한 소정의 신호를 발생하는 신호발생 수단을 포함하는 것을 특징으로 하는 어드레스 핀을 테스트 모드 설정 입력 핀으로 활용하는 집적회로.
- 제1항에 있어서, 상기 신호발생 수단은,상기 집적회로의 리셋 신호를 입력받아 1 사이클 크기의 인에이블(enable) 신호를 생성하는 원샷신호 발생기;상기 원샷신호 발생기에 의해 생성되는 인에이블 신호의 구간 동안 상기 어드레스 핀을 통해 입력되는 테스트 모드 입력 신호를 저장하는 플립플롭을 포함하는 것을 특징으로 하는 어드레스 핀을 테스트 모드 설정 입력 핀으로 활용하는 집적회로.
- 제2항에 있어서,상기 플립플롭은 D 플립플롭인 것을 특징으로 하는 어드레스 핀을 테스트 모드 설정 입력 핀으로 활용하는 집적회로.
- 제1항에 있어서,상기 리셋 구간 동안 상기 입력 버퍼는 인에이블되고, 상기 출력 버퍼는 디스에이블(disable)되는 것을 특징으로 하는 어드레스 핀을 테스트 모드 설정 입력 핀으로 활용하는 집적회로.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030093161A KR20050062837A (ko) | 2003-12-18 | 2003-12-18 | 어드레스 핀을 테스트 모드 설정 입력 핀으로 활용하는집적회로 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030093161A KR20050062837A (ko) | 2003-12-18 | 2003-12-18 | 어드레스 핀을 테스트 모드 설정 입력 핀으로 활용하는집적회로 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20050062837A true KR20050062837A (ko) | 2005-06-28 |
Family
ID=37254753
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020030093161A Ceased KR20050062837A (ko) | 2003-12-18 | 2003-12-18 | 어드레스 핀을 테스트 모드 설정 입력 핀으로 활용하는집적회로 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR20050062837A (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100904479B1 (ko) * | 2007-06-27 | 2009-06-24 | 주식회사 하이닉스반도체 | 반도체 메모리장치 및 이의 어드레스 입력방법 |
-
2003
- 2003-12-18 KR KR1020030093161A patent/KR20050062837A/ko not_active Ceased
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7697368B2 (en) | 1920-06-27 | 2010-04-13 | Hynix Semiconductor, Inc. | Semiconductor memory device and method of inputting addresses therein |
KR100904479B1 (ko) * | 2007-06-27 | 2009-06-24 | 주식회사 하이닉스반도체 | 반도체 메모리장치 및 이의 어드레스 입력방법 |
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Legal Events
Date | Code | Title | Description |
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PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 20031218 |
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PG1501 | Laying open of application | ||
A201 | Request for examination | ||
PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 20081104 Comment text: Request for Examination of Application Patent event code: PA02011R01I Patent event date: 20031218 Comment text: Patent Application |
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E902 | Notification of reason for refusal | ||
PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20091218 Patent event code: PE09021S01D |
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E601 | Decision to refuse application | ||
PE0601 | Decision on rejection of patent |
Patent event date: 20100331 Comment text: Decision to Refuse Application Patent event code: PE06012S01D Patent event date: 20091218 Comment text: Notification of reason for refusal Patent event code: PE06011S01I |