KR20050062122A - Method for fabricating semiconductor device - Google Patents

Abstract

The present invention relates to a method for manufacturing a semiconductor device, comprising: forming a field oxide film defining an active region of an element on a first conductive semiconductor substrate, and forming a gate and a cap layer by interposing a gate oxide layer on the active region; Forming sidewalls on the side surfaces of the gate and cap layers, forming first and second impurity regions of the second conductivity type in the exposed portions of the semiconductor substrate, and forming a first interlayer dielectric layer exposing a portion of the active region on the semiconductor substrate. Forming a first and a second landing pad in contact with the first and second impurity regions by filling polycrystalline silicon doped with impurities between sidewalls on the first interlayer insulating layer; Selectively silencing the surface of the landing pad to form first and second low resistance layers, and first contact holes exposing the first low resistance layers on the first interlayer insulating layer. Forming a second interlayer dielectric layer and forming a bit line in contact with the first landing pad through the first contact hole on the second interlayer dielectric layer; and covering the bit line on the second interlayer dielectric layer Forming a third insulating layer having a second contact hole for exposing the low resistance layer, and filling the second contact hole with polysilicon to form a plug.

Description

Method for fabricating semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of reducing contact resistance between a landing pad and a storage node plug.

As the degree of integration of semiconductor devices is increased, design rules are reduced to reduce the size of the impurity regions forming the source and drain regions. Therefore, a plug or a landing pad for electrically connecting the impurity region with other layers to be formed later is formed by a Self Align Contact (SAC) method.

1A to 1E are process drawings showing a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1A, a field oxide film 13 is formed on a P-type semiconductor substrate 11 to define an active region. The field oxide layer 13 may be formed by a shallow trench isolation (STI) method or a local oxide of silicon (LOCOS) method.

The gate 20 and the cap layer 21 are formed on the active region of the semiconductor substrate 11 with the gate oxide film 15 interposed therebetween. The gate oxide film 15 is formed by thermally oxidizing an active region of the semiconductor substrate 11. In addition, after the polycrystalline silicon layer 17, the silicide layer 19, and the cap layer 21 doped with impurities are sequentially stacked on the gate oxide layer 15, a photo including anisotropic etching such as reactive ion etching (RIE) or the like. Patterned by lithographic method. In the above, the polysilicon layer 17 and the silicide layer 19 become the gate 20. The silicide layer 19 is a silicide such as tungsten, and the cap layer 21 is formed by depositing silicon nitride or the like by chemical vapor deposition (hereinafter, referred to as CVD).

Referring to FIG. 1B, silicon oxide having a different etching selectivity from silicon nitride is deposited by a CVD method to cover the gate 20 and the cap layer 21 on the semiconductor substrate 11, and then the semiconductor substrate 11 and the cap layer ( The upper surface of 19 is etched back to form sidewalls 23 on the sides of gate 20 and cap layer 21.

Source and drain regions of the device by ion implanting N-type impurities such as phosphorus (P) or arsenic (As) into the exposed portions of the semiconductor substrate 11 using the cap layer 21 and the sidewalls 23 as masks. First and second impurity regions 25 and 27 are formed.

Then, silicon oxide or the like is deposited on the semiconductor substrate 11 to cover the cap layer 21 and the sidewall 23 by the CVD method, and planarized by the chemical mechanical polishing (CMP) method to form the first interlayer insulating layer 29. do. Next, the first interlayer insulating layer 29 is patterned by photolithography to expose a portion of the active region of the semiconductor substrate 11.

Referring to FIG. 1C, polycrystalline silicon doped with impurities is deposited on the first interlayer insulating layer 29 by contacting the first and second impurity regions 25 and 27 with CVD. do. Then, the deposited polysilicon is etched back by RIE method or polished by CMP method so that the cap layer 21 is exposed and contacted with the first and second impurity regions 25 and 27 between the sidewalls 21, respectively. First and second landing pads 31 and 33 are formed. At this time, the first interlayer insulating layer 29 is also etched so that there is no step with the cap layer 21.

Referring to FIG. 1D, silicon oxide or the like is deposited on the entire surface of the above-described structure by CVD to form a second interlayer insulating layer 35, and the second interlayer insulating layer 35 is patterned by a photolithography method. A first contact hole 37 exposing the first landing pad 31 is formed.

The diffusion barrier layer 39 in contact with the first landing pad 31 exposed by the first contact hole 37 is deposited by sequentially depositing and heat-treating Ti / TiN, which is a barrier metal, on the second interlayer insulating layer 35. Form. At this time, Ti reacts with Si at the contact interface between the diffusion barrier layer 39 and the first landing pad 31 to form a low resistance layer 41 having a low resistance characteristic made of TiSi 2. The low resistance layer 41 reduces the resistance between the first landing pad 31 and the diffusion barrier layer 39.

Then, a metal such as Co, Ta, Pt, W, or Mo is deposited on the diffusion barrier layer 39 so as to fill the first contact hole 37, and the diffusion barrier layer 39 is also removed by a photolithography method to remove the second interlayer. The insulating layer 35 is patterned to form a bit line 43. At this time, the bit line 43 is formed to fill the first contact hole 37 to be electrically connected to the first landing pad 31 through the diffusion barrier layer 39 and the low resistance layer 41.

Referring to FIG. 1E, silicon oxide or silicon nitride is deposited on the second interlayer insulating layer 35 by CVD to cover the bit line 43 to form a third interlayer insulating layer 45. The third and second insulating layers 45 and 35 are patterned by photolithography to expose the second landing pads 33 to form second contact holes 47 for storage node contacts.

Polycrystalline silicon doped with impurities on the third insulating layer 45 is deposited to contact the second landing pad 33 by filling the second contact hole 47 by the CVD method. The plug 49 is formed by etching or CMPing the deposited polysilicon so that the third interlayer insulating layer 45 is exposed so as to remain only in the second contact hole 47.

As described above, the conventional method of manufacturing a semiconductor device forms a low resistance layer having low resistance when forming the diffusion barrier layer on the first landing pad, thereby reducing the contact resistance between the first landing pad and the bit line.

However, since a low resistance layer is not formed between the second landing pad and the plug, the contact resistance is increased. Therefore, the _TWR (Write Recovery Time), which is a time until data is input during the write operation, is delayed, thereby deteriorating device characteristics. there was.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving device characteristics by reducing the contact resistance between the second landing pad and the plug to shorten the write recovery time (T _WR ).

A method of manufacturing a semiconductor device according to the present invention for achieving the above object is to form a field oxide film defining an active region of a device on a first conductivity type semiconductor substrate, and the gate and cap layer by interposing a gate oxide film on the active region Forming sidewalls on side surfaces of the gate and cap layers, and forming first and second impurity regions of a second conductivity type on exposed portions of the semiconductor substrate and exposing a portion of the active region on the semiconductor substrate. Forming a first interlayer dielectric layer; and filling first polysilicon doped with impurities between the sidewalls on the first interlayer dielectric layer to contact the first and second impurity regions. Forming a first and second low-resistance layers by selectively silicifying the surfaces of the first and second landing pads, and forming the first and second low resistance layers. Forming a second interlayer insulating layer having a first contact hole exposing a first low resistance layer on the insulating layer and contacting the first landing pad through the first contact hole on the second interlayer insulating layer And forming a third insulating layer having a second contact hole covering the bit line and exposing the second low resistance layer on the second interlayer insulating layer, and forming a polycrystal in the second contact hole. And filling the silicon to form a plug.

The first and second low resistance layers are formed by selectively depositing and thermally treating tungsten on the first and second landing pads.

Tungsten is deposited by the LPCVD method at a temperature of 250 to 400 ° C. and a pressure of 100 to 200 mTorr while flowing tungsten with a SiH 4 gas: WF 6 gas at a mixing ratio of 1: 0.5 to 1.0.

In the above, tungsten is deposited to a thickness of 50 to 200 kPa.

In the above, tungsten is silicided by rapid heat treatment at a temperature of 700 to 800 ° C. in an inert gas atmosphere of N 2 or Ar.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are process drawings showing the manufacturing method of the semiconductor device according to the present invention.

Referring to FIG. 2A, a field oxide film 53 is formed on a P-type semiconductor substrate 51 to define an active region in which an element is to be formed. The field oxide film 53 may be formed by the STI method or the LOCOS method.

The gate 60 and the cap layer 61 are formed on the active region of the semiconductor substrate 51 via the gate oxide film 55. The gate oxide film 55 is formed by thermally oxidizing an active region of the semiconductor substrate 51. Then, the polysilicon layer 57, the silicide layer 59, and the cap layer 61 doped with impurities are sequentially stacked on the gate oxide layer 55, and then patterned by a photolithography method including anisotropic etching such as RIE. do. The polysilicon layer 57 and the silicide layer 59 patterned above become the gate 60. The silicide layer 59 is tungsten silicide, and the cap layer 61 is formed by depositing silicon nitride or the like by the CVD method.

Referring to FIG. 2B, silicon oxide having a different etching selectivity from silicon nitride is deposited by a CVD method to cover the gate 60 and the cap layer 61 on the semiconductor substrate 51, and then the semiconductor substrate 51 and the cap layer ( The upper surface of 59 is etched back to form sidewalls 63 on the sides of gate 60 and cap layer 61.

Source and drain regions of the device by ion implanting N-type impurities such as phosphorus (P) or arsenic (As) into the exposed portions of the semiconductor substrate 51 using the cap layer 61 and the sidewall 63 as masks. First and second impurity regions 65 and 67 are formed.

Then, silicon oxide or the like is deposited on the semiconductor substrate 51 by the CVD method to cover the cap layer 61 and the sidewall 63, and the first interlayer insulating layer 69 is formed by planarization by the CMP method. Next, the first interlayer insulating layer 69 is patterned by photolithography to expose a portion of the active region of the semiconductor substrate 51.

Referring to FIG. 2C, polycrystalline silicon doped with impurities is deposited on the first interlayer insulating layer 69 by contact with the first and second impurity regions 65 and 67 by CVD. do. Then, the deposited polysilicon is etched back by RIE method or polished by CMP method to expose the cap layer 61 and contacted with the first and second impurity regions 65 and 67 between the sidewalls 61, respectively. First and second landing pads 71 and 73 are connected to each other. At this time, the first interlayer insulating layer 69 is also etched so that there is no step with the cap layer 61.

Tungsten is selectively deposited and heat-treated on the first and second landing pads 71 and 73 to form first and second low resistance layers 75 and 77 having tungsten silicide (WSix). Form. In the above, the first and second low resistance layers 75 and 77 are LPCVD at a temperature of 250 to 400 ° C. and a pressure of 100 to 200 mTorr while flowing tungsten with a mixing ratio of SiH 4 gas: WF 6 gas at a ratio of 1: 0.5 to 1.0. It is formed by vapor deposition to a thickness of 50 to 200 kPa by rapid heat treatment at a temperature of 700 to 800 ° C. in an inert gas atmosphere such as N 2 or Ar.

Referring to FIG. 2D, silicon oxide or the like is deposited on the entire surface of the above-described structure by CVD to form a second interlayer insulating layer 79, and the second interlayer insulating layer 79 is patterned by photolithography. The first contact hole 81 exposing the first low resistance layer 75 is formed.

The diffusion barrier layer 83 is formed by depositing Ti / TiN, which is a barrier metal, on the second interlayer insulating layer 75 to be in contact with the first landing pad 75 exposed by the first contact hole 81 at a thickness of 300 to 500 Å. ). Then, a metal such as Co, Ta, Pt, W, or Mo is deposited on the diffusion barrier layer 83 to fill the first contact hole 81, and the diffusion barrier layer 83 is also removed by a photolithography method to remove the second interlayer. The bit line 85 is formed by patterning the insulating layer 79 to expose the insulating layer 79. In this case, the bit line 85 is formed to fill the first contact hole 81 to be electrically connected to the first landing pad 71 through the diffusion barrier layer 83 and the first low resistance layer 75. do. Since the first low resistance layer 75 has low resistance, the contact resistance between the first landing pad 71 and the diffusion barrier layer 83 is reduced.

Referring to FIG. 2E, silicon oxide or silicon nitride is deposited on the second interlayer insulating layer 79 by CVD to cover the bit line 85 to form a third interlayer insulating layer 87. The third and second insulating layers 87 and 79 are patterned by photolithography to expose the second low resistance layer 77 to form second contact holes 89 for storage node contacts.

Polycrystalline silicon doped with impurities on the third insulating layer 87 is deposited to contact the second low resistance layer 77 by filling the second contact hole 89 by a CVD method. Then, the third poly interlayer insulating layer 87 is etched back or CMP so that the deposited polysilicon remains only in the second contact hole 89, thereby forming a plug 91 for contacting the storage node.

The plug 91 is electrically connected in contact with a lower electrode (not shown) of a capacitor to be formed thereafter. The second landing pad 73 is formed by the second low resistance layer 77 having a low resistance characteristic. The contact resistance between and is reduced. Second speed because the landing pad 73 and the signal speed faster T _WR (Write Recovery Time) by the contact resistance decrease between the plugs (91) to improve the device characteristics.

As described above, the present invention forms the first and second low resistance layers on the first and second landing pads before forming the second interlayer dielectric layer, so that not only the contact resistance between the first bonding pad and the diffusion barrier layer but also the The contact resistance between the second bonding pad and the plug is also reduced.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Accordingly, the present invention has the advantage to improve the second low by the resistor layer is the signaling rate faster by the contact resistance decrease between the second landing pad and the plug element characteristics because shortening the T _WR (Write Recovery Time) .

1A to 1E are process drawings showing a method for manufacturing a semiconductor device according to the prior art.

2A to 2E are process drawings showing a method of manufacturing a semiconductor device according to the present invention.

Explanation of symbols on the main parts of the drawings

51 semiconductor substrate 53 field oxide film

55 gate oxide film 60 gate

61: cap layer 63: side wall

65, 67 first and impurity regions 69 first interlayer insulating layer

71 and 73: first and second landing pads 75 and 77: first and second low resistance layers

79: second interlayer insulating layer 81: first contact hole

83: diffusion barrier layer 85: bit line

87: third interlayer insulating layer 89: second contact hole

91: plug

Claims (5)

Forming a field oxide film defining an active region of the device on the first conductive semiconductor substrate and forming a gate and a cap layer through the gate oxide layer on the active region; A first interlayer insulating layer having sidewalls formed on side surfaces of the gate and cap layers, forming first and second impurity regions of a second conductivity type in exposed portions of the semiconductor substrate, and exposing a portion of the active region on the semiconductor substrate; Forming a process, Forming first and second landing pads contacting the first and second impurity regions by filling polycrystalline silicon doped with impurities between the sidewalls on the first interlayer insulating layer; Selectively silicifying the surfaces of the first and second landing pads to form first and second low resistance layers; Forming a second interlayer dielectric layer having a first contact hole exposing a first low resistance layer on the first interlayer dielectric layer and the first landing pad through the first contact hole on the second interlayer dielectric layer; Forming a bit line in contact with the; Forming a third insulating layer having a second contact hole covering the bit line and exposing the second low resistance layer on the second interlayer insulating layer and filling a polysilicon in the second contact hole to form a plug; A semiconductor device manufacturing method comprising the step. The method of claim 1, And forming the first and second low resistance layers by selectively depositing and thermally treating tungsten on the first and second landing pads. The method of claim 2, A method of manufacturing a semiconductor device in which the tungsten is deposited by a LPCVD method at a temperature of 250 to 400 ° C. and a pressure of 100 to 200 mTorr while flowing SiH 4 gas: WF 6 gas in a mixing ratio of 1: 0.5 to 1.0. The method of claim 2, A method of manufacturing a semiconductor device, wherein the tungsten is deposited to a thickness of 50 to 200 GPa. The method of claim 2, A method of manufacturing a semiconductor device, wherein the tungsten is silicided by rapid heat treatment at a temperature of 700 to 800 ° C. in an inert gas atmosphere of N 2 or Ar.