KR20050062059A - Method of testing a nand flash memory device - Google Patents

Abstract

The present invention relates to a test method of a NAND flash memory device, and applies a bypass stress by applying a bypass stress voltage of a predetermined level, and then accurately screens a cell in which a defect occurs through a read operation, and provides a margin of stress. It provides a test method for NAND flash memory devices that can be freely wide, can select only cells to be failed, and can fully screen cells, thereby improving product reliability.

Description

Method of testing a NAND flash memory device

The present invention relates to a test method of a NAND flash memory device, and a screen method of a bypass voltage stress fail cell.

Currently, NAND flash memory devices include portable electronic systems such as notebooks, PDAs, and cellular phones, computer BIOSes, printers, and USB drivers. Its use is expanding. The flash memory device is an electronic program / erase capable device that performs program and erase functions by changing the threshold voltage of a cell while electrons are moved by a strong electric field in a thin tunnel oxide film having a predetermined thickness.

In order to program the NAND flash memory device, a voltage of 0 V is applied to a bit line, and a voltage of about 18 V, which is a program voltage Vpgm, is applied to a word line. In addition, a voltage of about 10 V, which is a bypass voltage, is applied to another word line that is not programmed.

Since the distribution of the program cells is between about 1 to 3.5V, the entire cell of the string is turned on, and the transistor for drain selection is also turned on because the supply voltage is applied so that the voltage in the channel maintains the bit line voltage of 0V. do. Thus, the program operation is generated by applying all the program voltages to the cells to be programmed.

In case of bit line not to be programmed, the difference between the bit line to be programmed and the condition is that the bit line voltage is applied to the power supply voltage. This is because as the voltage of all the cells of the string increases, the channel increases due to the voltage applied to the bit line. The voltage of the channel increases to the value of the power supply voltage minus the threshold voltage, and the drain select transistor is turned off to turn off the channel of the string. Becomes a floating state. Tunnel oxide capacitance and ONO capacitance exist between the channel and the control gate, and depletion capacitance exists between the channel and the bulk. The voltage of the channel is boosted and raised by the coupling of the three capacitances. As a result, the string cells of the flash memory device to which the power supply voltage is applied to the bit line are not programmed.

As described above, when the program is to be executed, the threshold voltages of the actual cells are 1 to 3.5V. Therefore, a voltage of about 5V is sufficient because the cells in the string to which the program cells are connected need only be turned on. However, in the case of a non-programmed cell string, that is, a bit line, the channel must be sufficiently boosted, and the boosting level is highly dependent on the bypass voltage. This prevents the bypass voltage from dropping below a certain voltage. Typically a bypass voltage of about 10V is used. However, the F-N tunneling occurs even under this voltage condition, so that the threshold voltage of the erased cell cannot be prevented. In addition, fast program bits are pushed up to the program state, which is one of the most important factors in determining the reliability characteristics of NAND flash memory devices.

An object of the present invention is to increase the bypass stress voltage applied to the gate terminal of the cell to be bypassed, so that the grain fail cell can be tested even under normal read conditions, thereby providing a test method of a NAND flash memory device that can solve the above problems. It is.

A plurality of cell strings in which a plurality of cells are connected in series, a common drain terminal of the cell string, a common source terminal of the cell string, a word line for selecting each cell, and a well of a semiconductor substrate on which the cell is formed A NAND flash memory device comprising: applying a selection voltage to the selected word line, applying a bypass stress voltage to the unselected word lines, applying a power supply voltage to the selected bit lines, Applying a ground voltage to the bit line, applying a ground voltage to the selected word line, applying a pass voltage to the unselected word line, applying a read voltage to the selected bit line, The bit line provides a test method of a NAND flash memory device that floats to test the cell.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

NAND flash memory does not use negative voltage, which does not create a negative voltage path, which is advantageous in layout, and does not form a high voltage PMOS transistor or a high voltage NMOS with a triple well structure, thereby reducing process steps. have. However, since the negative voltage is not used, the negative threshold voltage of the cell cannot be read.

In the case of NAND flash memory, a string structure is used. Cells in a string having the same threshold voltage of the cell have a threshold voltage changed according to a state. Generally, when cells in the same string are programmed, they are read compared to the case of being erased. Even if the cell is in the same state, it should be screened at about 0.5V and should be screened at about -1V considering margin. However, since the negative threshold voltage cannot be read, the current method uses erase confirmation. When reading, a voltage of 4.5V is used to turn on the cells in the pass word line, and when erasing is confirmed, a threshold voltage of less than 0V is sensed by increasing the turn-on resistance of neighboring cells by increasing 0V or 0.5V to the pass word line. to be. In this case, the dependence of the threshold voltage of the neighboring cells is large. That is, if the cells in all strings are at similar threshold voltages, the threshold voltage can be sensed at about -1.2 when the pass word line voltage is 0.5V, but the other cells in the strings are at -2 to -3V, which are all similar. When the threshold voltage is increased by only one cell due to the bypass voltage stress, it is no different from that of reading sensing at about -0.1 to 0V. In addition, gain defects caused by the bypass voltage mainly occur only one bit at a bit in randomness, so the screen itself is almost impossible because there is no difference in the case of reading in most cases.

1 is a conceptual diagram illustrating a test method of a flash memory device according to the present invention.

2 is a graph illustrating a difference of threshold voltages for each bypass stress voltage.

Table 1 is a table of voltages applied during the test operation according to the present invention.

Node Name Select word line Pass Wordline (Pass WL) DSL SSL CSL Selected BL Unselected Bitline (Unselected BL) Bulk Program bias (V) 17-19 11 Vcc 0 Vcc 0 Vcc 0 Lead bias (V) 0 4.5 Vcc Vcc 0 To 1 0

1, 2 and Table 1, a plurality of cell strings in which a plurality of cells are connected in series, a common drain terminal DSL of a cell string, a common source terminal CSL of a cell string, and a cell A NAND flash memory memory device comprising a word line WL for selecting and a well of a semiconductor substrate on which a cell is formed,

Apply a select voltage to the selected word line (Selected WL), apply a bypass stress voltage to the unselected word line (Pass WL), apply a power supply voltage to the selected bit line (Selected BL), and select unselected bits. The ground voltage is applied to the line Unselected BL. At this time, a power supply voltage is applied to the common drain terminal DSL, a ground voltage is applied to the source select line SSL, a power supply voltage is applied to the common source terminal CSL, and a ground voltage is applied to the well bulk. .

Applying a ground voltage to the selected word line (Selected WL), applying a pass voltage to the non-selected word line (Pass WL), applying a read voltage to the selected bit line (Selected BL), the non-selected bit line ( Unselected BL) floats to screen the bypass stress voltage fail cell. As a result, the test yield of the chip can be improved by filtering out only cells having a problem with bypass stress. In this case, a power supply voltage is applied to the common drain terminal DSL, a power supply power is applied to the source select line SSL, a ground voltage is applied to the common source terminal CSL, and a ground voltage is applied to the well bulk. .

The selection voltage is preferably 17 to 19V, the bypass stress voltage is preferably 11 to 12V, the pass voltage is preferably 4.5 to 5.5V, the read voltage is 1 to 2V It is preferable to use a voltage of. It is more preferable to use 18V as the selection voltage, 11V for the bypass stress voltage, 4.5V for the pass voltage, and 1V for the read voltage. The margin of bypass stress voltage can be set freely.

If the threshold voltage changes as the voltage applied to the program (same as the bypass stress) word line while the cells are sufficiently erased due to the program or erase characteristic of the flash memory due to F / N tunneling, the screen is displayed as a read condition. The same effect can be obtained when screening at -1V.

When the bypass stress time is constant due to the characteristics of the NAND flash memory cell, the change of the threshold voltage after the stress causes the change of the bypass voltage. That is, A shows the difference between the threshold voltages after applying the bypass stress voltages of 10V and 11V, respectively, and maintains the same voltage of 1V as the stress voltage difference. The relationship between the distribution (B) of cells after applying 10 V for 10 ms and the distribution (C) of the cell after applying 11 V for 10 ms has a perfect distribution, and only 1 V of a pig value increases. In the case of 11V stress, the threshold voltage is increased by 1V as the distribution is perfectly matched with the case of 10V, so screening the gain cell at 0V under the lead condition has the same effect as filtering the threshold voltage at -V at 10V. Can be reduced.

In the case of NAND flash memory cells, the threshold voltages of the cells vary according to the state of the neighboring cells. Therefore, if the difference is exactly 1V, the threshold voltages of all cells have increased by 1V. Should take to V However, the difference of about 1V of the bypass word line is only about 0.1V of the threshold voltage of the cell, so 4.5V may be used as it is.

As described above, the present invention can apply a bypass stress by applying a bypass stress voltage of a predetermined level, and then accurately screen a cell in which a defect occurs through a read operation.

It is also possible to free the margin of stress.

In addition, only the cells to be failed can be picked out, and the cells can be completely screened, thereby improving the reliability of the product.

1 is a conceptual diagram illustrating a test method of a flash memory device according to the present invention.

2 is a graph illustrating a difference in threshold voltages for each bypass stress voltage.

Claims (2)

A NAND comprising a plurality of cell strings in which a plurality of cells are connected in series, a common drain terminal of the cell string, a common source terminal of the cell string, a word line for selecting each cell, and a well of a semiconductor substrate on which the cell is formed In a flash memory device, Applying a selection voltage to the selected word line, applying a bypass stress voltage to the unselected word lines, applying a power supply voltage to the selected bit lines, and applying a ground voltage to the unselected bit lines ; And A NAND for applying the ground voltage to the selected word line, applying a pass voltage to the unselected word lines, applying a read voltage to the selected bit lines, and plotting the unselected bit lines to test the cell. Test method of flash memory device. The NAND flash memory device of claim 1, wherein the select voltage is 17 to 19 V, the bypass stress voltage is 11 to 12 V, and the pass voltage is 4.5 to 5.5 V. 6. .